JPH0250631B2 - - Google Patents

Abstract

PURPOSE:To ensure a prolonged service life for memory by a method wherein a floating gate type semiconductor memory is provided in an n type Si substrate p well and an erase electrode is provided in a p<+> layer in the well. CONSTITUTION:The SiO2 layer 12 laid on an n type Si substrate 11 is provided with p well covered with an Si3N4 mask and B<+> ion implantation is accomplished for a channel stop feature. Oxidation follows for the formation of a field oxide film 12 and a part thereof is removed for the creation of a 100Angstrom thick SiO2 film 12''. Next, a doped polycrystalline Si film 16 is laid for the creation of an oxide film 17, which is further covered with a doped polycrystalline Si film 18 wherewith a floating gate 16 and a controlling gate 18 are produced with help of a resist mask. The product is covered with an SiO2 film 19, polycrystalline line Si films 20 and 20'' are provided, a p well is ion implanted with the layer 20 as a mask for the creation of an n<+> layer, a p<+> layer is selectively formed, and terminals for an erase line E, a word line W, a bit line B, and wirings for a CMOS are provided. In this construction, zero voltage V is applied to the terminal W at the time of read. Positive voltage here being 5V at the maximum thanks to the insulator film 12'' being extremely thin, information stored remains free of erasure for a prolonged period of time.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in semiconductor memory devices, particularly nonvolatile semiconductor memory devices.

The present applicant disclosed an invention named a nonvolatile semiconductor memory device in patent application No. 182745/1982 (hereinafter referred to as the earlier application) filed on December 25, 1980. Referring to FIG. 1, which shows a cross section of a floating type nonvolatile semiconductor memory device as an embodiment of the present invention, the present invention is a semiconductor device in which a channel region 4 and the only impurity diffusion region 3 adjacent to the channel region 4 are formed. substrate 1, this semiconductor substrate 1
a first insulating film 5 formed on the channel region 4, a floating gate 6 formed on this insulating film 5, a second insulating film 7 formed on this floating gate 6, and a second insulating film 7 formed on this insulating film 5; It is characterized by consisting of a control 8 formed on a membrane 7. In the figure, 1' is a channel stop diffusion layer.

Write and erase operations in such devices utilize tunneling or avalanche breakdown. For example, when injecting electrons from the semiconductor substrate 1 to the floating gate 6 using the tunnel effect, the potential of the bit line terminal B is set to zero, and the potential of the word line terminal W is set to a positive high voltage. .
Further, when the electrons in the floating gate 6 are to be swept to the semiconductor substrate 1, the potential of the bit line terminal B is set to a positive voltage, and the potential of the word line terminal W is set to a negative high voltage.

Next, the reading operation of the apparatus shown in FIG. 1 will be explained. FIGS. 2a and 2b are schematic cross-sectional views for explaining the readout operation of the device shown in FIG. 1, and the channel stop diffusion layer 1' is omitted. Second
Figure a shows a state in which electrons are accumulated in the floating gate 6, and figure b shows a state in which there are no electrons in the floating gate 6. In addition, the second
In figures a and b, the bit line terminal B is left in a floating state, and the word terminal W is supplied with a predetermined positive voltage (however,
(relatively low) is applied.

As shown in FIG. 2a, a small depletion layer 9 exists in the channel region 4 due to the presence of electrons in the floating gate 6, whereas as shown in FIG. In the absence of electrons, a large depletion layer 9' exists in the channel region 4. Therefore, in FIG. 2b, the moment a positive voltage is applied to the word line terminal W, the depletion layer expands, and electrons flow from the impurity diffusion region 3 toward the depletion layer as shown by the arrow X. Therefore, by detecting the current generated in this way, the memory state "1" or "0" can be read.

In such a device, not only during a read operation but also during an erase operation, as described above, the potential of the pit line terminal B is set to a positive voltage, and the potential of the word line terminal W is set to a negative high voltage or an ambient voltage. Therefore, in order to make the potential of bit line terminal B high,
As a result, there is a risk that the electrons will disappear and information will be lost during long-term use.

An object of the present invention is to solve the above-mentioned problems and provide a non-volatile semiconductor memory device that is easy to write and erase electrically and can withstand use for 10 to 20 years. In order to achieve this object, in the semiconductor memory device of the present invention, an element having only one n-type impurity diffusion region is formed in a p-well formed in an n-type substrate, as in the case of the previous application, and The first insulating film, the floating gate, the second insulating film, and the control gate are formed in the same manner as in the device of the prior application, but the first and second insulating films are Although the thickness of the film is the same as in the case of the previous application, the first insulating film is formed on the channel region of the substrate near the field oxide film, that is, in the region separated from the only impurity diffusion region.
It is formed as thin as about 100 Å, and on the opposite side of the field insulating film that is in contact with the channel part, the p
If a high concentration p-type impurity is diffused into the well, an electrode is taken out from the thus formed high concentration p-type impurity diffusion region, and a p-well is formed using this electrode for each bit or word, erasing can be performed for each word. It is used for various purposes.

Embodiments of the semiconductor memory device of the present invention will be described below with reference to the accompanying drawings.

First, a method for manufacturing a semiconductor memory device according to the present invention will be explained with reference to FIG.
As a result, the CMOS circuit has the advantages of low power consumption, high operating speed, and easy low voltage operation.

As shown in FIG. 3, an n-type silicon substrate 11
Silicon dioxide (SiO ₂
An insulating film 12 is grown, and then a photoresist 1 is grown.
Using 3 as a mask, boron (B ⁺ ) is ion-implanted.
Subsequently, this photoresist is removed and heat treatment is performed to form the p-well 14.

Next, a silicon nitride (Si ₃ N ₄ ) film 15 is grown, and then a photoresist 21 is formed, the Si ₃ N ₄ film is patterned, and as shown in ^FIG . Perform typing.

Subsequently, selective oxidation is performed using the Si ₃ N ₄ film 15 to grow a field insulating film 12' (FIG. 3c). At this time, SiO ₂ film 1 which becomes the first insulating film
2 has a film thickness of 700 to 800 [Å]. In the apparatus of the present invention, the portion indicated by 12'' in FIG. 3c is made thinner, so that after the SiO ₂ film is scraped off, this portion is oxidized again to a film thickness of 100 to 120 [Å].

Next, the first layer of polycrystalline silicon (polysilicon) 1 for making a floating gate is formed.
6' is grown on the entire surface, its resistance is reduced by ion implantation, and the entire surface is oxidized to form a second insulating film 17.
A second polysilicon layer 18' is grown on the entire surface,
Similar ion implantation is performed. Then, etching is performed using a mask, as shown in Figure 3d.
On the semiconductor substrate 11, from below, a first insulating film 12 having a thinned portion 12'', a floating gate 16 formed on it, and a second insulating film grown on it. 17. A control gate 18 is formed on this insulating film.An advantage of the device manufacturing method of the present invention is that such a structure can be formed by etching using a single mask.

In the next step, as shown in FIG. 3e, an insulating film 19 is grown by oxidation, polysilicon is grown on it, and the formed polysilicon layer is patterned to form an n ⁺ region. To do this, the polysilicon layer 20' and its drain and source regions are covered, and phosphorus or arsenic is ion-implanted through the insulating film 19 (SiO ₂ film) using the polysilicon layer 20 as a mask.

Further, the p ⁺ region is formed by coating the polysilicon layer 20 and its drain and source regions with a resist and implanting B ⁺ ions using a conventional technique (FIG. 3f).

Finally, erase line terminal E, word line terminal W, bit line terminal B and CMOS terminals are formed (FIG. 3g). In the figure, what is shown to the left of the dashed-dotted line is a semiconductor memory device according to the present invention, and what is shown to the right is a CMOS device.

The write operation of the device of the present invention shown in FIG.
1 to the floating gate 16, the bit line terminal B is grounded to set it to a low (L) level (zero), and the potential of the word line terminal W is set to a high (H) level. At this time, the threshold value V _TH becomes high. If you don't want to write,
When the potentials of both the bit line terminal B and the word line terminal W are set to H level, no electrons are injected, and the threshold value V _TH becomes low.

When you want to erase all bits or words, that is, when you want to sweep the electrons in the floating gate 16 to the semiconductor substrate 11, the potential of the word line terminal W is set to L level (zero), and the potential of the erase line terminal E is set to H level.
level. At this time, the threshold value V _TH is small. When the terminal E is set to H level, the semiconductor substrate under the thinned part 12'' of the first insulating film becomes positive;
It will be appreciated that the electrons in floating gate 16 are swept into the positive portion of this semiconductor substrate by tunneling.

Furthermore, in reading with the device of the present invention, the potential of the erase line terminal E is set to L level, the potential of bit line terminal B is also set to L level, the potential of word line terminal W is set to H level of about 5V, and the potential of bit line terminal B is set to L level. Depending on whether or not electrons are injected under the word line terminal W, that is, under the control gate 17, a potential level is generated at the bit line terminal B, and this is read by a sense amplifier.

In the device of the prior application, as mentioned above, when electrons are injected from the semiconductor substrate to the floating gate, the potential of the pit line terminal W is set to a positive high voltage (for example, about 50 V), and When sweeping out electrons to the semiconductor substrate, the potential of the word line terminal W is set to a negative high voltage or ambient voltage. Thus, in the device of the prior application, the potential of the bit line terminal B is set to a high positive voltage while the word line terminal is at 0V, which can have an undesirable effect on the memory retention time of the device. In the device of the present application, an extremely thin part of about 100 [Å] is formed in the first insulating film 12, but even when the pit wire terminal is set to H level, the voltage is about 5V, as mentioned above. Since no undesirable effects occur, the memory retention time is 10~
Guaranteed to last for 20 years.

As explained above, in the device of the present invention, since the impurity diffusion region is reduced compared to the conventional example, it is possible not only to increase the degree of integration of the device, but also to increase the information retention time, and to reduce the manufacturing cost of the device. This has the effect of being simplified by using CMOS device manufacturing technology.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a floating type non-volatile semiconductor memory device as an embodiment of the invention of the earlier application;
Figures a and b are cross-sectional views for explaining the readout operation of the device of FIG. 1, and figures a to g of FIG. 3 are cross-sectional views of the steps for manufacturing the device of the present invention. 11... Semiconductor substrate, 12... First insulating film,
12'... Field insulating film, 12''... Thinned portion of first insulating film, 13... Photoresist film,
14...P well, 15...Silicon nitride film, 1
6... Floating gate, 17... Second insulating film, 18... Control gate, 19... Insulating film, 20... Polysilicon layer.

Claims (1)

[Claims] 1. A semiconductor substrate in which a channel region and the only impurity diffusion region adjacent to the channel region are formed, a first insulating film formed on the channel region of the semiconductor substrate, and a first insulating film formed on the first insulating film. In a semiconductor memory device comprising a floating gate, a second insulating film formed on the floating gate, and a control gate formed on the second insulating film, the semiconductor memory device has a conductivity opposite to that of the semiconductor substrate. 1. A semiconductor memory, characterized in that the well is formed in a shaped well, a high concentration impurity diffusion region of the same conductivity type as the well is formed, and an electrode for erasing operation is provided in the high concentration impurity diffusion region. Device.