JPH0250499B2 - - Google Patents

Info

Publication number
JPH0250499B2
JPH0250499B2 JP60008077A JP807785A JPH0250499B2 JP H0250499 B2 JPH0250499 B2 JP H0250499B2 JP 60008077 A JP60008077 A JP 60008077A JP 807785 A JP807785 A JP 807785A JP H0250499 B2 JPH0250499 B2 JP H0250499B2
Authority
JP
Japan
Prior art keywords
address
buffer
address translation
processor
flag
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60008077A
Other languages
English (en)
Japanese (ja)
Other versions
JPS61166653A (ja
Inventor
Kazuhiko Ikeda
Naoki Koizumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
PFU Ltd
Original Assignee
PFU Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by PFU Ltd filed Critical PFU Ltd
Priority to JP60008077A priority Critical patent/JPS61166653A/ja
Publication of JPS61166653A publication Critical patent/JPS61166653A/ja
Priority to US07/275,598 priority patent/US4896257A/en
Publication of JPH0250499B2 publication Critical patent/JPH0250499B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Storage Device Security (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
JP60008077A 1985-01-19 1985-01-19 アドレス変換エラー処理方法 Granted JPS61166653A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP60008077A JPS61166653A (ja) 1985-01-19 1985-01-19 アドレス変換エラー処理方法
US07/275,598 US4896257A (en) 1985-01-19 1988-11-23 Computer system having virtual memory configuration with second computer for virtual addressing with translation error processing

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60008077A JPS61166653A (ja) 1985-01-19 1985-01-19 アドレス変換エラー処理方法

Publications (2)

Publication Number Publication Date
JPS61166653A JPS61166653A (ja) 1986-07-28
JPH0250499B2 true JPH0250499B2 (US06826419-20041130-M00005.png) 1990-11-02

Family

ID=11683273

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60008077A Granted JPS61166653A (ja) 1985-01-19 1985-01-19 アドレス変換エラー処理方法

Country Status (2)

Country Link
US (1) US4896257A (US06826419-20041130-M00005.png)
JP (1) JPS61166653A (US06826419-20041130-M00005.png)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2007737C (en) * 1989-02-24 1998-04-28 Paul Samuel Gallo Data transfer operations between two asynchronous buses
US5249297A (en) * 1991-04-29 1993-09-28 Hewlett-Packard Company Methods and apparatus for carrying out transactions in a computer system
US5455834A (en) * 1993-06-14 1995-10-03 Hal Computer Systems, Inc. Fault tolerant address translation method and system
US5893152A (en) * 1996-03-08 1999-04-06 Sun Microsystems, Inc. Method and apparatus that detects and tolerates inconsistencies between the cache and main memory, and the translation lookaside buffer and the virtual memory page table in main memory
US5832205A (en) * 1996-08-20 1998-11-03 Transmeta Corporation Memory controller for a microprocessor for detecting a failure of speculation on the physical nature of a component being addressed
US6199152B1 (en) 1996-08-22 2001-03-06 Transmeta Corporation Translated memory protection apparatus for an advanced microprocessor
US6580431B1 (en) 1999-03-04 2003-06-17 Nexmem System, method, and computer program product for intelligent memory to accelerate processes
US20020135611A1 (en) * 1999-03-04 2002-09-26 Trevor Deosaran Remote performance management to accelerate distributed processes
US6968469B1 (en) 2000-06-16 2005-11-22 Transmeta Corporation System and method for preserving internal processor context when the processor is powered down and restoring the internal processor context when processor is restored
US20080096631A1 (en) * 2004-10-02 2008-04-24 Wms Gaming Inc. Gaming Device With Error Correcting Memory
KR20070118589A (ko) * 2005-02-11 2007-12-17 유니버셜 데이터 프로텍션 코퍼레이션 마이크로프로세서 데이터 보안을 위한 방법 및 시스템
US20070177433A1 (en) * 2005-09-07 2007-08-02 Jean-Francois Poirier Method and system for data security of recording media
US7861042B2 (en) * 2006-10-23 2010-12-28 Hewlett-Packard Development Company, L.P. Processor acquisition of ownership of access coordinator for shared resource
JP5579003B2 (ja) * 2010-09-22 2014-08-27 三菱重工業株式会社 アドレス変換検査装置、中央処理演算装置、及びアドレス変換検査方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3723976A (en) * 1972-01-20 1973-03-27 Ibm Memory system with logical and real addressing
FR130806A (US06826419-20041130-M00005.png) * 1973-11-21
JPS533029A (en) * 1976-06-30 1978-01-12 Toshiba Corp Electronic computer
US4373179A (en) * 1978-06-26 1983-02-08 Fujitsu Limited Dynamic address translation system
US4386402A (en) * 1980-09-25 1983-05-31 Bell Telephone Laboratories, Incorporated Computer with dual vat buffers for accessing a common memory shared by a cache and a processor interrupt stack
US4481573A (en) * 1980-11-17 1984-11-06 Hitachi, Ltd. Shared virtual address translation unit for a multiprocessor system
JPS57138079A (en) * 1981-02-20 1982-08-26 Toshiba Corp Information processor
JPS6047624B2 (ja) * 1982-06-30 1985-10-22 富士通株式会社 アドレス変換制御方式

Also Published As

Publication number Publication date
JPS61166653A (ja) 1986-07-28
US4896257A (en) 1990-01-23

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