JPH02502956A - Semiconductor device and method for manufacturing the device - Google Patents
Semiconductor device and method for manufacturing the deviceInfo
- Publication number
- JPH02502956A JPH02502956A JP50886688A JP50886688A JPH02502956A JP H02502956 A JPH02502956 A JP H02502956A JP 50886688 A JP50886688 A JP 50886688A JP 50886688 A JP50886688 A JP 50886688A JP H02502956 A JPH02502956 A JP H02502956A
- Authority
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- Prior art keywords
- shunt
- collector
- diffused
- well
- oxide region
- Prior art date
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- Pending
Links
- 238000000034 method Methods 0.000 title claims description 26
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 239000004065 semiconductor Substances 0.000 title claims description 18
- 239000000463 material Substances 0.000 claims description 23
- 239000007943 implant Substances 0.000 claims description 12
- 238000002347 injection Methods 0.000 claims description 12
- 239000007924 injection Substances 0.000 claims description 12
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 11
- 229910052785 arsenic Inorganic materials 0.000 claims description 11
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 11
- 229910052698 phosphorus Inorganic materials 0.000 claims description 11
- 239000011574 phosphorus Substances 0.000 claims description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 3
- 150000004767 nitrides Chemical class 0.000 claims 1
- 229920001296 polysiloxane Polymers 0.000 claims 1
- 238000013519 translation Methods 0.000 description 10
- 238000012937 correction Methods 0.000 description 6
- 239000002019 doping agent Substances 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000013459 approach Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 238000009387 deep injection well Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
- H01L21/743—Making of internal connections, substrate contacts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0821—Collector regions of bipolar transistors
Abstract
(57)【要約】本公報は電子出願前の出願データであるため要約のデータは記録されません。 (57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】 半導体装置及びその装置の製造方法 本発明は全般的に半導体装置及びその装置の製造方法に係り、特に、しかしそれ に限るものではないが改良されたバイポーラ装置、特にバイポーラトランジスタ ー、及びそのトランジスタ′−を製造する方法に関する。[Detailed description of the invention] Semiconductor device and method for manufacturing the device TECHNICAL FIELD The present invention relates generally to semiconductor devices and methods of manufacturing the same, and particularly, but not limited to, Improved bipolar devices, especially but not limited to bipolar transistors - and a method of manufacturing the transistor.
知られているＢｉＣＭＯ３（バイポーラ相補型金属−酸化物一半導体）方法で製 造されたバイポーラトランジスターは基本的なバイポーラ構造の電流処理特性に よりその応用範囲が限定されている。この限定はＣＭＯＳ技術の“ウェル”、の みを使用する必要性によって、またそのトランジスターの基本的なスペックが１ ４Ｖの耐圧を持つように要求していることから作られた高コレクターシリーズ抵 抗に基づく。Manufactured using the known BiCMO3 (Bipolar Complementary Metal-Oxide-Semiconductor) method The constructed bipolar transistor follows the current handling characteristics of the basic bipolar structure. The scope of its application is more limited. This limitation is the “well” of CMOS technology. Depending on the need to use the transistor, and the basic specifications of the transistor High collector series resistors are made because they are required to have a withstand voltage of 4V. Based on resistance.
“バイポーラのみ”の技術での通常の装置は高抵抗エミッター−コレクター間通 路の距離を最小にするためバイポーラトランジスターのエミッター下方に“埋没 層”を使用する。Typical devices with “bipolar only” technology have high resistance emitter-collector connections. The emitter of the bipolar transistor is “buried” under the emitter to minimize the path distance. layer”.
これはエミッター−コレクター間抵抗“通路”がＲＩ＋Ｒ１＋Ｒ３である添付第 １図に示されている。This is the attached section where the emitter-collector resistance “path” is RI+R1+R3. This is shown in Figure 1.
このアプローチは主に複雑さとコストの両面での増加と歩留低下をもたらすこと なしには従来のＣλ１０Ｓウェル構造について不可能である。This approach primarily results in increased complexity and cost, as well as reduced yield. This is not possible for conventional Cλ10S well structures without this.
基本的な周知のＢ１ＣＭＯＳバイポーラトランジスターの構造は第２図に示され ている。エミッターからコレクターへの通路（Ｒ＋’ ＋Ｒ，”を含む）が高抵 抗Ｎウェルを横方向に通る第２シスターの耐圧によって決定される。更に、ウェ ルの深さＸる。もしもその深さＸがそれ以上になると、深さＸの増大に伴ない指 数関数的に時間が増加するため製造時間が非常に長時間か＼る。The structure of the basic well-known B1CMOS bipolar transistor is shown in Figure 2. ing. The path from the emitter to the collector (including R+’+R,”) is high-impact. It is determined by the withstand pressure of the second sister passing laterally through the anti-N well. In addition, The depth of the If the depth The manufacturing time is extremely long because the time increases mathematically.
本発明の目的は半導体装置において、エミッターからコレクターへの横方向伝導 路を増加させること、すなわち、ウェルを通しての抵抗路を減少させること、に ある。The purpose of the present invention is to improve lateral conduction from an emitter to a collector in a semiconductor device. to increase the resistance path, i.e. to decrease the resistance path through the well. be.
この目的を達成する１つの可能な方法として逆行するウェルを用いることである 。しかしながら、その逆行するウェルは、極端に制御しにくいものである。その アプローチは基本的にｐ−拡散の補償か特殊な拡散技術かによって表面のピーク 濃度を減少させることである。どちらの場合でもこのアプローチを使用する改良 は非常に限界があり、可変性は受は入れがたいものである。One possible way to achieve this goal is to use retrograde wells. . However, the retrograde well is extremely difficult to control. the The approach is basically to compensate for the surface peaks by compensation of p-diffusion or by special diffusion techniques. The goal is to reduce the concentration. Improvements using this approach in both cases is very limited and variability is unacceptable.
それに代わる第２のアプローチは深い注入ウェルを用いることである。深い注入 技術は抵抗路を実質的に短かくし、その技術は多−メガボルト注入機（３ないし ６ＭｅＶ）を必要とする。貞だその方法のコストと複雑さ及びそれに必要な装置 は現在この技術を受は入れがたく、また不適用になるようにしている。A second alternative approach is to use deep implant wells. deep injection The technique substantially shortens the resistance path, and the technique uses multi-megavolt injectors (3 to 6MeV). The cost and complexity of the method and the equipment required. currently renders this technology unacceptable and inapplicable.
本発明の他の目的はウェルを通しての抵抗路を減少させる他の技術を提供するこ とにある。これは以下“コレクター分路（ｓｈｕｎｔ）、”と呼ばれるものの使 用によって達成される。Another object of the invention is to provide other techniques for reducing the resistance path through the well. It's there. This is the use of what is hereinafter referred to as a “collector shunt.” This is achieved by using
本発明の１つはエミッター、コレクター及びその間の酸化物領域を有する半導体 装置を提供するもので、その酸化物領域の下に拡散された注入材料が配置され、 それによって酸化物領域下の横方向エミッター−コレクター通路の抵抗を減少さ せる。One of the inventions is a semiconductor having an emitter, a collector and an oxide region therebetween. an apparatus in which a diffused implant material is disposed under the oxide region; thereby reducing the resistance of the lateral emitter-collector path under the oxide region. let
本発明はバイポーラＣＭＯＳ装置、特にバイポーラトランジスターの製造に特に 適用される。The present invention is particularly applicable to the manufacture of bipolar CMOS devices, particularly bipolar transistors. Applicable.
分路注入材料（ドーパント）はリン、ヒ素、又はリンとヒ素の混合が好ましい。The shunt implant material (dopant) is preferably phosphorus, arsenic, or a mixture of phosphorus and arsenic.
半導体装置内に拡散されたコレクター分路はエミッターからコレクターへの高濃 度横方向通路を形成する。これは寄生量の増大や、装置の耐性を減少させずにコ レクターの抵抗を著しく減少させる。A collector shunt diffused within a semiconductor device is a high density forming a transverse passageway. This reduces cost without increasing parasitic load or reducing device tolerance. Significantly reduces Rector's resistance.
高濃度分路が酸化物領域を越えて横方向に、より好ましくはコレクターとの隣接 関係に伸びるのがよい。この手段によって横方向伝導路効率が上昇する。High concentration shunts laterally across the oxide region, more preferably adjacent to the collector It's good to grow in relationships. By this measure the lateral conduction path efficiency is increased.
本発明ではまた酸化物領域形成前に、分路が前記酸化物領域用に決められた領域 に注入形成され、そこから拡散せしめられ、それによって前記酸化物領域下方で 横方向のエミッター−コレクター通路の抵抗を減少させる、エミッター、コレク ター及びその間の酸化物領域を有する半導体装置を製造する方法を提供する。The invention also provides that prior to the formation of the oxide region, a shunt is formed in the area defined for the oxide region. is implanted into and diffused from the oxide region, thereby forming a emitter-collector to reduce resistance in the lateral emitter-collector path. A method is provided for manufacturing a semiconductor device having a semiconductor layer and an oxide region therebetween.
本方法の好ましい実施態様によればその方法は分路の注入形成前に、分路注入形 成用の領域の境界を規定するためにシリコン窒化物の堆積を含む。該シリコン窒 化物層を自動レジスターに使用するためにコレクター分路は特にＢ１ＣＭＯＳ技 術に、特にバイポーラトランジスターの製造に好ましい。According to a preferred embodiment of the method, the method includes, prior to implant formation of the shunt, including the deposition of silicon nitride to define the boundaries of the area of growth. The silicon nitride The collector shunt is especially suitable for B1CMOS technology in order to use the compound layer for automatic registers. It is particularly preferred for the production of bipolar transistors.
本発明によればまた イ）基板内にウェルを注入する工程： 口）該ウェル表面にシリコン窒化物をマスク形状に堆積する工程： ハ）該シリコン窒化物によって決められた領域に分路を注入形成する工程： 二）該注入材料をウェル内に拡散する工程：ホ）分路が注入形成された少なくと もその領域上に酸化物層を成長する工程： へ）エミッター、ベース及びコレクターを形成する工程：の各工程を有する半導 体装置を製造する方法が提供される。According to the invention also b) Process of implanting wells into the substrate: (a) Step of depositing silicon nitride in a mask shape on the well surface: C) Implanting a shunt in the region defined by the silicon nitride: 2) Diffusion of the injection material into the well: e) At least one step in which the shunt is formed by injection. The process of growing an oxide layer on that area: f) A semiconductor having the steps of forming an emitter, base and collector: A method of manufacturing a body device is provided.
本発明が十分に理解されるように、本発明に従った半導体装置の製造において基 本的な連続する工程を示す添付図面の第３図ないし第７図をこ＼で参照する。こ れらの連続する工程は実施例のみによって与えられ、変化、追加及び／又は縮少 の問題であることが理解されるはずである。゛またその工程はコレクター分路の 形成に特に関連する方法におけるそれらの工程に集中している半導体装置の一連 の製造工程を示すものでない。In order that the present invention may be fully understood, the basics used in manufacturing a semiconductor device according to the present invention will be explained below. Reference is now made to Figures 3-7 of the accompanying drawings which illustrate the essential sequential steps. child These successive steps are given by way of example only and are subject to variations, additions and/or reductions. It should be understood that this is a problem.゛The process also includes the collector branch A series of semiconductor devices concentrating on those steps in methods specifically related to their formation It does not indicate the manufacturing process.
第３図ないし第７図はＢｉＣＩＪＯＳ工程でコレクター分路の形成を示すが本発 明に係るコレクター分路の形成はその方法に限定されず、特に酸化物領域がシリ コン窒化物で規定される、ロコス法を用いながら製造した他の半導体装置で使用 できることも理解されよう。Figures 3 to 7 show the formation of collector shunts in the BiCIJOS process, but the present invention The formation of collector shunts according to Used in other semiconductor devices manufactured using the Locos method specified by Con-Nitride I hope you understand what you can do.
まず第３図によれば、これはシリコン酸化物層１２が堆積されるＰ導電型材料の 基板１０を示す。酸化物層１２内のギャップ内にウェルを形成するＮ導電型が注 入された材料１４がある。First, according to FIG. 3, this is the P conductivity type material on which the silicon oxide layer 12 is deposited. A substrate 10 is shown. The N conductivity type forming a well within the gap in the oxide layer 12 is injected. There is material 14 inserted.
ウェル注入形成は第４図に示されるように“拡がり”ウェル１６を形成し、その 後、シリコン窒化物１８を、ギャップ２０を規定する所定のマスク形状の層とし てウェル表面上に堆積する。Well implantation forms a "spread" well 16 as shown in FIG. Afterwards, the silicon nitride 18 is formed into a layer with a predetermined mask shape defining the gap 20. and deposited on the well surface.
第５図に示すように、次にレジストマスク２２を堆積する。As shown in FIG. 5, a resist mask 22 is then deposited.
次に自動レジスタ一層としてシリコン窒化物層１８を用いながら、分路ドーパン ト材料２４を、シリコン窒化物層で規定されたギャップ２０内でウェル１６に注 入する。この分路ドーパント面に記載されている分路ドーパント材料２４はリン とヒ素の組合せである。別にその材料はリンのみでもよくまたヒ素のみでもよい 。１０”／ｃＪ個の原子のオーダーの濃度がリン注入の場合に好ましいことが見 出された。ヒ素注入の場合１０”／ｄ個の原子の濃度が好ましい。Next, using the silicon nitride layer 18 as an auto-resistor layer, the shunt dopant is A material 24 is poured into the well 16 within the gap 20 defined by the silicon nitride layer. Enter. The shunt dopant material 24 written on this shunt dopant surface is phosphorus. and arsenic. In particular, the material may be only phosphorus or only arsenic. . It has been found that concentrations on the order of 10”/cJ atoms are preferred for phosphorus implants. Served. For arsenic implants, a concentration of 10''/d atoms is preferred.
第６図に示すように、分路ドーパント注入部２４を次に好ましくは２．５ミクロ ンのオーダーの深さに拡げ約４．５ミクロン深さのウェルにする。注入部の拡大 は一般に２６で示された高濃度領域をウェル内にそしてシリコン窒化物層下の横 側にも拡散させる。第６図に示すように、ドーパント材料がリンとヒ素の混合物 である場合、分路領域２６はリンが実質的容積２８を越えて延びるように拡散し 、一方ヒ素の場合は分路領域先端のバンド３０内である。As shown in FIG. 6, the shunt dopant implant 24 is then preferably 2.5 microns thick. The wells are approximately 4.5 microns deep. Enlargement of injection part The high concentration region generally designated 26 is placed within the well and laterally below the silicon nitride layer. Spread it on the sides as well. As shown in Figure 6, the dopant material is a mixture of phosphorus and arsenic. , the shunt region 26 diffuses the phosphorus so that it extends beyond the substantial volume 28. , while for arsenic, it is within the band 30 at the tip of the shunt region.
拡散の後、フィールド酸化物３２は該装置の表面に、特に該分路領域上方にそし てウェル１６の端部上に成長する。After diffusion, field oxide 32 is deposited on the surface of the device, particularly over the shunt area. and grows on the edge of well 16.
第７図は本装置の製造が完成した段階を示す。これは第６図に示された段階から シリコン窒化物層を除去し、コレクター３４、エミッター３６及びベース３８を 作ることによって達成される。エミッター３６は多結晶シリコンが好ましい。エ ミッターからコレクターへの電流方向は第７図に矢印４０で示されている。酸化 物３２下のエミッターからコレクターの横方向通路は高濃度コレクター分路２６ を介しているのでこの通路の抵抗は実質的に減少せしめられる。第７図から明ら かなように、拡散された注入分路材料はその上方にある酸化物３２を越えて、実 際コレクター３４と接触するところ迄、横方向に伸びている。FIG. 7 shows the completed stage of manufacturing the device. This starts from the stage shown in Figure 6. Remove the silicon nitride layer and remove the collector 34, emitter 36 and base 38. This is achieved by making. Emitter 36 is preferably polycrystalline silicon. workman The direction of current flow from the emitter to the collector is indicated by arrow 40 in FIG. oxidation The lateral passage from the emitter under the object 32 to the collector is the high concentration collector shunt 26. , the resistance of this path is substantially reduced. It is clear from Figure 7 As shown, the diffused injection shunt material extends beyond the overlying oxide 32 and into the actual It extends laterally until it comes into contact with the collector 34.
これによってウェル１６の材料を通して電流通路長さを最小にすることができる 。This allows the current path length to be minimized through the material of the well 16. .
本発明に係るコレクター分路を有するバイポーラトランジスターは、システムア レイとディジタルアレイにおいて特定の応用がなされる。The bipolar transistor with collector shunt according to the present invention Particular applications are found in rays and digital arrays.
コレクター分路技術がウェルを通る抵抗路を減少させることに実質的に利点をも たらすが逆行するウェル技術や上で説明した深い注入ウェル技術と組合わせるこ とができると認識されよう。特に、コレクター分路技術は、深い注入ウェル技術 が利用しやすく工業的に可能であればその技術と共に用いることが適当である。Collector shunt technology also has a substantial advantage in reducing the resistance path through the well. This can be combined with the retrograde well technique and the deep injection well technique described above. It will be recognized that it can be done. In particular, the collector shunt technology is a deep injection well technology. If it is easy to use and industrially possible, it is appropriate to use it together with that technology.
浄書（内容に変更なし） ＦＩＧ、１． （先行技術） ＦＩＧ、２． （先行技術） 手続補正書（方式） ％式％ １、事件の表示 ＰＣＴ／ＧＢ８８１００９９６ ２ 発明の名称 半導体装置及びその装置の製造方法 ３、補正をする者 。Engraving (no changes to the content) FIG. 1. (Prior art) FIG.2. (Prior art) Procedural amendment (formality) %formula% 1.Display of the incident PCT/GB88100996 2 Name of the invention Semiconductor device and method for manufacturing the device 3. Person who makes corrections.
事件との関係 特許出願人 名称 エルニスアイ ロジック ニアラブ」 住所 〒１０５東京都港区虎ノ門−丁目８番１０号静光虎ノ門ビル 電話５０４ −０７２１５、補正命令の日付 平成２年４月３日（発送日） ６、補正の対象 （１）特許法第１８４条の５第１項の規定′による書面の「特許出願人の代表者 」の欄 （２）委任状 （３）明細書の翻訳文 （４）請求の範囲の翻訳文 ７、補正の内容 （１）（２） 別紙の通り （３）明細書の翻訳文の浄書（内容に変更なし）（４）請求の範囲の翻訳文の浄 書（内容に変更なし）８、添付書類の目録 （１）訂正した特許法第１８４条の５ 第１項の規定による書面 １通（２）委任状及びその翻訳文 各１通（３）明細書の翻訳文 １通（４）請求の範囲の 翻訳文 ト通手続補正書（方式） 平成２年６月２ｚ日 特許庁長官 吉 １）文 毅 殿 １、事件の表示 ＰＣＴ／ＧＢ８８１００９９６ ２、 発明の名称 半導体装置及びその装置の製造方法 ３、補正をする者 事件との関係 特許出願人 名称 エルニスアイ ロジック ニアラブパブリック リミティド カンパニー ４、代理人 住所 〒１０５東京都港区虎ノ門−丁目８番１ｏ号静光虎ノ門ビル 電話５０４ −０７２１５、補正の対象 図面の翻訳文 ６、補正の内容 図面の翻訳文の浄書（内容に変更なし）７、添付書類の目録 図面の翻訳文 各１通国際調査報告 Ｉｍｓ＋ｍカ１１−＾−ｍｔａ”” ＰＣＴ／ＧＢ ８８１００９９６Ｉ際 調査報告Relationship to the incident Patent applicant Name: Ernis Eye Logic: Near Love” Address: Shizuko Toranomon Building, 8-10 Toranomon-chome, Minato-ku, Tokyo 105 Phone: 504 -07215, date of correction order April 3, 1990 (shipment date) 6. Subject of correction (1) In accordance with the provisions of Article 184-5, Paragraph 1 of the Patent Law ” column (2) Power of attorney (3) Translation of the specification (4) Translation of the scope of claims 7. Contents of correction (1) (2) As per attached sheet (3) Translation of the specification (no change in content) (4) Translation of the scope of claims (No change in content) 8. List of attached documents (1) Amended Article 184-5 of the Patent Act Document pursuant to the provisions of paragraph 1 1 copy (2) Power of attorney and its translation 1 copy each (3) Translation of the specification 1 copy (4) Translation of the scope of claims translated text June 2z, 1990 Yoshi, Commissioner of the Patent Office 1) Takeshi Moon 1.Display of the incident PCT/GB88100996 2. Name of the invention Semiconductor device and method for manufacturing the device 3. Person who makes corrections Relationship to the case Patent applicant Name Elnis Eye Logic Near Love Public Limited Company 4. Agent Address: Shizuko Toranomon Building, No. 8-1o, Toranomon-chome, Minato-ku, Tokyo 105 Phone: 504 -07215, subject of correction translation of the drawing 6. Contents of amendment Engraving of the translation of the drawing (no change in content) 7. List of attached documents Translation of drawing 1 Each international survey report Ims+mka11-^-mta"" PCT/GB 88100996I Investigation report
Claims (18)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB878726367A GB8726367D0 (en) | 1987-11-11 | 1987-11-11 | Cmos devices |
| GB8726367 | 1987-11-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02502956A true JPH02502956A (en) | 1990-09-13 |
Family
ID=10626764
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP50886688A Pending JPH02502956A (en) | 1987-11-11 | 1988-11-11 | Semiconductor device and method for manufacturing the device |
Country Status (5)
| Country | Link |
|---|---|
| EP (1) | EP0346409A1 (en) |
| JP (1) | JPH02502956A (en) |
| AU (1) | AU2620888A (en) |
| GB (2) | GB8726367D0 (en) |
| WO (1) | WO1989004555A1 (en) |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3648125A (en) * | 1971-02-02 | 1972-03-07 | Fairchild Camera Instr Co | Method of fabricating integrated circuits with oxidized isolation and the resulting structure |
| US4283236A (en) * | 1979-09-19 | 1981-08-11 | Harris Corporation | Method of fabricating lateral PNP transistors utilizing selective diffusion and counter doping |
| JPS5931052A (en) * | 1982-08-13 | 1984-02-18 | Hitachi Ltd | Semiconductor ic device and manufacture thereof |
| JPS61164262A (en) * | 1985-01-17 | 1986-07-24 | Toshiba Corp | Semiconductor device |
-
1987
- 1987-11-11 GB GB878726367A patent/GB8726367D0/en active Pending
-
1988
- 1988-11-11 AU AU26208/88A patent/AU2620888A/en not_active Abandoned
- 1988-11-11 GB GB8915454A patent/GB2219137B/en not_active Expired - Fee Related
- 1988-11-11 EP EP19880909569 patent/EP0346409A1/en not_active Withdrawn
- 1988-11-11 JP JP50886688A patent/JPH02502956A/en active Pending
- 1988-11-11 WO PCT/GB1988/000996 patent/WO1989004555A1/en not_active Application Discontinuation
Also Published As
| Publication number | Publication date |
|---|---|
| GB8915454D0 (en) | 1989-08-23 |
| GB2219137B (en) | 1990-10-24 |
| EP0346409A1 (en) | 1989-12-20 |
| GB8726367D0 (en) | 1987-12-16 |
| WO1989004555A1 (en) | 1989-05-18 |
| GB2219137A (en) | 1989-11-29 |
| AU2620888A (en) | 1989-06-01 |
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