EP0346409A1 - Bipolar transistor devices and methods of making the same - Google Patents

Bipolar transistor devices and methods of making the same

Info

Publication number
EP0346409A1
EP0346409A1 EP19880909569 EP88909569A EP0346409A1 EP 0346409 A1 EP0346409 A1 EP 0346409A1 EP 19880909569 EP19880909569 EP 19880909569 EP 88909569 A EP88909569 A EP 88909569A EP 0346409 A1 EP0346409 A1 EP 0346409A1
Authority
EP
European Patent Office
Prior art keywords
implant
shunt
collector
emitter
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19880909569
Other languages
German (de)
French (fr)
Inventor
Peter Fred Blomley
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LSI Logic Europe Ltd
Original Assignee
LSI Logic Europe Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LSI Logic Europe Ltd filed Critical LSI Logic Europe Ltd
Publication of EP0346409A1 publication Critical patent/EP0346409A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0821—Collector regions of bipolar transistors

Definitions

  • This invention relates generally to semiconductor devices and to methods of making such' devices, and is .particularly but not exclusively concerned with improved bipolar devices, especially bipolar transistors, and a method of making the same.
  • bipolar complementary metal-oxide-semi ⁇ onductor processes are limited in their range of application by the current handling characteristics of the basic bipolar structure. This limitation is due to the high collector series resistance created by t e need to use only the "wells" of a CMOS technology device and also by virtue of the fact that the basic specification of., the transistor requires it to have a breakdown voltage of 14 V. Normal devices in "bipolar only” technologies use "buried layers" under the emitter of the bipolar transistor in order to minimise the length of the high resistance emitter-to-collector path. This ' is illustrated in Fig. 1 of the accompanying drawings, where the emitter-to-collector resistance "path" is R-
  • Fig.2 The structure of the basic known BiCMOS bipolar transistor is shown in Fig.2. It will be apparent from Fig. 2 that the path from the emitter to the collector, comprising R-j * + R-
  • the resistivity of the well is determined by the breakdown voltage of the bipolar resistor.
  • the depth x of the well is also fixed by the CMOS constraints, at for instance 4.5 microns or less. If the depth x is made any greater than this, then the device takes too long to fabricate because the time increases exponentially, with an increase in the depth x.
  • •It is an object of the present invention, in a semiconductor device, to increase the lateral conduction path efficiency from the emitter to the collector, i.e. to reduce the resistance path through the well.
  • ⁇ approach is to reduce the peak surface concentration by either compensation with a P-diffusion or a special diffusion technique. In either case the improvement using this approach is very marginal and the variability is unacceptable.
  • a second alternative approach is to use deep implant wells.
  • the deep implant technique can give a substantial reduction in the resistance path, but the technique requires a multi-megavolt implanter (3 to 5 MeV) . Also, the cost and complexity of the process and the availability of the necessary apparatus is at . present such as to make this technique unacceptable and/or unavailable.
  • collector shunt It is an object of the present invention to provide an alternative technique for reducing the resistance path, through the well. This is achieved by the use of what is hereinafter referred to as a "collector shunt".
  • a semiconductor device comprising an emitter, a collector and an oxide region therebetween. wherein a shunt comprising a diffused implant is located below said oxide region thereby to reduce the resistance of the lateral emitter-to-collector path beneath said oxide region.
  • the invention is particularly appropriate in the manufacture of bipolar CMOS devices, especially bipolar transistors.
  • the shunt implant is preferably of phosphorus, of arsenic, or of a mixture of phosphorus and arsenic.
  • the collector shunt diffused into the semiconductor device creates a high concentration lateral path from emitter to collector. This dramatically reduces the resistance of the collector without any increase in parasitics, and without reducing the breakdown performance of the device.
  • the high concentration shunt extends laterally beyond the oxide region, and preferably into contiguous relationship with the collector. By this means one achieves an increase in the lateral conduction path efficiency.
  • a method of manufacturing a semiconductor device having an emitter, a collector and an oxide region therebetween in which, prior to the creation of said oxide region, a shunt is implanted in the region determined for said oxide region and is diffused therefrom, thereby to reduce the resistance of the lateral emitter-to-collector path beneath said oxide region.
  • the method includes, prior to the implantation of the shunt, the deposition of silicon nitride to define the boundary of the area for the shunt implant.
  • the use of a silicon nitride layer to auto-register a bipolar colle.ctor shunt is particularly advantageous. especially in BiCMOS technology, particularly for the manufacture of bipolar transistors.
  • a method of manufacturing a semiconductor device which comprises the steps of: a) implanting a well into a substrate; b) depositing silicon nitride on the well, surface in a masking configuration; c) implanting a shunt in a region determined by the silicon nitride; d) diffusing the implant into the well; e) growing an oxide layer on the device over at least the region where the shunt was implanted; and, f) creating an emitter, a base and a collector.
  • Figures 3 to 7 illustrate the provision of a collector shunt in a BiCMOS process
  • the provision of a collector shunt in accordance with the invention is not limited to such processes and could be embodied in any other semiconductor device manufactured using a LOCOS process, especially where the oxide regions are defined by silicon nitride.
  • Fig. 3 shows a substrate 10 of P conductivity material on which is deposited a silicon oxide layer 12.
  • a silicon oxide layer 12 Within a gap in the oxide layer 12 is implanted material 14 of N conductivity type which is to constitute a well.
  • the well implant is "driven in" as shown in Fig.
  • a shunt dopant material 24 is implanted in the well 16 within the gap 20 defined by the silicon nitride layer.
  • This shunt dopant material is a heavy, i.e. high concentration, implant (N+) .
  • the shunt dopant material 24 which is illustrated in the drawings is a combination of phosphorus and arsenic.
  • the material can be phosphorus alone, or yet again can be arsenic alone.
  • a concentration of the order of 10 * 13 atoms per cm2 has been found to be acceptable in the case of a phosphorus implant.
  • a concentration of 10 14 atoms per cm2 is preferred.
  • the shunt dopant implant 24 is then driven in, preferably to a depth of the order of 2.5 microns with a well of about 4.5 microns depth.
  • This driving in of the implant causes the high concentration region, indicated generally at 26, to diffuse down into the well and also sideways under the silicon nitride layer.
  • the dopant material is a mixture of phosphorus and arsenic
  • Fig. 7 shows the stage where fabrication of the device is complete. This is achieved, from the stage shown in Fig. 6, by removing the silicon nitride layer, and- b creating a collector 34, an emitter 36 and a base 38.
  • the emitter 36 is preferably of polysilicon.
  • the shunt material of the diffused implant extends laterally beyond the oxide region 32 which is above it, and indeed into contact with the collector 34. This helps to minimise the
  • Bipolar transistors in accordance with the present invention incorporating a collector shunt find particular application in systems arrays and in digital
  • collector shunt technique provides subst ant ia l advantages in terms of reducing the resistance path through the wel l , it can be combined wi th the
  • the collector shunt technique is appropriate to be used with the deep implant well technique if and when the latter becomes available and commercially viable.

Abstract

A semiconductor device, preferably a bipolar CMOS device such as a bipolar transistor, comprising an emitter (36) and a collector (34) with an oxide region (32) therebetween, is provided with a collector shunt (26) in the form of a high concentration diffused implant below the oxide region (32), thereby to reduce the resistance of the emitter-to-collector path. The implant may be of phosphorous and/or arsenic. In a process for manufacturing such a device, silicon nitride is deposited on the well surface to define the boundary of the area for the shunt implant.

Description

Bipolar transistor devices and methods of making- the same. SPECIFICATION
This invention relates generally to semiconductor devices and to methods of making such' devices, and is .particularly but not exclusively concerned with improved bipolar devices, especially bipolar transistors, and a method of making the same. The bipolar transistors produced in known BiCMOS
(bipolar complementary metal-oxide-semiσonductor) processes are limited in their range of application by the current handling characteristics of the basic bipolar structure. This limitation is due to the high collector series resistance created by t e need to use only the "wells" of a CMOS technology device and also by virtue of the fact that the basic specification of., the transistor requires it to have a breakdown voltage of 14 V. Normal devices in "bipolar only" technologies use "buried layers" under the emitter of the bipolar transistor in order to minimise the length of the high resistance emitter-to-collector path. This' is illustrated in Fig. 1 of the accompanying drawings, where the emitter-to-collector resistance "path" is R-| + R2 + R3.
This approach is not possible with a conventional CMOS well structure without incurring a major increase in both complexity and cost and a significant decrease in yield.
The structure of the basic known BiCMOS bipolar transistor is shown in Fig.2. It will be apparent from Fig. 2 that the path from the emitter to the collector, comprising R-j * + R-| ' ' , is lateral through the high resistance N well. The resistivity of the well is determined by the breakdown voltage of the bipolar resistor. Additionally, the depth x of the well is also fixed by the CMOS constraints, at for instance 4.5 microns or less. If the depth x is made any greater than this, then the device takes too long to fabricate because the time increases exponentially, with an increase in the depth x.
•It is an object of the present invention, in a semiconductor device, to increase the lateral conduction path efficiency from the emitter to the collector, i.e. to reduce the resistance path through the well.
One possible way of achieving this would be to use a retrograde well. However, the retrograde well is extremely difficult to control. Basically, the
■ approach is to reduce the peak surface concentration by either compensation with a P-diffusion or a special diffusion technique. In either case the improvement using this approach is very marginal and the variability is unacceptable.
A second alternative approach is to use deep implant wells. The deep implant technique can give a substantial reduction in the resistance path, but the technique requires a multi-megavolt implanter (3 to 5 MeV) . Also, the cost and complexity of the process and the availability of the necessary apparatus is at . present such as to make this technique unacceptable and/or unavailable.
•• It is an object of the present invention to provide an alternative technique for reducing the resistance path, through the well. This is achieved by the use of what is hereinafter referred to as a "collector shunt".
In accordance with one aspect of the invention there is provided a semiconductor device comprising an emitter, a collector and an oxide region therebetween. wherein a shunt comprising a diffused implant is located below said oxide region thereby to reduce the resistance of the lateral emitter-to-collector path beneath said oxide region. The invention is particularly appropriate in the manufacture of bipolar CMOS devices, especially bipolar transistors.
The shunt implant is preferably of phosphorus, of arsenic, or of a mixture of phosphorus and arsenic. The collector shunt diffused into the semiconductor device creates a high concentration lateral path from emitter to collector. This dramatically reduces the resistance of the collector without any increase in parasitics, and without reducing the breakdown performance of the device.
Preferably, the high concentration shunt extends laterally beyond the oxide region, and preferably into contiguous relationship with the collector. By this means one achieves an increase in the lateral conduction path efficiency.
Also in accordance with the invention there is provided a method of manufacturing a semiconductor device having an emitter, a collector and an oxide region therebetween, in which, prior to the creation of said oxide region, a shunt is implanted in the region determined for said oxide region and is diffused therefrom, thereby to reduce the resistance of the lateral emitter-to-collector path beneath said oxide region. According to a preferred embodiment of this method, the method includes, prior to the implantation of the shunt, the deposition of silicon nitride to define the boundary of the area for the shunt implant. The use of a silicon nitride layer to auto-register a bipolar colle.ctor shunt is particularly advantageous. especially in BiCMOS technology, particularly for the manufacture of bipolar transistors.
Also in accordance with the invention there is provided a method of manufacturing a semiconductor device which comprises the steps of: a) implanting a well into a substrate; b) depositing silicon nitride on the well, surface in a masking configuration; c) implanting a shunt in a region determined by the silicon nitride; d) diffusing the implant into the well; e) growing an oxide layer on the device over at least the region where the shunt was implanted; and, f) creating an emitter, a base and a collector. In order that the invention may be fully understood reference is now made to Figures 3 to 7 of the accompanying drawings which show the basic sequence of steps in the creation of a semiconductor device in accordance with the invention. It is to be understood that these sequence steps are given by way of example only and are subject to variation, addition and/or subtraction. Also, they do not show every step in the sequence of manufacturing the semiconductor device, concentrating on those steps in the process which are especially relevant to the. provision of the collector shunt.
It should also be understood that although Figures 3 to 7 illustrate the provision of a collector shunt in a BiCMOS process, the provision of a collector shunt in accordance with the invention is not limited to such processes and could be embodied in any other semiconductor device manufactured using a LOCOS process, especially where the oxide regions are defined by silicon nitride. Referring first to Fig. 3, this shows a substrate 10 of P conductivity material on which is deposited a silicon oxide layer 12. Within a gap in the oxide layer 12 is implanted material 14 of N conductivity type which is to constitute a well. . The well implant is "driven in" as shown in Fig. 4 to create a well 16 and, thereafter, silicon nitride 18 is deposited on the well surface as a layer in a desired masking configuration which defines a gap 20. As shown in Fig. 5, a resist mask 22 is then deposited. Next, using the silicon nitride layer 18 as an auto-registering layer, a shunt dopant material 24 is implanted in the well 16 within the gap 20 defined by the silicon nitride layer. This shunt dopant material is a heavy, i.e. high concentration, implant (N+) . ' The shunt dopant material 24 which is illustrated in the drawings is a combination of phosphorus and arsenic. Alternatively, the material can be phosphorus alone, or yet again can be arsenic alone. A concentration of the order of 10*13 atoms per cm2 has been found to be acceptable in the case of a phosphorus implant. In the case of an arsenic implant a concentration of 1014 atoms per cm2 is preferred.
As shown in Fig. 6, the shunt dopant implant 24 is then driven in, preferably to a depth of the order of 2.5 microns with a well of about 4.5 microns depth. This driving in of the implant causes the high concentration region, indicated generally at 26, to diffuse down into the well and also sideways under the silicon nitride layer. As shown in Fig. 6, the shunt region 26, in the case where the dopant material is a mixture of phosphorus and arsenic, diffuses in such a way that the phosphorus extends over a substantial volume 28, -whereas the arsenic is concentrated, towards the top of the shunt region, in a band 30. Again as shown in Fig. 6, after the diffusion of the collector shunt into the well, field oxide 32 is "grown" on the surface of the device, in particular over the shunt region and over the edges of the well 16. 5 Fig. 7 shows the stage where fabrication of the device is complete. This is achieved, from the stage shown in Fig. 6, by removing the silicon nitride layer, and- b creating a collector 34, an emitter 36 and a base 38. The emitter 36 is preferably of polysilicon.
10 The direction of current flow from the emitter 36 to
■ the collector 34 is indicated in Fig. 7 by the arrows
40. Because the lateral path from the emitter to the collector below the oxide 32 is through the high concentration collector shunt 26, the resistance of
15 this path is substantially reduced. As will be apparent from Fig. 7 , the shunt material of the diffused implant extends laterally beyond the oxide region 32 which is above it, and indeed into contact with the collector 34. This helps to minimise the
2.0 length of the current flow path through the material of the well 16.
Bipolar transistors in accordance with the present invention incorporating a collector shunt find particular application in systems arrays and in digital
25 arrays.
It should also be appreciated that although the collector shunt technique provides subst ant ia l advantages in terms of reducing the resistance path through the wel l , it can be combined wi th the
30 retrograde well technique or with the deep implant well technique referred to above . In parti cular , the collector shunt technique is appropriate to be used with the deep implant well technique if and when the latter becomes available and commercially viable.
35

Claims

CLAIMS :
1. A semiconductor device comprising an emitter, a collector and an oxide region therebetween, wherein a shunt comprising a diffused implant is located below said oxide region, thereby to reduce the resistance of the lateral emitter-to-collector path beneath said oxide region.
2. A device according to claim 1, which is a bipolar CMOS device.
3. A device according to claim 2, which is a bipolar transistor.
4. A device according to any preceding claim, in which the shunt implant is of phosphorus.
5. A device according to any of claims 1 to 3, in which the shunt implant is of arsenic.
6. A device according to any of claims 1 to 3, in which the shunt implant comprises phosphorus and arsenic.
7. A device according to claim 4, in which the phosphorus implant has a concentration of the order of
10*13 atoms per cm2.
8. A device according to claim 5, in which the arsenic has a concentration of the order of 10*14 atoms per cm^.
9. A device according to any preceding claim, in which the implant is diffused to a depth of the order of 2.5 microns.
10. A device according to any preceding claim, in which the implant is diffused into a well which is formed below the emitter, the collector and the oxide region.
11. A device according to any preceding claim, in which the material of the diffused implant extends laterally beyond said oxide region.
12. A device according to claim 11, in which the material of the diffused implant extends into contiguous relationship with the collector.
13. A method of manufacturing a semiconductor device having an emitter, a collector and an oxide region therebetween, in which, prior to the creation of said oxide region, a shunt is implanted in the region determined for said oxide -region and is diffused therefrom, thereby to reduce the resistance of the lateral emitter-to-collector path beneath said oxide region.
14. A method according to claim 13, which includes, prior to the implantation of the shunt, the deposition of ■silicon nitride to define the boundary of the area for the shunt implant.
15. A method according to claim 13 or 14, for the manufacture of a bipolar CMOS device.
16. A method according to claim 13 or 14, for the manufacture of a bipolar transistor.
17. A method according to any of claims 13 to 16, in which the shunt implant is of phosphorus and/or arsenic.
18. A method of manufacturing a semiconductor device which comprises the steps of: a) implanting a well into a substrate; b) depositing silicon nitride on the well surface in a masking configuration; c) implanting a shunt in a region determined by the silicon nitride; d) diffusing the implant into the well; e) growing an oxide layer on the device over at least the region where the shunt was implanted; and, f) creating an emitter, a base and a collector.
EP19880909569 1987-11-11 1988-11-11 Bipolar transistor devices and methods of making the same Withdrawn EP0346409A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB878726367A GB8726367D0 (en) 1987-11-11 1987-11-11 Cmos devices
GB8726367 1987-11-11

Publications (1)

Publication Number Publication Date
EP0346409A1 true EP0346409A1 (en) 1989-12-20

Family

ID=10626764

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19880909569 Withdrawn EP0346409A1 (en) 1987-11-11 1988-11-11 Bipolar transistor devices and methods of making the same

Country Status (5)

Country Link
EP (1) EP0346409A1 (en)
JP (1) JPH02502956A (en)
AU (1) AU2620888A (en)
GB (2) GB8726367D0 (en)
WO (1) WO1989004555A1 (en)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3648125A (en) * 1971-02-02 1972-03-07 Fairchild Camera Instr Co Method of fabricating integrated circuits with oxidized isolation and the resulting structure
US4283236A (en) * 1979-09-19 1981-08-11 Harris Corporation Method of fabricating lateral PNP transistors utilizing selective diffusion and counter doping
JPS5931052A (en) * 1982-08-13 1984-02-18 Hitachi Ltd Semiconductor ic device and manufacture thereof
JPS61164262A (en) * 1985-01-17 1986-07-24 Toshiba Corp Semiconductor device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO8904555A1 *

Also Published As

Publication number Publication date
JPH02502956A (en) 1990-09-13
GB8915454D0 (en) 1989-08-23
GB2219137B (en) 1990-10-24
GB8726367D0 (en) 1987-12-16
WO1989004555A1 (en) 1989-05-18
GB2219137A (en) 1989-11-29
AU2620888A (en) 1989-06-01

Similar Documents

Publication Publication Date Title
JP4780709B2 (en) Complementary bipolar transistor having high early voltage, high frequency performance and high breakdown voltage characteristics and method of manufacturing the same
US5034337A (en) Method of making an integrated circuit that combines multi-epitaxial power transistors with logic/analog devices
CA1282872C (en) Circuit containing integrated bipolar and complementary mos transistors on a common substrate
US4458158A (en) IC Including small signal and power devices
JP3205361B2 (en) Method for manufacturing power MOS transistor with longitudinal current
US4283236A (en) Method of fabricating lateral PNP transistors utilizing selective diffusion and counter doping
US5679587A (en) Method of fabricating an integrated circuit with vertical bipolar power transistors and isolated lateral bipolar control transistors
US6249031B1 (en) High gain lateral PNP and NPN bipolar transistor and process compatible with CMOS for making BiCMOS circuits
US4780425A (en) Method of making a bipolar transistor with double diffused isolation regions
EP0051534B1 (en) A method of fabricating a self-aligned integrated circuit structure using differential oxide growth
US5110749A (en) Method for manufacturing semiconductor device
EP0168325A2 (en) Ion implantation to increase emitter energy gap in bipolar transistors
EP0043007A2 (en) Saturation-limited bipolar transistor circuit structure and method of making
US5837590A (en) Isolated vertical PNP transistor without required buried layer
US4101349A (en) Integrated injection logic structure fabricated by outdiffusion and epitaxial deposition
US4106049A (en) Semiconductor device
US5633180A (en) Method of forming P-type islands over P-type buried layer
EP0045848A1 (en) Planar semiconductor integrated circuits including improved bipolar transistor structures and method of fabricating such circuits
US6624497B2 (en) Semiconductor device with a reduced mask count buried layer
US7271070B1 (en) Method for producing transistors
WO1989004555A1 (en) Bipolar transistor devices and methods of making the same
US5273913A (en) High performance lateral PNP transistor with buried base contact
US6979624B2 (en) Reduced mask count buried layer process
KR100358306B1 (en) method of fabricating vertical type bipolar transistor
KR100368612B1 (en) method of fabricating vertical type transistor

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE CH DE FR GB IT LI LU NL SE

17P Request for examination filed

Effective date: 19891109

17Q First examination report despatched

Effective date: 19910607

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 19940316