JPH0249464A - Bi-mos semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To make a Bi-MOS semiconductor high in density and performance by a method wherein a bipolar and a MOS transistor are formed on a silicon single crystal layer of an SOI (Silicon on Insulator) structure through a common process. CONSTITUTION:A SiO2 layer 2 and a p-type silicon single crystal layer 3 are formed on a silicon substrate 1, and a p-type diffusion region 50, an n-type well 70, an isolation insulating layer 4, a gate, and an insulating layer 8 are formed on a bipolar and a MOS transistor regions 5 and 7 respectively, and then polycrystalline silicon is deposited thereon and impurity is injected thereinto, and patterning is performed to provide a base lead-out electrode 72, and gates 6G and 7G to the region 5 and the MOS transistor regions 6 and 7 respectively. After an n-type impurity region 62 has been formed, a SiO2 layer is deposited, which is etched back to form a side wall 18 and a layer 17. A process follows, where a thermal oxidation is executed to make the impurity diffuse into the region 50 for the formation of a p<+> impurity region 52 and a through-oxide film 20. Next, impurity is injected into the layer 3 to form an n<+> impurity region 53, an n<+> impurity region 63, and a p<+> impurity region 73 on the regions 5, 6, and 7 respectively, and then a protective layer 22 and an electrode 24 are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a bi-MOS semiconductor device, and particularly to a bi-MOS semiconductor device consisting of a lateral bipolar transistor with a sor structure and a MOS transistor.

The purpose of this invention is to reduce the number of required masks and steps by making it possible to form bipolar transistors and MOS transistors in the same process as much as possible, thereby making it possible to reduce manufacturing costs.

forming means for electrically isolating from each other the bipolar transistor region and the MOS I-transistor region defined in the semiconductor single crystal layer formed on the insulating layer;
Implantation of base forming impurities into the bipolar transistor region? Implantation of well formation impurities or source/drain formation impurities into the IO5 transistor region or implantation of channel cut formation impurities into the isolation means formation region are simultaneously performed, or emitter and collector formation impurities are implanted into the bipolar transistor region. The method is configured to include at least a step of simultaneously implanting source/drain impurities into the MOS transistor region.

[Industrial application field]

The present invention relates to bi-MOS semiconductor devices, and particularly relates to bi-MOS semiconductor devices.

A bi-MOS in which a lateral bipolar transistor and a MOS transistor are formed in a semiconductor single crystal layer with an SOI structure, that is, a semiconductor single crystal layer formed on an insulating layer.
Related to semiconductor devices.

[Conventional technology]

By integrating bipolar transistors and MOS transistors on the same substrate, integrated circuits have been put into practical use that have the characteristics of high-speed operation of bipolar transistors and the high degree of integration and low power consumption of MOS transistors. For example, the access speed of an SRAM made of CMOS cells equipped with bipolar transistors as logic circuits is about 20 ns, and the maximum access time of an SRAM made only of CMOS is 35 ns, which is overall faster.

Meanwhile, elements such as transistors are manufactured in a semiconductor single crystal layer formed on an insulating layer. The so-called 5OI (Silic
The on-on in5ulator technology enables a structure in which each element is completely separated by an insulating layer, resulting in high-speed operation and low power consumption due to the reduction of parasitic capacitance between the substrate and the element. , it has advantages such as the withstand voltage between elements can be easily improved.

[Problem to be solved by the invention]

However, in conventional bi-MOS semiconductor devices, it has been difficult to take advantage of the advantages of the 501 structure due to the following secondary reasons.

(2) Like a normal bipolar transistor, a bipolar transistor in a conventional bi-MOS structure requires a buried layer to serve as a collector electrode.

Then, an epitaxial growth layer for forming an element is formed on this buried layer. the result.

As the thickness of the semiconductor layer increases, the effect of reducing the source/drain junction capacitance of a MOS transistor by using a semiconductor single crystal layer with a sor structure, which usually has a thickness of 1 μm or less, cannot be obtained. A bipolar transistor in a bi-MOS semiconductor device is formed according to the process of a normal bipolar transistor. Therefore, if high-temperature heat treatment such as melting of a PSG (borosilicate glass) film is performed to flatten the treated surface.

Emitter impurities tend to diffuse excessively, and in an SOI structure using a thin semiconductor crystal layer, breakdown voltage defects in the base layer tend to occur.

In order to solve the problems caused by bipolar transistors as described above, it is possible to use lateral bipolar transistors. It has been reported that a lateral bipolar transistor that can also operate as an NO3 transistor is formed in a silicon layer with an S01 structure (B, Y,
Tsaur et al., It! II! E ELECTROND
EVICE Ll! TTERS, VOL, EDL-4,
No. 8, 1983, PP, 269-271). The structure of this element is as shown in FIG.

It is said that it is formed as a four-terminal element and can be used as an NPN type bipolar transistor or an n-channel type MOS transistor.

However, the above report does not disclose that a bipolar transistor and a NO3 transistor having different carrier conductivity types are formed separately, and therefore, a lateral bipolar transistor and a CMOS
There is also no disclosure of a bi-MOS semiconductor device composed of transistors.

In addition, in the above report, since the base extraction electrode is provided at the end of the base part, the base resistance is large, or the impurity concentration in the base region of the bipolar transistor and that in the channel region of the MOS transistor are simultaneously minimized. It is difficult to convert into

The present invention provides bipolar transistors with SOI structure and MO
By making it possible to form the S transistor in the same process as much as possible, the number of required masks and processes can be reduced, thereby reducing manufacturing costs.

A bipolar transistor with any carrier conductivity type and M
It is an object of the present invention to provide a bi-MOS semiconductor device formed by combining OS transistors, and furthermore, a bi-MOS semiconductor device having a CMOS structure.

[Means to solve the problem]

The above purpose is to provide a semiconductor device crystal layer formed on an insulating layer;
A bipolar transistor region and a MOS transistor region defined in the semiconductor single crystal layer, means for electrically isolating each of the transistor regions from each other, and a lateral bipolar transistor formed in the bipolar transistor region.

A CMOS transistor consisting of MOS transistors with channels of different conductivity types formed in a plurality of MO5 transistor regions, respectively, or a MOS transistor having a channel of a conductivity type different from the carrier conductivity type in the lateral bipolar transistor. a bi-MOS semiconductor device according to the present invention, and a step of forming means for electrically isolating a bipolar transistor region and a MOS transistor region defined in a semiconductor single crystal layer formed on one insulating layer; Implantation of base forming impurities into the bipolar transistor region and implantation of well forming impurities, source/drain forming impurities, or channel cant forming impurities into the Mos transistor region are performed simultaneously, or emitter and collector forming impurities are implanted into the bipolar transistor region. Injection and the MO
This is achieved by the method for manufacturing a bi-MOS semiconductor device according to the present invention, which includes the step of simultaneously implanting source/drain impurities into five transistor regions.

[For production]

While controlling the impurity concentration in the impurity diffusion region to an optimum value in a thin semiconductor single crystal layer with a saI structure.

A lateral bipolar transistor can be formed together with a MOS transistor. In particular, by providing spacers on the side surfaces of the gate electrode of the MOS transistor and the side surfaces of the base electrode of the lateral bipolar transistor, a high performance MOS transistor and a lateral bipolar transistor can be formed.

According to the invention, a lateral bipolar transistor and M
The OS transistors can be formed as desired, whether the conductivity types of the carriers are the same or different. Therefore, it is also possible to form a bi-CMOS structure consisting of a bipolar transistor and a CMOS transistor.

Further, by forming the base of the lateral bipolar transistor by lateral diffusion of base impurities, its thickness can be controlled with high accuracy to 1 μm or less.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a cross-sectional view of a main part showing the principle structure of a high-MOS semiconductor device according to the present invention, and is a 5iO1 layer 2 formed on a silicon substrate 1 with a thickness of about 1.0 μm. A 1 μm silicon single crystal layer 3 is separated into a bipolar transistor region 5 and MOS transistor regions 6 and 7 by a two-separation insulating layer 4, and is an NPN consisting of a lid PC.
A transistor is formed, and the MOS transistor regions 6 and 7 include an n-source/drain 6
n-channel consisting of S and 6D and gate 6G? lO5 transistor and p+-source/drain 7S and 7
P channel MOS transistors each consisting of a gate D and a gate 7G are formed. In addition, 51 is a base extraction electrode made of polycrystalline silicon, 53 is an n'''-collector contact layer, 54 is an emitter electrode and a collector electrode, 64 is a source/drain electrode of the n-channel MOS transistor, and 74 is the p-channel MOS transistor. M.O.S.
Source/drain electrodes of the transistor, 8 a gate insulating film, 9 a glabellar insulating layer made of, for example, PSG (borosilicate glass).

As shown in the figure, the bi-MOS semiconductor device of the present invention includes bipolar transistors with different carrier conductivity types, such as an NPN transistor formed in region 5 and a p-channel MO3I-transistor formed in region 7, and a MO3I-MOS semiconductor device of the present invention.
S has a transistor. Also, n-channel MOS
Both the transistor and the p-channel MO3 transistor are formed in MOS transistor regions 6 and 7, respectively, separated by a Sol structure, forming a bi-CMO transistor.
It is also possible to have an S structure.

FIG. 2 is a sectional view of a main part for explaining the steps of an embodiment of the method for manufacturing a bi-MOS semiconductor device of the present invention.

Figure 2 (see al) 1. For example, a Si02 layer 2 with a thickness of about 0.5μ is deposited on a silicon substrate l by a wet oxidation method.
After forming the SiO2 layer 2, a polycrystalline silicon layer having a thickness of about 1 μm is deposited on the SiO2 layer 2 using a well-known technique such as CVD (chemical vapor deposition). During the deposition of this polycrystalline silicon layer, 1.5xl of p-type impurity such as boron (B) is added.
The polycrystalline silicon layer is doped to an extent of O"/cm2. The polycrystalline silicon layer is recrystallized by a method such as laser annealing. In this way, a substrate with an SOI structure having a p-type silicon single crystal layer 3 with a specific resistance of approximately 10 Ωcm is prepared. Then, the surface of the silicon single crystal layer 3.

For example, it is thermally oxidized at 1000° C. in dry oxygen gas to form a through oxide film with a thickness of about 300 or less and 10 SiO□ layers.

On the surface of silicon single crystal layer 3, regions are defined such as bipolar transistor region 5 and MOS transistor regions 6 and 7. Then, for example, phosphorus ions (9) are applied to the silicon single crystal layer 3 in the MOS transistor region 7.
An n-type impurity such as P) is selectively implanted. The ion energy at this time is about 100 KeV, and the implantation amount is 1×lO''/-.

Next, the silicon single crystal layer 3 in the bipolar transistor region 5 is irradiated with 9 ions, such as boron ions (B).
Selectively implant type impurities. The ion energy at this time was about 100 KeV, and the implantation amount was 1xlO"/-
shall be. After that, the silicon substrate 1 is placed in nitrogen gas for 1
For example, annealing is performed at 1200° C. for 3 hours. As a result, the implanted impurities are diffused.

As shown in FIG. 2(b), a p-type diffusion region 50 and an n-type well 70 are formed in the bipolar transistor region 5 and the MOS transistor region 7, respectively.

After the above, the SiO2 layer 1O is removed and the SiO2 layer 1O is removed.
1, the bipolar transistor region 5 and the MO
A well-known LOGOS mask layer is formed to mask the S I-transistor regions 6 and 7. This mask layer consists of a Si02 layer 11 with a thickness of about 300 or less and a thickness of 100
It consists of about 0OiJn (silicon nitride) layer 12.

Next, the portions of the silicon single crystal layer 3 exposed from the mask layer are selectively etched by about 0.7 μm, and the silicon single crystal layer 3 remaining in the exposed portions is locally oxidized to form an isolated layer made of SiO□. An insulating layer 4 is generated.

After that, the Si3N4 layer 12 and the Si0g layer 11 were removed.

The surfaces of the silicon single crystal layer 3 in the bipolar transistor region 5 and the MOS transistor regions 6 and 7 are thermally oxidized to form a gate insulating layer 8 made of a 5iOz film with a thickness of 300 μm. Here, if necessary, for the MOS transistor regions 6 and 7, a p
Selective implantation of type impurities and n-type impurities is performed. Next, gate insulating layer 8 in bipolar transistor region 5 is selectively removed. FIG. 2(d) shows the state immediately after this removal.

Next, a polycrystalline silicon layer with a thickness of about 5,000 yen is deposited on the entire surface of the silicon substrate 1, and 9, for example, B'' ions are implanted into this polycrystalline silicon layer as an impurity to increase conductivity. The injection amount is
50KeV and 1xlO"/-, respectively. After that, a well-known CVD process was applied to the entire surface of the polycrystalline silicon layer.
A layer of approximately 3000 nm thick is deposited using the method.

Then, using the well-known dry etching method, the above S
patterning the in, layer and polycrystalline silicon layer;
As shown in FIG. 2(e), base lead electrodes 72. Gates 6G and 7G are formed. On top of these to form part of the side walls, which will be described later.

The SiO1 layer 17 deposited on the polycrystalline silicon layer remains.

- Next, using the gate 6G as a mask, 9, for example, phosphorus (P''') ions are implanted as an n-type impurity into the silicon single crystal layer 3 exposed in the MOS transistor region 6.The ion energy and implantation amount at this time are as follows. 50K
eV and 1xlO"/-. As a result, the n-type impurity region 62 constituting the low concentration drain (LDD)
is formed.

After the above, a SiO□ layer having a thickness of approximately 3000 layers is deposited on the entire surface of the silicon substrate 1, and this is etched by a well-known etch-back method. This sex back.

The end point is when the silicon single crystal layer 3 in the bipolar transistor region 5 and the MOS transistor regions 6 and 7 begins to be exposed. the result.

As shown in FIG. 2(f), a side wall 18 having a thickness of about 3000 mm is formed on each of the base extraction electrode 51 and the gates 6G and 7G. Further, the 5iCh layer 17 remains on each upper surface. Next, the exposed surface of the silicon single crystal layer 3 is thermally oxidized to form a through oxide film 20. Note that the impurity doped in the base extraction electrode 51 is diffused into the p-type diffusion region 50 during the heat treatment, and the p-type
``The impurity region 52 is formed.

Next, bipolar transistor region 5 and MOS
n in the silicon single crystal layer 3 in the transistor region 6
For example, arsenic (As) ions are selectively implanted as type impurities. The ion energy and implantation amount at this time are 100 KeV and 1xlO''/-, respectively.

As a result, the bipolar transistor region 5 has an n3 impurity region 53 constituting the emitter 5E and collector 5C.
However, in the MOS transistor region 6, an n impurity region 63 forming a source/drain is formed. Furthermore, 1, for example, B ions are selectively implanted as a p-type impurity into the silicon single crystal layer 3 in the MOS transistor region 7.

The ion energy and implantation amount at this time are 30 KeV and 1xlO''/-, respectively.As a result, p' impurity regions 73 forming the source/drain are formed.

After the above, the silicon substrate 1 is heat-treated at 1000° C. in dry oxygen. As a result, as shown in Figure 2 (g),
In each region, a block oxide film (not shown) is formed on the silicon single crystal layer 3 covered with the thin Si02 layer 20, and the bipolar transistor region 5 and MOS
n゛ impurity region 53 and MO in transistor region 6
S P impurity region 73 in transistor region 7
diffuses until reaching the 5iOz layer 2 in each region.

Next, the entire surface of the silicon substrate 1 is coated as a protective layer.

For example, after depositing a PSG (borosilicate glass) layer 22.

A contact hole is formed in the predetermined position, and as shown in Figure 1,
Electrodes 24 made of aluminum, for example, are formed to be connected to n'' impurity regions 53 and 63 and p'' impurity region 73 through these contact holes, respectively. In this way, a lateral bipolar transistor having the n° impurity region 53 as the emitter and collector and the p-type impurity region 50 as the collector is formed using the bipolar transistor region 5.
In addition, an n-channel MOS transistor having an LDD structure with the n impurity region 63 as the source/drain is M
In the OS transistor region 6, p-channel MOS transistors having the p impurity region 73 as the source/drain are formed in the MOS transistor region 7, respectively.
The bi-MOS semiconductor device of the present invention is completed.

FIG. 3 is a sectional view of a main part for explaining the steps of another embodiment of the method for manufacturing a bi-MOS semiconductor device according to the present invention.

A silicon substrate having a silicon single crystal layer formed on a SiO2 layer is prepared in the same manner as in the previous embodiment.

In this example, the silicon single crystal layer is doped with n-type impurities and has a resistivity of 5 Ωcffl. Figure 3 (
8), the silicon single crystal layer 3 is selectively etched away to form a groove 25 reaching the 5iOz layer 2. In this way, silicon single crystal layer 3 is separated into bipolar transistor region 5 and MOS transistor regions 6 and 7.

The surface of the silicon single crystal layer 3 in each region is thermally oxidized to form a 26-layer SiO□ layer 6 with a thickness of about 300 layers.

The 5iOz layer 26 is provided for the purpose of oxidizing the inside of the trench 25.

1. After depositing a SiO2 layer with a thickness of about 1 μm on the entire surface of the silicon substrate 1 using, for example, the well-known CVD method,
This is removed using a well-known etch bank method. As a result, as shown in FIG. 3(b), the SiO2 layer remains in the groove 25, forming an isolation insulating layer 4. During the etch bank described above, a part of the two bipolar transistor regions 5 is masked with a resist layer (not shown). As a result, the SiO layer 41 covering a portion of the silicon single crystal layer 3 in the bipolar transistor region 5 remains.

In areas not masked by the resist layer, the Si01 layer 26 is removed and the silicon single crystal layer 3 is removed.
may be exposed. For this reason, after the etch bank step, thermal oxidation is performed to form a SiO□ layer with a thickness of approximately 200 nm, which becomes a through oxide film in the first step. The reference numeral 26 is attached to this Si01 layer.

Next, as shown in FIG. 3(C), the MOS transistor region 6 is selectively masked with a resist layer 27.

Phosphorous ions (P), for example, are implanted as an n-type impurity into the silicon single crystal layer 3 exposed in the bipolar transistor region 5 and the MOS transistor region 7. The ion energy and implantation dose in this implantation are 100 KeV and 4xlO''/cj, respectively. In the above implantation, the 5iCh layer 41 remaining in the bipolar transistor region 5 acts as a mask.

Next, as shown in FIG. 3(dl), the MOS transistor region 7 is selectively masked with a resist layer 28, and p-type impurities such as boron ions (B+) are implanted into the exposed silicon single crystal layer 3. What is the ion energy and implantation dose for this implantation?

100 KeV and 2xlO"/-, respectively. In the above B9 ion implantation, the 5i02 layer 41 remaining in the bipolar transistor region 5 functions as a mask. In the above process, the silicon single crystal layer 3 in the bipolar transistor region 5 is Be on the exposed part
Both ions and P+ ions are implanted, but since the range of B° ions is greater than that of P′ ions, an Ip essential region 55 is formed.

After the above, the resist layer 28 is removed.

The Si02 layer 41 is selectively removed. Selective removal of the Si02 layer 4I can be achieved by removing the resist layer 28, applying a resist layer to the entire surface of the silicon substrate 1, and etching back until the silicon single crystal layer 3 is exposed. Next, the silicon substrate l is placed in dry oxygen gas.
Heat treatment is performed at 900°C, and further heat treatment is performed at 1200°C in nitrogen gas. As a result, as shown in FIG. 3 (81), 316 layers 29 with a thickness of about 200 layers are generated on the surface of the silicon single crystal layer 3 exposed in each transistor region 5, 6.7, and each of the transistors The impurity implanted in the region is diffused. Due to this diffusion, the thin p-type region 55 in the bipolar transistor region 5 moves across the silicon single crystal layer 3 in the layer thickness direction. The silicon single crystal layer 3 in each becomes a p-type well and an n-type well as a whole.The present inventor has disclosed a method for manufacturing a bipolar transistor having a base composed of a thin p-type region 55 as described above. has been done.

(Patent application No. 63-073125, dated March 29, 1988) After the above, if necessary, for adjusting the threshold voltage (V) of the MOS transistors formed in the p-type well and n-type well. First, impurity ions of a predetermined conductivity type and concentration are selectively implanted into each region. The Sin layer 29 functions as a through oxide film in this ion implantation, and if ion implantation for V adjustment is not performed, the heat treatment in oxygen gas may be omitted. If a Sin layer 29 is formed, it is removed after the ion implantation for V adjustment.

After the above, the silicon substrate l was placed in dry oxygen gas for 1000 ms.
As shown in FIG. 3(f), a Si01 layer 8 with a thickness of about 300 nm is formed to serve as a gate oxide film on the surface of the silicon single crystal layer 3 in each transistor region 5.6 and 7.
is formed, and this Si01 layer 8 in the bipolar transistor region 5 is selectively removed.

In this case, in the bipolar transistor region 5, the 5iOz layer 8 is left so that the portion of the silicon single crystal layer 3 constituting the collector is masked.

Next, a polycrystalline silicon layer with a thickness of about 5,000 SiO is deposited on the entire surface of the silicon substrate 1, and after implanting B+ ions, for example, into this layer, a SiO layer with a thickness of about 3,000 SiO is deposited.
Stack one layer. The above implantation was carried out using an ion energy of 50K.
eV and an injection volume of 5×lO”/aa. And.

The Si01 layer and the polycrystalline silicon layer are patterned using the well-known glue sogelaf technique, and as shown in FIG.
form 6G and 7G, respectively. code 30
is a Sin layer patterned together with the polycrystalline silicon layer.

If necessary, impurity ions for forming an LDD are selectively ion-implanted into each of the MOS I-transistor regions 6 and 7 using Ga) 6G and 7G and a resist layer (not shown) as masks. This ion implantation is 5
For example, for the MQS transistor region 6, P4 ions are implanted at an ion energy of 50 KeV and an implantation amount of 1χ10.
At Iff/-, BP is applied to the MOS transistor region 7 with an ion energy of 10 KeV and an implantation amount of 1x10/ell. In FIG. 3, numerals 62 and 72 respectively indicate an n-type impurity region and an n-type impurity region constituting the LDD.

Next, 1, for example, BP, ions are implanted into the entire surface of the silicon substrate 1 to a thickness of about 3000 p-type impurities.

In the bipolar transistor region 5, an n3- impurity region 53 which becomes an emitter and collector contact layer is formed into a MOS
An n-impurity region 63 serving as a source/drain is formed in the transistor region 6, and a p-impurity region 73 serving as a source/drain in the MOS transistor region 7. The above As'' ions and BF,° ions were implanted at an ion energy of 100 eV and 30 KeV, respectively, and the implantation dose was 1xlO''/a.
Let it be J. Note that the side wall 32 in the above is made of, for example, a polycrystalline silicon layer, and its surface is coated with SiOg by oxidation.
A structure in which layers are formed may also be used.

Side walls 32 made of SiO2 are formed on each of gates 6G and 7G. Then, selectively to the bipolar transistor region 5 and the MOS transistor region 6.

Simultaneously implant 5, for example As'' ions as n-type impurities, while selectively into the MOS transistor region 7.

A 5 iOz layer (not shown) of 5 iOz (not shown) and a PSG (borosilicate glass) layer 33 having a thickness of about 1 μm are sequentially deposited, and contact holes are formed at predetermined positions in each layer using a well-known lithography technique. Then, through these contact holes, the n-emitter 7E, the B+-collector contact layer 53. n”-source/drain 6S and 6D
, the emitter and collector electrodes 54 and the source and drain electrodes 64 and 74 connected to the p''-source/drains 7S and 7D, respectively, are formed to complete the bi-MOS semiconductor device according to the present invention.

FIG. 4 is a sectional view of a main part for explaining the steps of still another embodiment of the method for manufacturing a bi-MOS semiconductor device of the present invention, in which impurity implantation into the base region of a lateral bipolar transistor and sauce/
A case is shown in which impurity implantation into the drain region is performed simultaneously.

As shown in FIG. 4(a), in the same manner as in FIG.

A SiO□ layer 2 with a thickness of about 0.5 μm is formed on a silicon substrate 1.
is formed, and on this Si01 layer 2, an n-type silicon single crystal layer 3, for example, is formed. The silicon single crystal layer 3 is separated into a bipolar transistor region 5 and a MOS transistor region 7 by an isolation insulating layer 4 . On the surface of the silicon single crystal layer 30, a SiO2 layer 10 with a thickness of approximately 300 layers is formed by thermal oxidation.

The base region and M in the bipolar transistor region 5
After forming a resist layer 27 for masking the entire OS transistor region 7, an n-type impurity such as arsenic ion (As") is ion-implanted to form the n"-jff region, which will become the emitter and collector of the lateral npn transistor. Form 53.

Then 2. After removing the resist layer 27 and the Si02 layer 10, the surface of the silicon single crystal layer 30 is thermally oxidized to form the gate insulating layer 8, as shown in FIG.

A gate 7G made of a polycrystalline silicon layer is formed in a predetermined region of the MOS transistor region 7, and then
A resist layer 28 having an opening corresponding to the base region of the transistor region 5 is formed. and.

Using the gate 7G and the resist layer 28 as a mask, an n-type impurity such as boron ions (B+) is implanted into the single crystal silicon layer 3. In this way, the bipolar transistor region 5 has a p"4rM region that becomes the base of the npn transistor, and the MOS transistor region 7 has a p"-eI region 73 that forms the source/drain of the p-channel MOS I-transistor. are formed respectively.

FIG. 5 is a cross-sectional view of a main part for explaining the steps of still another embodiment of the method for manufacturing a bi-MOS semiconductor device of the present invention, including the implantation of impurities into the base region of a lateral bipolar transistor and the channel of the MOS transistor. A case is shown in which impurity implantation for forming cuts is performed at the same time.

As shown in FIG. 5(a), in the same manner as in FIG.

A Si01 layer 2 with a thickness of about 0.5 μm is formed on a silicon substrate 1.
A p-type silicon single crystal layer 3, for example, is formed on the 5iOz layer 2. The silicon single crystal layer 3 is separated into a bipolar transistor region 5 and a MOS transistor region 6 by an isolation insulating layer 4. on the surface of silicon single crystal layer 3.

Si02 layer 10 with a thickness of about 300 by thermal oxidation and CVD
After forming a 5izNa layer 12 with a thickness of approximately 1000 nm by a method.

A resist layer 27 is formed to cover a predetermined region within the MOS transistor region. Using the resist layer 27 as a mask.

After selectively etching the Si, N, and layers 12, ions of, for example, boron ions (B') are implanted as a p impurity into the exposed silicon single crystal layer 3. An example of this implantation condition is that the ion energy is 100 KeV and the dose is 1.
xlO''/cIat'.

After removing the resist layer 27, the silicon single crystal layer 3 is thermally oxidized using the 5iJ4 layer 12 as a mask, as in the normal LOCOS method. As a result, as shown in FIG. 5), an isolation insulating layer 41 made of SiO
A region 31 is formed. Also in the bipolar transistor region 5, a SiO□ layer 42 is formed. after that.

The 5i3Na layer 12 is removed, and the Sin layer 42 in the bipolar transistor region 5 is also selectively removed.

Next, the Si remaining in the MOS transistor region 6 is removed.
After removing the 0g layer 10, the surface of the silicon single crystal layer 3 is thermally oxidized to form a 5iOz gate insulating layer 8 as shown in FIG. 5(C). After this, a base electrode 51 made of, for example, polycrystalline silicon is formed in the bipolar transistor region 5, and a gate electrode 51 is formed in the MOS transistor region 6.
6G respectively. Incidentally, the Sin layer formed on the surface of the silicon single crystal 3 in the bipolar transistor region 5 at the same time as the gate insulating layer 8 described above is selectively removed in advance before forming the base electrode 51 and the like.

After the above, the base electrode 51 and the gate 6G.

Using the isolation insulating layers 41 and 42 as masks, arsenic ions (A
s") to form the n-region 5, which constitutes the emitter and collector of the npn bipolar transistor.
3 and n-channel MOS transistor source/
A no- region 63 constituting a drain is formed.

As described above, in this embodiment, the p-type impurity forming the base of the npn bipolar transistor and the p-type impurity forming the channel cut around the n-channel MOS transistor are simultaneously implanted.

In each of the above embodiments, a case is shown in which an npn type bipolar transistor is formed in the bipolar transistor region 5, but it can be easily understood that a pnp type bipolar transistor is formed in the region 5.

〔Effect of the invention〕

According to the present invention, it is possible to form bipolar transistors and MOS transistors in a silicon single crystal layer having an SOI structure in a common process, and to achieve high density and high performance bi/M
OS semiconductor device or bi-CMOS semiconductor device
This has the effect of promoting the practical use of OS transistors.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of essential parts showing the basic structure of a bi-MOS semiconductor device according to the present invention. FIG. 2 is a sectional view of a main part for explaining the steps of an embodiment of the method for manufacturing a bi-MOS semiconductor device of the present invention. 3 to 5 are sectional views of main parts for explaining the steps of another embodiment of the method for manufacturing a bi-MOS semiconductor device of the present invention. FIG. 6 is a sectional view showing the structure of a conventional semiconductor device in which a lateral bipolar transistor, which also operates as a MOS I-transistor, is formed in an SOI silicon recrystallized layer. In fig. 1 is a silicon substrate. 2 and 10 and 11 and 17 and 20 and 26 and 29 and 30 and 4
2 is a 5i (h layer. 3 is a silicon single crystal layer. 4 and 41 are isolation insulating layers. 5 is a bipolar transistor region. 6 and 7 are MOS transistor regions. 4B is a base. 4C is a collector. 7E is an emitter. 6G and 7G are Gates 6S and 78 are sources. 6D and 7D are drains. 9, 22 and 33 are PSG layers. 8 is a gate insulating layer. 12 is Si, N, layer 1. 18 and 32 are side walls. 24, 54, 64 and 74 are Electrode. 25 is a groove. 27 and 28 are resist layers. 31, 52 and 73 are p+- regions. 50, 55 and 72 are p-type head regions. 51 is a base extraction electrode. 53 and 63 are n- regions. 60 and 70 are wells. 62 is an n-type region. -f'>θ, jJL
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Claims (8)

[Claims] (1) A semiconductor single crystal layer formed on an insulating layer, at least one bipolar transistor region and a plurality of MOS transistor regions defined in the semiconductor single crystal layer, and electrically separating each of the transistor regions from each other. a lateral bipolar transistor having an emitter and a collector of one conductivity type formed in the bipolar transistor region; a MOS transistor having a source/drain of one conductivity type formed in one of the MOS transistor regions; and a MOS transistor having a source/drain of an opposite conductivity type formed in another one of the MOS transistor regions. (2) a semiconductor single crystal layer formed on an insulating layer, a bipolar transistor region and a MOS transistor region defined in the semiconductor single crystal layer, and means for electrically isolating each of the transistor regions from each other; A lateral bipolar transistor having an emitter and a collector formed by selectively implanting impurities of one conductivity type into a predetermined region within a bipolar transistor region; and a lateral bipolar transistor having an emitter and a collector formed by selectively implanting impurities of an opposite conductivity type into a predetermined region within the MOS transistor region. 1. A bi-MOS semiconductor device comprising: a MOS transistor having a source/drain formed as a MOS transistor. (3) a semiconductor single crystal layer formed on an insulating layer, a bipolar transistor region and a MOS transistor region defined in the semiconductor single crystal layer, and means for electrically isolating each of the transistor regions from each other; A lateral bipolar transistor having as a base a diffusion layer formed by lateral diffusion of an impurity selectively implanted into a predetermined region in a bipolar transistor region outside the predetermined region; and a MOS transistor formed in the MOS transistor region. A bi-MOS semiconductor device characterized by comprising: (4) A side wall having at least a surface covered with an insulating material is provided on each of the side surface of the gate of the MOS transistor and the side surface of the base electrode of the lateral bipolar transistor. or 3 bi-MOS semiconductor devices. (5) forming means for electrically isolating the bipolar transistor region and the MOS transistor region defined in the semiconductor single crystal layer formed on the insulating layer; and implanting base forming impurities into the bipolar transistor region. A method for manufacturing a bi-MOS semiconductor device, comprising the step of simultaneously implanting well-forming impurities or source/drain-forming impurities into the MOS transistor region. (6) a step of forming a mask covering a predetermined region within the bipolar transistor region; a step of implanting the base forming impurity into the region exposed from the mask; and a step of performing heat treatment after implanting the impurity. 6. The method of manufacturing a bi-MOS semiconductor device according to claim 5, wherein the impurity diffusion layer laterally diffused into the bipolar transistor region under the mask is used as a base. (7) forming a means for electrically isolating the bipolar transistor region and the MOS transistor region defined in the semiconductor single crystal layer formed on the insulating layer; A method for manufacturing a bi-MOS semiconductor device, comprising the steps of simultaneously performing implantation and implanting source/drain impurities into the MOS transistor region. (8) Forming a means for electrically isolating the bipolar transistor region and the MOS transistor region defined in the semiconductor single crystal layer formed on the insulating layer from each other; implanting base forming impurities into the bipolar transistor region and separating the bipolar transistor region; A method for manufacturing a bi-MOS semiconductor device, comprising the step of simultaneously implanting channel cut forming impurities into a region where a means is to be formed.