JPS61230354A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain a Bi-CMOS IC having characteristics as a bipolar-transistor having extremely high performance by forming base-emitter regions in a controllable manner in fine size. CONSTITUTION:Drain-source regions and a gate electrode in a CMOS section are shaped, an inter-layer insulating layer 14 is laminated on the whole surface, the PSG film in the region of a bipolar-transistor is removed selectively through etching, and the PSG film is melted through heating. B ions are implanted while using a resist, to which only a base region is bored, as a mask, and electrode windows 17 are bored to the bipolar-transistor section. Polycrystalline silicon 15 is laminated on the whole surface, and As ions are implanted while employing a resist, to which only collector-emitter regions are bored, as a mask. Polycrystalline silicon on the MOS side is removed through etching, and source- drain electrode windows 16 are bored through a tapered etching method to the PSG film.

Description

[Detailed Description of the Invention] [Summary] When manufacturing an integrated circuit device in which bipolar and Mis) transistors are formed on the same chip, it is possible to form shallow base and emitter regions in the bipolar part by improving the process. As a result, we reduced the power consumption and increased the speed of the device.

[Industrial application field]

The present invention is an integrated circuit that requires the coexistence of a logic circuit and a linear circuit, and is a so-called Bi-MISIC in which bipolar and MIS transistors can be formed on the same chip.
Relating to a manufacturing method.

As the manufacturing technology of semiconductor integrated circuits advances, there is an increasing demand for forming a logic circuit section and a linear amplifier circuit on the same chip.

In the manufacturing process of such integrated circuits, MISF
The difference in structure between the ET section and the bipolar transistor section complicates the process, and the problem often arises that bipolar characteristics cannot be achieved as desired due to process constraints.

In particular, in order to reduce the power consumption and increase the speed of Bi-MISIG, it is necessary to form the base region of the HAI boular transistor as shallow as possible, and improvements are desired.

[Conventional technology]

As a conventional MIS) transistor, CMO3
A method for manufacturing a Bi-CMO3 IC composed of the following will be explained with reference to step-by-step cross-sectional views of FIGS.

FIG. 2 (al) shows a state in which an n-type buried layer 2 is selectively formed in the p-MOS and bipolar transistor portions using a mask on the p'' type silicon substrate 1.

An n-type epitaxial layer 3 is grown in vapor phase on the silicon substrate. This is shown in FIG. 2(b). In this growth, the substrate temperature is heated to 1000° C. or more, so the impurity layer spreads to the epitaxial layer.

Next, a Sing film 4 is formed on the entire surface of the substrate by thermal oxidation, and further,
A 5izN4 film 5 is laminated by CVD. Then M.O.3
The S i 3 N 4 film other than the element forming region and the bipolar base and collector regions is removed by selective etching.

Next, the formation region of the p-well 6 and the isolation region 7 are masked with a resist, boron (B) ions are implanted, and annealing is performed to form the p-well and p-type isolation region shown in FIG. 2 (C1). area is obtained.

Next, B and arsenic (As) ions are implanted under the oxide film between adjacent transistors using a resist as a mask to form p-type and n-type channel cuts 8.9. By thermally oxidizing this substrate, S i 3
A thick field oxide film 10 is formed in areas other than those covered with the Na film. This state is shown in FIG. 2(d).

This completes the pre-process before forming the transistor element.

After chemically cleaning and removing the thin 5ilN film and SiO□ film on the substrate to expose the silicon substrate in the MOS and bipolar transistor forming regions, a gate oxide film 11 is grown in this region.

Next, B ions are implanted using a resist that opens only the base region of the bipolar transistor.

Next, n-type polycrystalline silicon is grown over the entire surface, and the base ion implanted region is annealed.

Next, the polycrystalline silicon is etched away except for the gate electrode portion to form the gate electrode 12.

Next, ions of AS% and B are implanted into the source and drain regions of the n-MOS and p-MOS while masking the gate electrode and other regions with resist.

At this time, when implanting As, ions are also implanted into the emitter region 17 and collector region 18 of the bipolar transistor. Further, when implanting B, B is also implanted into the base contact region. Through the above steps, the image shown in FIG. 2 (el) is obtained.

Next, the surface of the gate electrode is coated with Si as a block oxide film.
After growing the film 13 and growing the PSG film 14 on the entire surface, a contact hole 16 for an electrode window is opened.

In this state, high-temperature heat treatment at about 1050° C. is performed to melt the PSG film, thereby completing the structure shown in FIG. 2(f).

Description of the steps after the wiring step will be omitted.

[Problem that the invention seeks to solve]

In the conventional method described above, the formation of the PSG film is performed after the formation of the transistor element region.

Furthermore, since the electrode windows are opened after the PSG film is formed for both CMO5 and bipolar, the windows in the emitter and base regions, which require fine dimensions, are also exposed to the high-temperature dry melting process of the PSG film. For this reason, the base diffusion region cannot be made shallow.

Further, the emitter electrode window cannot be formed by the emitter diffusion region and the self-line.

As described above, there are major problems in improving the performance of bipolar transistors, and improvements are therefore desired.

[Means for solving problems]

The problem mentioned above is that after forming the drain, source region, and gate electrode of the CMOS section, an interlayer insulating layer (P
SG film) is stacked, and the interlayer insulating layer in the bipolar part is removed.

Next, after forming the base and collector regions in the bipolar part, electrode windows are opened in the surface insulating film, and a polycrystalline silicon layer is laminated on the entire surface. Form an emitter region.

Next, the polycrystalline silicon layer in the CMOS SJI area is removed, and a CMO layer is formed on the interlayer insulating film by tipper etching.
This problem is solved by the manufacturing method of the present invention, which includes a step of forming an electrode window in the S section.

[Effect]

The electrode window in the bipolar part is formed not through the PSG film, but through the surface oxide film, and after laminating a polycrystalline silicon layer, an emitter diffusion layer is formed by ion implantation, etc. Therefore, the emitter region is not an electrode window. It can be formed in a self-aligned manner against the window.

In addition, since the highly accurate formation of the bipolar base and emitter regions can be performed after the element formation of the CMOS section and the growth of the PSG film, the base region can be formed shallowly, and the diffusion region can be expanded in later steps. do not have.

〔Example〕

An embodiment according to the present invention will be explained in detail with reference to process cross-sectional views shown in FIGS. 1(a) to (dl). Since the steps up to the step of forming a transistor element remain the same, subsequent steps will be explained from FIG. 2(d). The same reference numerals in the drawings will be omitted.

Using the substrate formed as shown in Fig. 2(d),
After cleaning and removing the i 2 Na film and the Si0g film, a new gate oxide film 11 is formed over the entire surface. N-type polycrystalline silicon is grown over the entire surface, and the polycrystalline silicon is etched away except for the gate electrode 12.

Next, B ions are implanted using a resist mask that opens only the drain and source regions of the p-MOS and the external base region of the bipolar transistor.

Further, using the resist as a mask to open the drain and source regions of the n-MOS and the collector region of the bipolar transistor, ions of A3 are implanted to obtain the structure shown in FIG. 1(a).

Next, an oxide film 13 is grown on the gate electrode, source, drain, and bipolar transistor, and P is deposited on it.
The SG film 14 is laminated. The PSG film in the bipolar transistor region is selectively etched away. then 9
The PSG film is melted by heating in oxygen gas at 50° C. or lower.

Next, B ions are implanted using a resist mask that opens only the base region, and an electrode window 17 is opened in the bipolar transistor portion.

Next, approximately 500 layers of polycrystalline silicon 15 are deposited on the entire surface, and As ions are implanted using a resist mask that opens only the collector and emitter regions.

At this time, As is introduced while accurately controlling the amount of diffusion in the emitter region. This state is shown in FIG. 1(C).

Next, the polycrystalline silicon of the MOS (12) is removed by etching, and source and drain electrode windows 16 are opened by taper etching the PSG film.

This is shown in FIG. 1(d).

A description of the wiring patterning of the polycrystalline silicon layer of the bipolar portion, the subsequent A1 wiring process, etc. will be omitted.

〔Effect of the invention〕

As explained above, by applying the manufacturing method of the present invention, it is possible to control the formation of the base and emitter regions with fine dimensions, and it is possible to obtain a Bi-0MO3 IC with the characteristics of an extremely high-performance bipolar transistor. I can do it.

[Brief explanation of drawings]

Figures 1(a) to (d) show Bi-MI related to the present invention.
2(a) to (f) are cross-sectional views of the manufacturing process of Bi-Mi by the conventional method.
s is shown in cross-sectional view in the order of manufacturing steps. In the drawings, 1 is a p9 type silicon substrate, 2 is an n° type buried layer, 3 is an n type epitaxial layer, 4 is a Stow film, 5 is a Si 3 Na film, 6 is a p well, 7 is an isolating region, 8 is a p-type channel cut, 9 is an n-type channel cut, 10 is a field oxide film, 11 is a gate oxide film, 12 is a gate electrode, 13 is an oxide film, 14 is a PSG film, 15 is a polycrystalline silicon, 16, 17 denotes the electrode window and , respectively. 1m81 Figure 1 n-Mo5 ρ-Mos Ha1p-
tshi & number

Claims (1)

[Claims] In an integrated circuit consisting of a bipolar and MIS section, the drain, source region, and gate electrode (1
After forming 2), stacking an interlayer insulating film (14) on the entire surface, removing the interlayer insulating layer in the bipolar part, and then introducing an impurity into the base region of the bipolar part; After opening an electrode window (17) in the surface insulating film, a polycrystalline silicon layer (15) is laminated on the entire surface to form an emitter region, and the polycrystalline silicon layer (15) in the MIS region is removed. ,
A method for manufacturing a semiconductor integrated circuit device, comprising the step of forming an electrode window (16) in an MIS section by etching an interlayer insulating film (14).