JPH0249248A - Reference signal forming circuit - Google Patents

Abstract

PURPOSE:To simplify a circuit by providing a buffering period for the selection of the frequency of a reference signal so that the polarity of an error signal can be set at the one opposite to that of the signal in a recording speed detecting period. CONSTITUTION:A first sample and hold circuit is omitted, and the arrangement of the reference signal of a reference generation circuit 2 is changed. When the reference signal is inputted to a mixer 1, the polarity of the error signal (e) in the speed detecting period is set at the one opposite to that of the signal in the buffering period, and the periods are equal to each other, therefore, a noise can be canceled without fluctuating a DC level by inputting it to a low-pass filter LPF 10 for noise elimination with a time constant 48sec. In other words, the output of the LPF 10 cancels the fluctuation of the DC level generated by the error signal in the speed detecting period by the error signal in the buffering period. Therefore, an A/D conversion circuit 11 which inputs the output of the LPF can perform A/D conversion in full periods without stopping. Thus, the circuit can be simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a reference signal forming circuit that is effective when employed in 8 mm video.

C) Conventional Technology A video tape recorder called 8 mm video switches four types of pilot signals for each recording track and multiplexes them onto an FM video signal during recording. During playback of this 8mm video, a reference signal is formed, a beat component is formed with the playback pilot signal, two types of beat frequency components are separated individually, and their levels are compared to form an error signal. Based on the signals, tape running is controlled to eliminate tracking errors. Furthermore, 8 mm video allows the tape speed to be switched between two speeds, the standard speed and the second speed, during recording, and it is necessary to determine the recording speed of the tape during playback. Therefore, for example, Japanese Patent Application Laid-Open No. 60-136932 (G11B 151
087), the reference signal frequency is switched during a part of the period when one track is reproduced and scanned, and a reference signal frequency that generates one of the beat signal frequencies that forms the error signal is temporarily generated, and during that period, The recording tape speed is constantly detected based on the error signal.

FIG. 4 shows an 8 mm video tracking servo circuit according to the prior art described above. First, the reproduced pilot signal and the reference signal from the reference generation circuit (2) are input to the mixer (1). During normal reproduction, the reproduced pilot signal frequencies are h, fz, E5. It is switched in the order of Es... In addition, the reference signal frequency is set to f+ in synchronization with the switching of the reproduction peak signal.

It is switched in the order of fa, fg, fz, . . . Furthermore,
The reference signal frequency is f! at the center of each scan. , ft, f4. It is switched in the order of is... In Figure 5, (5) is the head output switching pulse, 忤) is the switching order of the reproduced pilot signal, (q is the basic switching order of the reference signal, and ([)) is the reference actually input to mixer (1). This shows the signal switching order.

Figure 5) shows that the reference signal temporarily forms a tape recording speed detection period at approximately the center of the playback scan, and other periods form a tracking error detection period. ing.

Therefore, the tracking servo circuit detects the tracking error during the tracking error detection period l, and detects the recording tape speed during the recording tape speed detection period.

The aforementioned reference signal and reproduced pilot signal are input to the mixer (1) to form a beat component. The beat component derived from the mixer (1) is input to a first band pass filter (3) that separates 46 KHz and a JG2 band pass filter (4) that separates 16 KHz. Each bandpass output is provided by the first and second detection circuits t5, respectively.
After being input to +61, it is input to a comparison circuit (7). An error signal corresponding to the level difference between the two transverse wave outputs is formed and derived from this comparison circuit (7).

FIG. 5(E) shows an error signal waveform when the recording tape speed and the reproduction tape speed match. This error signal waveform becomes a negative bell because many beat components of 16U (Z) occur during the recording speed detection period, indicating that a tracking error close to 0 level is formed during the tracking error detection period. Therefore, conventionally, a first sample and hold circuit (8) is installed after the comparison circuit (7) to perform sample and hold during the recording speed detection period, and a second sample and hold circuit to perform sample and hold during the tracking error signal detection period. A hold circuit (9) is arranged. Figs. 5(F) and q show the 1st and 9J2 control pulse waveforms input to the 1st and 2nd sample and hold circuits +81 and +91, respectively, and both sample and hold circuits +81 (
91 passes the input signal during the high level period and holds the input signal during the low level period (functions. As a result, the first sample and hold circuit (p) in FIG.
From 8), the signal related to the tracking error is
Further, an error signal related to speed switching is derived from the second sample and hold circuit (9). The first sample-and-hold output is input to a low-pass filter C11m for noise removal, then to an AD conversion circuit fllll, and then input to a servo microcomputer that detects a tracking error and switches the tape speed. Furthermore, when the level of the second sample-and-hold output fluctuates, it can be considered that the reproduction tape speed does not match the recording tape speed. Therefore, although not shown, a second sample and hold circuit (9
), the tape speed discrimination circuit that follows detects a large level change in the sample-and-hold output and switches the playback tape speed.

Therefore, according to the conventional circuit described above, the tape speed is switched due to the error signal during the recording speed detection period, and the running (phase) of the tape is controlled using the error signal during the tracking error detection period.

e→ Problem to be Solved by the Invention However, in the prior art described above, when the first sample and hold circuit (8) is omitted and the error signal is input directly to the low-pass filter, the time constant of the low-pass filter is Since the setting is relatively long, the correct A is maintained until the low-pass output level returns to the original level after the recording speed detection period.
D conversion is not possible, and the period in which AD conversion is possible is short and limited, making it impossible to correctly detect fz''ll-rough king errors.Also, if the time constant of the low noise filter is close to 1 field or more, the error output level The DC component of the signal decreases, making AD conversion difficult over the entire period.

Therefore, in view of the above points, the present invention is characterized in that even if the first sample and hold circuit (8) is omitted, the DC component of the error output does not decrease or increase.

(2) Means for Solving the Problem Therefore, in view of the above-mentioned points, the present invention provides a buffer period in which the reference signal frequency is selected following the recording speed detection period so that the error signal has the opposite polarity to that of the recording speed detection period. It is characterized by providing.

(E) Effect Therefore, according to the present invention, fluctuations in the DC level of the error signal that occur due to the error signal in the recording speed detection period are canceled by the error signal in the buffer period, and fluctuations in the DC level are eliminated. .

(f) Example Hereinafter, the present invention will be explained according to an illustrative example. 1st
The figure shows a circuit block diagram of the tracking servo circuit of this embodiment. The feature of this embodiment is that the first sample and hold circuit is omitted compared to the conventional circuit shown in FIG. The point is to change the signal arrangement.

The reference signal of this embodiment forms a recording speed detection period of 100 μsec and a buffer period of 100 μsec at the center of the tracking error detection period, and the reference signal frequency in the previous field is also transmitted during the recording speed detection period. The buffer period is characterized by selecting the reference signal frequency in the subsequent field (Fig. 3 f).
reference).

Therefore, in this embodiment, a reference generation circuit is formed which consists of blocks as shown in FIG. First, the head output switching pulse (Fig. 5A
) is used to derive a field pulse generating circuit (field pulse CP which is input to l'l and whose phase is synchronized with the rising and falling edges of the head output switching signal).

This field pulse (P) is input to a 2-bit down counter (13 counts down in synchronization with head output switching, and the field pulse I) is input to the first. Second latch circuit +14! (151 latches the count output of one field before and two fields before to function as a shift register. Therefore, the down counter (131, and the first and second latch circuits (141α
will derive three consecutive count outputs.

On the other hand, the gate control circuit that inputs the switching pulse (P) (1 mark indicates 100 μsec near the center of the field)
A third gate control pulse (g3) of , and a S1 gate control pulse (gl) of (IQQμseC) following the third gate control pulse (g3) are formed, and the first and third gate control pulses (gl) (g3) are formed. The second gate control pulse (
gl). Therefore, the third gate control pulse (
g3) is the recording speed detection period - the second gate control pulse is the tracking error detection period, and the first gate control pulse (g
l) respectively form a buffer period. 1st. Second. Third
The timing of generation of the gate control pulses (gl) (gl) (g3) has a relationship as shown in FIG. Therefore, the second gate control signal (gl) is input to the second gate circuit side which inputs the first latch output, and the first gate control pulse (gl) is input to the second gate circuit side which inputs the first latch output.
gl) is input to the first gate circuit α9 which inputs the down counter output, and the third gate control pulse (g3) is input to the second gate circuit α9.
On the other hand, the oscillation output of the master clock oscillation circuit is input to each E1, f2, E3, and f4 generation circuit r2℃■■ (Incorporated) that functions as a frequency divider circuit, and each generates four types of reference signals. The first reference signal is input to the first switch ■, the second reference signal is input to the second switch ■, the third reference signal is input to the third switch (to), and the fourth reference signal is input to the fourth switch. . Each of these switches receives a switching control signal (Sl) (Sl) (S3) (S4) derived from a decoder.
controlled by.

That is, when the count output value is @00'', the decoder outputs the first switching output (Sl) to select the first reference signal, and when the count output value is ``01'', it outputs the second switching output (Sl) to select the second reference signal. Select the reference signal and
When the output is "10", the third switching output (S3) is generated to select the third reference signal, and when the output is "11", the fourth switching output (34) is output and the fourth reference signal is selected.As a result, The reference signal is shown in Figure 3 f.
The switching is derived in the order shown in . The specific configuration of the reference generation circuit (2) described above is just one row, and various other configurations are possible, and it is possible to configure it not only by hardware but also by software using a microcomputer.

The reference signal consisting of the above arrangement is sent to the mixer (2)
When input to the error signal (e), the error signal (e) has a waveform as shown in FIG. 3(e). In other words, the polarities of the error signals in the speed detection period and the buffer period are opposite, and the periods are also equal, so the time constant is 4.
If input to the 6m5ec noise removal low-pass filter (II), the DC level will not fluctuate (the peak will be canceled. In other words, the output of the low-pass filter II will be
Fluctuations in the DC level caused by the error signal during the speed detection period are canceled by the error signal during the buffer period.

Therefore, the AD conversion circuit (111) which inputs the low-pass filter output can perform AD conversion without stopping AD conversion during the entire period. However, in this embodiment, the FC pulse of the 893 kk capstan is used as the AD conversion pulse. AD in the vicinity of 200μsec of the speed detection period and buffer period.
Conversion is paused only once.

In this embodiment, this AD conversion output is input to the microcomputer, and after digitally performing phase compensation within the microcomputer, the drive voltage of the capstan motor is derived as a digital value. Therefore, the capstan drive circuit converts the derived digital value into an analog value to form a drive voltage for the capstan motor.

The output of the second sample and hold circuit is also compared with the reference level (0 level), binarized, and input into the microcomputer, and when the recording speed and playback speed do not match, The data value derived as the capstan drive voltage is switched.

(g) Effects Therefore, according to the present invention, even if the sample and hold circuit is omitted, the error signal can be used as it is as an error signal for tracking error detection, and the circuit can be simplified.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram showing one embodiment of the present invention, and FIG.
3 shows a circuit block diagram of the same main part, FIG. 3 shows a signal waveform diagram of the main part, FIG. 4 shows a circuit block diagram of the conventional circuit, and FIG. 5 shows a signal waveform diagram of the main part. (2J...Reference generation circuit, (8)...1st
Sample hold circuit, 00...low pass filter,
(11)...AD conversion circuit.

Claims (2)

[Claims] (1) Switching four types of pilot signals for each recording track in a predetermined order and reproducing the reference signal frequency in order to reproduce a videotape made by multiplexing the pilot signal and the FM video signal.Switching of the pilot signal frequency In addition to forming a tracking error detection period by switching in conjunction with a recording speed detection period is selectively selected, an error signal is formed by frequency-separating the beat components of the reproduction pilot signal and the reference signal and comparing the levels; In a video tape recorder of the type in which a tape speed control signal is formed based on the recording speed detection period and a tape speed switching signal is formed based on the error signal of the recording speed detection period, a reproduction pilot signal is generated immediately after the recording speed detection period. A reference signal forming circuit characterized in that a buffer period is formed by selecting a reference signal frequency whose beat component is the other frequency for forming the error signal. (2) The reference signal forming circuit according to claim 1, wherein the buffer period is equal to the recording speed detection period.