JPS611179A - Recording mode discriminating circuit - Google Patents

Abstract

PURPOSE:To discriminate effectively a mode discriminating circuit by frequency- dividing a tracking period in response to a tape speed, discriminating the period of a frequency division output and discriminating the recording mode to discriminate the recording mode even at the high speed reproducing mode. CONSTITUTION:An injected pilot signal frequency is switched by RF switching RF at generation 1 of injected pilot signal, a beat of a reproduced and injected pilot signal is outputted by a mixer 2, the beat component is separated by 46, 16K filters 3, 4 and the level is compared (5). A tracking error signal is outputted through the comparison (5) and an error signal is frequency-divided at double speed reproduction by a variable frequency division circuit 8. The frequency division output is counted by a prescribed time counter 10, and the final count value of the counter 10 deviated from a prescribed value is detected by a decoder 13. An FF17 inverts the state by using the detected output of the decoder 13, the period of the circuit 8 is discriminated and a mode discriminating signal is outputted from the FF17. Then the recording mode is discriminated at the high speed reproducing mode.

Description

[Detailed description of the invention] g) Industrial application field The present invention relates to an 8 mm video recording mode discrimination circuit.

In the conventional 8mm video, instead of forming a control track like a general VTR, a tracking pilot signal is superimposed on the video trunk, and during playback, the beat component from the injected pilot signal is extracted and the signal is adjusted according to the level difference. It allows for tracking.

On the other hand, 8mm video has a standard recording mode and a double long-time recording mode, making it necessary to determine the recording mode during playback. Therefore, the applicant first applied for Japanese Patent Application Publication No. 59-71
No. 149 proposed a method for determining the recording mode in the normal playback mode. This discrimination principle is to identify the period by capturing the periodic level change of the tracking error while switching the frequency of the injection pilot signal at the field period. However, the above-described configuration is effective only in normal playback mode and cannot operate in high-speed playback mode.

(c) Purpose of the Invention Therefore, the present invention proposes a novel and effective recording mode discriminating circuit that is capable of discriminating the recording mode even in high-speed playback mode.

B) Structure of the Invention The present invention (-) The recording mode is determined by dividing the tracking error period according to the tape speed and then identifying all the periods of one branch output.

(e) Examples Hereinafter, a description will be given according to an example in which one flfi can be illustrated.

First, to explain the discrimination principle of this embodiment.

The playback mode and tracking error period will be explained.

As is clear from the above-mentioned Japanese Patent Laid-Open No. 59-71149, an error occurs when a tape recorded in standard mode is played back in standard mode, or when a tape recorded in long-term ID mode is played back in long-term mode. If the signal does not change significantly and a tape recorded in standard mode is played back in long-time mode, the error signal frequency will be z5 Hz, and the error signal will be 5 Hz if a tape recorded in long-time mode is played back in village standard mode. The signal frequency will be 15Hz. Therefore, if the error output is frequency-divided by % only when re-compressing in the standard mode, the error signal (or its %-frequency-divided output) generated when erroneous reproduction is performed will be 7.5 Hz.

FIG. 3 shows scanning traces and error signal changes when a tape recorded in the standard mode is played back at high speed in the standard mode. As is clear from this figure, the 5x playback scan trace (T3
), the error signal (IP') is 50)
i Z, the error signal (P5) when scanning the raw scan trace ('[' 5) multiplied by 5 becomes 6 (JHz, 5
The error signal (PB5) when scanning the double-speed reverse reproduction scan trace (TBS) is 90 Hz, and the error signal (PB2) when scanning the double-speed reverse reproduction scan trace rTB2)'(ll-) is 45 Hz. The above-mentioned relationship is also common when a tape recorded in the long-term mode is played back in the long-term mode.

Therefore, when n(n't-1) times speed reproduction is performed correctly, the error signal frequency fe is fθ=t1 to 1n-
It becomes 11. On the other hand, when the tape described in 21 is produced in the long 1.118°C mode in the anchor mode at T1 times speed.

The error signal frequency fθ is fθ=4i512n-11
becomes. In addition, record in the parrot mode and record the tape for a long time.
(When reproducing n times in J mode, the error signal frequency fe is fe = 151 (n/2) -' l. The above relationship is specifically shown in Figure 4 and Figure 5, C. It is.

Therefore, considering the above relationship, if the frequency is divided by the error signal @21n-t l during n (n≠1) times speed playback, if the recording mode and playback mode match, the 1-frequency output will be Z5.
It becomes HZ.

Therefore, during normal playback, the frequency division output should not be 75HZK, and during n-times fidelity playback, the frequency division output should not be 7.5H'!
It is necessary to change the tape speed so that

@1 Figure shows a circuit block diagram of this embodiment. According to this embodiment, the injection pilot signal generation circuit (1) switches the frequency of the injection pilot signal derived by the R-P switching pulse (head switching output) (RF) switched in the field period, and the mixer (2) In this step, the beat components of the reproduced pilot signal and the injection pilot signal are derived. Of this beat component, 46KHz component and 16
The KH8 components are separated by 46 filters (3) and 16 filters (4), respectively, and their levels are compared in a comparison circuit (5). Since the sign of this comparison output is inverted at the field period, the comparison output and its inverted output are alternately separated and derived by the changeover switch (6). This switching output (a) is used by the capstan servo as a tracking error signal during normal reproduction. In this embodiment, this (tracking) error signal (Fig. 2a) is input to the waveform shaping circuit (7) and converted into a rectangular wave (Fig. 2b) r according to the sign of the error signal. This square wave 0)
is input to the variable frequency divider circuit (8). This variable frequency dividing circuit (8) has a division ratio determined by a frequency division control circuit (9), and the division ratio determined by the division control circuit (9) is as follows.
n (n'!=1) It is specified that the frequency is divided by (n-1) during double speed playback. Note that during normal playback, % frequency division is specified in standard playback mode, and no frequency division is specified in long-time playback mode.

Therefore, when n times speed reproduction is performed correctly, the frequency division output is 7.5 Hz, and even when normal reproduction is performed erroneously, the frequency division output is 5 Hz.

The counter 0CJ uses the branch output (C) as the counting input.

A reset pulse with a period of 32 fields is input.

This reset pulse includes an RF switching pulse (f
) is input to the 1752 frequency divider circuit aD, and the divided output (bleeding) obtained by inputting it to the delay circuit r1z, the delayed pulse color obtained is utilized. However, the delay time is set to about 0.5 fields. Therefore, the count value of the counter CIO becomes .degree.4 plows only when the counter CIO receives the branch output of 7.5H2.

The decoder (13 is the count output (a) of this counter scream “4”
° is detected and a high level decode output Ce)k is generated.

During high-speed playback, the polarity of this decoded output is inverted, and it is input to the D terminal of the first flip 70 (I51) via the high-speed side terminal (sp) of the mode switch 114, and is input to the normal terminal (NM) k during normal playback. It is input as is via the

This 17th lip-flop 9 uses the frequency-divided output of L152 as a clock input, and changes from a low level to a high level when the recording mode and the reproduction mode do not match.

An AND circuit (161) receives the 17th lip 70 output (i), the delay pulse, and the mute signal.

After the operation of the 8mm video stabilizes and the mute signal becomes high level, when the first flip 70 tube output becomes high level, a mismatch in the playback mode with respect to the recording tape is detected and an inversion pulse (j) is sent. Force order.

The 27th lip 70 inputs this inverted pulse, and both terminals of the inverted output iD are inputted, and the high level output determines the standard reproduction mode, and the low level output determines the long reproduction mode. Therefore, this second flip-flop is
When the recording mode and the reproduction mode do not match, the reproduction mode is always made to match the recording mode by inverting the output level.

The mode discrimination signal, which is the output of this flip-flop, is input to the capstan control circuit in addition to the frequency dividing circuit (9) and is used to switch the tape running speed. Due to the well-known circuit configuration that is also used in current VH8 and Beta type VTRs,
A detailed explanation will be omitted.

Although the reproduction mode is made to match the recording mode by the above-described operation, the rotation of the capstan motor becomes unstable at the time of speed switching. Therefore, in this embodiment, each time the output of the 27th lip 70 is inverted, the mute signal is set to a low level for a certain period of time, and the 1 discrimination operation is performed only when the capstan motor is rotating stably. Ru.

(f) Effects of the Invention According to the present invention, as long as the tape is being played back at a constant speed, the recording mode can be determined.

The effect is great. .

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram according to an embodiment of the present invention, @2
The figure is a waveform diagram of the same main part, Figure 3 is a diagram explaining the error signal waveform during n-times speed playback, Figure 4 is a diagram explaining the relationship between the standard playback mode and the error signal frequency, and Figure 5 is a diagram explaining the relationship between the standard playback mode and the error signal frequency. Figures illustrating the relationship between error signal frequencies are shown. (8)...Variable frequency divider circuit, alpha decoder, u7)
...Blip-flop, shout--counter. Dejima style Sanyo Electric Co., Ltd.

Claims (1)

[Claims] (1) In a video tape recorder, four types of tracking pilot signals are superimposed and recorded on a video track at field intervals, and during playback, the levels of specific beat components of the reproduced pilot signal and the injection pilot signal are compared to obtain a tracking error signal. a variable frequency dividing circuit that divides the tracking error signal into 1/m|n-1|(m is a natural number) during n (n is an integer other than 1) double speed playback, and counts the frequency output for a predetermined period. A recording mode discriminating circuit comprising: a counter for determining whether the final count value of the counter has exceeded a predetermined value; a decoder for detecting that the final count value of the counter has deviated from a predetermined value; and a flip-flop for inverting the state based on the detection output of the decoder.