JPH0248759A - Channel adapter controlling system - Google Patents

Abstract

PURPOSE:To reduce the occurrence of the start impossibility of an I/O due to control unit busy by updating a second address pointer after the channel adapter informs an I/O address the second address pointer points and a channel command when a central control part reads information. CONSTITUTION:A first address pointer 6-1 and the second address pointer 6-2 to show the address of a buffer memory 6 are provided, and these two address pointers are updated successively in accordance with the progress of processing. Then, the buffer memory 6 is used effectively, and simultaneously, the channel adapters 21, 22 are made capable of accepting start continuously as securing the contents stored in it as long as they are required. Thus, the start impossibility of the I/O due to the control unit busy can be reduced.

Description

[Detailed Description of the Invention] [Summary] A control unit relating to a control method for a channel adapter that is located in a data processing device connected to a host computer via a channel and controls data transfer in opposition to a channel. In order to reduce the occurrence of inability to start I/O due to busy conditions, a buffer memory is provided in the channel adapter to store ■/○ addresses and channel commands related to the activation of ■/O from the channel adapter. A first pointer and a second pointer indicating the address of the buffer memory are provided, and when starting from the channel, after storing the I/O address and the channel command in the buffer memory address indicated by the first pointer, the first pointer and the second pointer are provided. When the central controller 8m updates the pointer of the 8m, sends the startup status, and generates an interrupt to the central controller, and the central controller 8m reads the information, the channel adapter
After notifying the I/O address and channel command pointed to by the address pointer, the second pointer is updated.

[Industrial application field]

The present invention relates to a control method for a channel adapter that controls an I/O interface of a data processing device that performs data communication with a host computer via a channel.

In recent years, as computer systems have become faster and larger, I/O control units such as communication control processing devices have come to control many high-speed Ilo's.

Therefore, processing that temporarily exceeds the control unit's capabilities may occur. Since activation from the channel cannot be accepted at this time, the channel adapter of the control unit responds with a control unit busy message. When this control unit busy increases,
The channel interface is occupied by this processing, reducing the efficiency of channel interface usage. As a result, the processing capacity of the entire system is reduced.

Therefore, in order to speed up the computer system, it is desired to reduce the response when the control unit is busy.

[Conventional technology]

FIG. 4 is a diagram explaining the operation of a conventional channel adapter, taking the case of a communication control processing device as an example.

In the figure, 51 is a host computer, 52 is a channel (
(hereinafter also referred to as CH), 53 is an interface cable,
54 is a communication control processing device (hereinafter also referred to as CCP); 55
is a channel adapter (hereinafter also referred to as CA), 56 is a central control unit (hereinafter also referred to as CCU), 57 is a line control unit, 5
8 represents a communication line.

In a system configured as described above, when the conventional channel adapter 55 receives activation from the channel 52, it stores an I/O address and a channel command in one register, and then issues an interrupt to the central control unit 56. The CCU 36 detecting this interrupt reads out the I/O address and channel command held in the register of the CA 35 and resets this interrupt. During this time, the CA 35 must guarantee the I/O address and channel command held in the register, so it will not accept the next activation until the interrupt is reset.

[Problem to be solved by the invention]

As described above, once an interrupt is generated in the central control unit, the conventional channel adapter does not accept any activation until the central control unit issues an instruction to reset the interrupt.

Further, when an interrupt factor with a higher priority than the interrupt factor occurs in the central control unit, activation related to the interrupt is kept open for a long time.

During this period, since activation from the channel was responded to by the control unit, there was a problem in that the usage efficiency of the channel interface deteriorated and the processing ability of the computer system decreased.

In view of these conventional problems, it is an object of the present invention to provide an out-of-control method that allows a channel adapter to continuously accept activations from a channel, thereby increasing the usage efficiency of the channel interface. It is an object.

[Means to solve the problem]

According to the invention, the above-mentioned object is achieved by the means specified in the claims. That is, the present invention provides a data processing device that has a channel adapter that connects to a channel of a host computer and a central control unit that controls the channel adapter, and that performs data communication with the host computer via the channel. A buffer memory that stores an I/O address and a channel command related to the generated activation, a first address pointer indicating an address value of the buffer memory, and a channel adapter notify the central control unit of the I/O address and channel command. and a second address pointer indicating the address value of the buffer memory to be referred to when the channel is activated, the channel adapter stores the I/O address and the channel command in the buffer memory, and
After updating the first address pointer, the activation status is sent to the channel, the channel adapter generates an interrupt related to I/O activation to the central control unit, and the central control unit interrupts the I/O activation status. When detected, the channel adapter repeatedly updates the second address pointer after reading the I/O address and channel command stored at the buffer memory address pointed to by the second address pointer. This is a control method for a channel adapter that accepts activation continuously.

[For production]

As described above, the present invention provides a first address pointer and a second address pointer that indicate the address of the buffer memory, and sequentially updates these two address pointers according to the progress of processing, thereby storing the buffer memory. The channel adapter can be activated continuously while ensuring that the stored contents are effectively used and stored for as long as they are needed.

Hereinafter, a detailed explanation will be given based on examples.

〔Example〕

The case where the present invention is applied to a channel adapter of a communication control processing device will be described below.

FIG. 3 is a diagram showing an example of the configuration of a communication control processing device implementing the present invention, in which 1 is a CCU, 2, 22 are channel adapters (CA), and 3+.

32 represents a line control unit, and 4 represents a system bus.

In the figure, CCU1 executes a control program within CCU1 to control the entire communication control processing device. CA
2+ and 22 are connected to a channel of the host computer, and data transfer is controlled by instructions issued by a control program according to a defined channel interface.

Line control unit 3. ．． 3. is connected to the line and performs line control based on commands issued by the control program.

FIG. 1 is a diagram showing an embodiment of the present invention, and shows the configuration of a channel adapter of a communication control processing device. In the figure, a system bus control unit 5 performs control of commands issued by a control program and interrupt control when accepting or accepting activation.

The memory 6 holds the firmware and information, startup addresses, and commands necessary for the firmware to execute. The microprocessor 7 reads and executes the firmware. The channel interface control section (
CHi FC (hereinafter also referred to as CHi FC) 8 receives information such as activation addresses and commands from the channel according to the channel interface.

FIG. 2 is a flowchart showing the control of the embodiment.

The operation will be explained below with reference to FIGS. 1 and 2.

The information necessary for the firmware 6-4 to implement the present invention to execute includes information on where to store the startup address and command in the memory 6 when the startup is received (hereinafter referred to as pointer 17), and the control program. (hereinafter NC
The memory 6 holds information (hereinafter referred to as pointer 2) about which data on C8 is to be responded to when the activation address and command are read from pointer P (hereinafter referred to as pointer 2).

When first activated from a channel, CHi Fe2 detects this and raises an interrupt to firmware 6-4 running on microprocessor 7. Firmware 6
-4 is the area 6-3 that holds the startup address and commands
It is determined whether the buffer area (hereinafter referred to as the buffer area) is -full or not, and if it is -full, a bit responsive to control unit busy (hereinafter referred to as CU-BUSY) of the control register 81 in CHiFCg is turned on. By this, C
Hi Fe2 is cu-su of 7yoto busy sequence
Reply with sy.

If not, turn on the bit in control register 8-1 in CHi Fe3 to continue processing. Then C
HiFC8 performs a startup sequence. When CHiFC8 receives a channel command, the firmware is interrupted. The firmware reads the startup address and command from the data register 8-2 and points it to pointer 1 indicated by 6-1.
The contents are stored in the buffer 6-3 as an address.

Then, create a startup status for the channel, store the startup status in the data register 8-2 in CHiFC8, and then store it in the control register 8-1 in CHi Fe3.
Turn on the status transfer request bit. Then CH
i Fe2 sends activation status. When the startup sequence is completed, an interrupt is generated from the CHiFC 8 to the firmware, and the startup interrupt bit of the interrupt control register 51 in the system bus control unit 5 is turned on in order to raise the startup interrupt to the firmware or NCP. This causes a startup interrupt to the NCP.

NCP issues command 9 to read the boot address and command.
Output on the system bus indicated by .

The data on this system bus 9 is transferred to the system bus control unit 5.
decodes the instruction data and sends it to the instruction control register 5-2.
and generates an interrupt to the firmware.

As a result, the firmware 6-4 reads the start address and command from the buffer 6-3 using the contents of pointer 2 indicated by 6-2 as an address, and stores them in the instruction control register 5-2 in the system bus control unit 5. . The command is now completed and the NCP can recognize the activation address and command.

Upon recognizing these, the NCP issues a command to reset the activation interrupt. Then, like the previous instruction, an interrupt occurs in the firmware 6-4.

The firmware 6-4 determines whether there is a startup address or command held in the buffer 6-3, and if not, resets the startup interrupt, but if so, does not reset the startup interrupt. The NCP only has to repeat these processes as if this activation interrupt had been reset. In a communication control processing unit, the priority of line control is generally higher than channel side control, so if a lot of line control is occurring or if other CA
Even when interrupt processing is being executed and interrupts cannot be accepted, by doing the above, it is possible to continue accepting interrupts until the buffer is full.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to improve the usage efficiency of the channel interface caused by overload of the control program of the channel adapter, so that the processing efficiency of the channel interface is improved.

This has the advantage that the processing capacity of the entire system can be expected to improve.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a flowchart showing control of the embodiment, FIG. 3 is a diagram showing an example of the configuration of a communication control processing device implementing the present invention, and FIG. FIG. 2 is a diagram illustrating the operation of a conventional channel adapter.

Claims (1)

[Claims] A system comprising: a channel adapter connected to a channel of a host computer; and a central control unit controlling the channel adapter;
In a data processing device that performs data communication with a host computer via a channel, a channel adapter has a buffer memory that stores an I/O address and a channel command related to activation generated by the channel, and a first buffer memory that stores an address value of the buffer memory. and a second address pointer indicating the address value of the buffer memory that the channel adapter refers to when notifying the central control unit of the I/O address and channel command. The adapter stores the I/O address and channel command in the buffer memory, updates the first address pointer, and then sends the activation status to the channel, and the channel adapter starts the I/O. When an interrupt is generated to the central control unit and the central control unit detects the interrupt, after reading the I/O address and channel command stored at the buffer memory address pointed to by the second address pointer. A control method for a channel adapter, characterized in that the channel adapter repeatedly updates a second address pointer, thereby continuously accepting activations.