JP3071210B2 - Task management control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a task management control system for managing execution of a plurality of tasks having a plurality of priority levels, in which a task corresponding to an interrupt request is switched at a high speed, and a P-level task is performed. A task having a plurality of priority levels and a task of the priority level provided in one-to-one correspondence with each of the priority levels are queued. In a task management control method having a priority level queue and preferentially executing a task queued in the highest priority level queue, a task executing means for executing the task of each priority level; It has a priority level queue for each priority level, and when an arbitrary task execution request is made by interrupt or program startup, Task management means for queuing the task requested to be executed in a priority level queue corresponding to the priority level of the task, and outputting queuing priority level information indicating the priority level of the queued task; First storage means for storing all priority levels of tasks currently waiting to be set, which are set based on the priority level information output from the task management means; and Second storage means for storing the priority level of the task in question, wherein when the queuing priority level information is output from the task management means, the priority level indicated by the queuing priority level information is stored in the first storage. Means, and based on information stored in the first storage means and the second storage means, The priority level of the task currently being executed by the task execution means is compared with the priority level of the task currently waiting for execution, and if the task waiting for execution has a higher priority level, the task It outputs switch priority level information indicating the highest priority level among the task switch command signal requesting switching and the priority level of the task waiting to be executed, while the priority level of the currently executing task is higher. If it is higher, the task switch command signal is not output, and the execution task selection means is not provided.The task management means is provided independently of the task execution means, and the execution task selection means is the task execution means or the task execution means. The task execution means is provided independently of any of the task management means. The information indicating the priority level of a task and sets the second storage means in said execution task selection means, the task switch instruction signal from said execution task selection means and by entering the said switch priority level information,
Suspends the execution of the currently executing task, newly executes the task queued at the top of the priority level queue corresponding to the priority level of the higher-level task, and executes the task after completion of the task execution. Determines whether the task is queued in the priority queue corresponding to the same priority level as the task that was waiting, and if the task is queued, starts executing the task. If the task is not queued, The execution of the task interrupted by the input of the task switch command signal is resumed, and information indicating the priority level of the task is written to the second storage means in the execution task selection means.

[Industrial applications]

The present invention relates to a task management control method for managing execution of a plurality of tasks having a plurality of priority levels.

[Conventional technology]

Generally, there are four types of activation factors for tasks of information processing devices such as programmable controllers: cyclic task activation, fixed-cycle interrupt task activation by interval timer external interrupt task activation, program interrupt task activation (soft enter, etc.). Examples of priority levels include a P-level task by starting a cyclic task, a periodic interrupt, an external interrupt, a 1-4 level task by starting a soft interrupt task, and a 0-level task by starting an external interrupt and a program interrupt task. The number of priority levels of this task is determined by the specifications and scale of each device.

6 (a) to 6 (f) are diagrams showing examples of task priority levels provided in the programmable controller and task numbers defined in each priority level. FIGS. 7A to 7F are examples in which the priority level of a task is determined by the task number.
In some cases, the priority level of a task can be freely set.

The task priority level is set to P <4 <3 <2 <1 <0. P-level tasks are dispatchers (di
X'00 '→ X'01' → …… → X'3E '
.. X′3F ′ → X′00 ′ → X′01 ′..., The tasks having the respective task numbers are stored in the P-level task number storage table shown in FIG. Performed cyclically. The level tasks of “1” to “4” include, for example, a fixed-cycle start that is started at a certain fixed time interval (for example, 100 msec), an external interrupt start based on plant input information, or an enter from program processing. It is executed by activation. The 0-level task is mainly used for system initial processing, serious failure processing, and the like, and is executed by activating the program processing or activating an external interrupt.

Next, the operation of the task will be described with reference to FIG. X'00 'in the storage order of the table shown in FIG.
X'01 '→ X'02' and the P-level task are executed, and X
If a task execution request for a three-level X'61 'task is issued while the' 02 'task is being executed, the execution of the X'02' task is interrupted and processed to a higher three-level X'61 'task. Moves. Then, when the execution request of the task of the one-level X'70 'occurs while the task of the three-level X'61' is being executed, the task of the three-level X'61 'is interrupted and the one-level X'61' is interrupted. Execution right is transferred to task '70'. Then, while this one-level X'70 'task is being executed, the two-level X'70'
Even if there is a request to execute the task of '6F', the execution of the task of X'6F 'is waited until the task of X'70' is executed, and is accepted after the execution of the task of X'70 'is completed. ,
Execution shifts from the task X'70 'to the task X'6F'. Similarly, if an execution request is issued from a higher-level task during execution of any task, the execution of the above-mentioned arbitrary task is suspended, and the execution right is assigned to the higher-level task. After the transition and the processing of the higher-level task is completed, the lower-level arbitrary task is executed again.

In FIG. 7, the task X'51 'is shifted to the task X'02'.
X'02 '→ X'03' ... → X'3E 'after the execution right has been transferred to the task (continuous execution)
The P-level tasks are cyclically executed in the order of → X′3F ′ → X′00 ′ → X′01 ′.

As one conventional method of such task management, there is an example in which both task execution and task management are performed by a single processor. In this case, task execution processing, interrupt event management processing, and when an event occurs or when 1 At the end of the task, the decision process (dispatch) to determine the task to be executed next is performed serially.
C user program (application program)
However, there is a problem in that the overhead required for the task switch as described above increases.

Further, as another example of the conventional task management method, in order to reduce the overhead, an execution processor that performs task execution and a task management processor that performs interrupt event management and task management and that can perform parallel processing with the execution processor are used. FIG. 8 shows an example of the system configured.

In FIG. 1, a program memory 11 is a memory such as a ROM (read only memory) or a RAM (random access memory) in which a user program composed of a plurality of tasks composed of macro instructions is stored, and a fetch control. The circuit 20 is a circuit for fetching a macro instruction from the program memory 11, and includes a program counter (PC) 21 and an instruction register (iRG) 22 in which the macro instruction is stored. The MAP control circuit 13 is a MAP control circuit for interpreting (decoding and executing) an instruction and for activating the execution processor 1 which decodes and executes a macro instruction by a microprogram control method described later. The data memory 30 is a task N which is an address table that manages the start addresses of all tasks stored in the program memory 11 in correspondence with the task numbers for each task.
o. Entry table 31 (hereinafter referred to as TET31), and the tasks that have been executed up to now when switching tasks in interrupt processing, include various information such as a program counter (hereinafter referred to as PC) and a stack pointer for each interrupt level. (0-4
Interrupt control file 32, which is the area saved to the level
(Hereinafter referred to as iRTCB32).

The execution processor 14 and the data memory 30 are connected to each other via an internal bus 50.
Are connected to an external system bus 60 (not shown).

The task management processor 40 detects events such as an external interrupt, a program interrupt from the execution processor 14, and a fixed-cycle interrupt from a fixed-cycle timer (interval timer) 41, and the like. First-in-first-out (FIFO) for registering an event with a task number corresponding to the queue file of the corresponding interrupt level among the 0 to 4 levels
An interrupt request queue file 43 having a structure, an interrupt control file 45 in which task management information (interrupt mask information and the like) at each execution level is written, an interrupt mask register 44 for each level, and a task number of a P-level task. It consists of a task number management file 46 to be managed.

As described above, the execution processor 14 employs a microprogram control method, and during execution of one task,
The macro instruction stored at the address pointed to by the PC 21 from the program memory 11 is fetched into the iRG 22 and the MAP control circuit 13
In the case of a normal instruction, various operations and data transfer are performed as micro-interpreter processing. The task is executed one instruction at a time by repeating this MAP → operation → MAP → operation... This processing corresponds to E in FIG.
The user program described by the macro instruction by the map control is mapped to the start address of the interpreter (decoding and execution of the instruction) corresponding to the macro instruction described by the micro instruction so that the predetermined program corresponding to the macro instruction is determined. And performs various data calculations and data transfer processing. In parallel with these execution processes, the task management processor 40 performs the following processes.

T The event detection mechanism 42 detects an external interrupt, a periodic interrupt from the periodic timer 41, and a program interrupt from the execution processor 14.

T When an interrupt event occurs, the task that has issued the interrupt request is stored in the interrupt request queue file 43 corresponding to the interrupt request level of the task by the task number.

T If the task number of the unmasked interrupt level is queued in the interrupt request queue file 43 based on the information of the interrupt level mask register 44 corresponding to the level of the task currently being executed (by software means) Judgment), saves the task management information (level No., mask register information, etc.) of the task that has been executed up to the area corresponding to the interrupt level of the currently executing task in the interrupt control file 45, and newly executes the task. Mask information corresponding to the level of the task to be set is set in the interrupt level mask register 44, and a task switch command is set to MAP
It notifies the control circuit 13 and the task number and level of the task to be newly activated by the interrupt to the execution processor 14.

T Delete the task number of the newly started task from the interrupt request queue file 43. Subsequently, the execution processor 14 performs the MAP processing by the task switch command,
The process is mapped to the task activation interrupt processing routine, and the following processes E to E are performed by executing the task activation interrupt processing routine.

E Data memory corresponding to the task level activated by the interrupt notified from the task management processor 40
Various task information (program counter, stack pointer, etc.) of the task of the level executed so far is saved in the interrupt control file 32 in 30.

E Task N notified from task management processor 40
The start address of the new interrupt task in the program memory 11 for the task having the task o.
And then execute the new interrupt task
Execute while repeating P → calculation → MAP → ...

E When a task end instruction is fetched, a task end interrupt is issued to the task management processor 40. As a result, the execution processor 14 waits for a task switch command from the task management processor 40.

Next, the task management processor 40
When a task end interrupt is added from step (1), the processing of T shown below is performed.

T Search the interrupt request queue file 43 for a level area equal to the level of the currently executing task (currently executing task level area).
MAP the same level task switch command again
After outputting to the control circuit 13 the task number and task level of the task to be activated by the interrupt to the execution processor 14, the processing T is performed.

The execution processor 14 performs the process E without performing the process E by the mapping process based on the task switch command.

On the other hand, if there is no required task number in the current execution level area in the processing T, the task management processor 40 performs the following processing T.

T The task management information of the task of the previous execution level saved from the interrupt control file 45 is restored, and the mask register information of the task of the previous execution level is set in the interrupt level mask register 44. MAP a task switch command to switch to another task
The control circuit 13 is notified.

When the task switch designation is added, the execution processor 14 performs the following processing E by MAP processing.

E Read various task information (PC, stack pointer, etc.) of the lower-level task that was previously executed from the level area equal to the level of the currently executed task in the interrupt control file 32, and The registers, flags, etc. are reset, and the MAP → operation →... Processing of the previously executed task is restarted again.

The above is the operation of the interrupt task, but the same applies to the P-level task.
The process of T shown below is performed by the end interrupt of the P-level task.

The task number to be executed next is obtained from the TP level task number management file 46 (the P level task is X'00 '→
X'01 '→ ... n (n is any positive hexadecimal value) → X'00' → ...
The task number of the task to be cyclically executed is determined as follows: → n → X'00 '), and a task switch command is sent to the MAP control circuit 13 as in the process T, and the task to be started is The task number and its level (P level) are notified to the execution processor 14.

The execution processor 14 performs the processing E without performing the processing E by the mapping processing based on the task switch command.
Similarly to the above, the start address of the storage area of the P-level task in the program memory 11 is set in the PC 21, and the P-level task is executed. Then, when the task end instruction is fetched, the process E is performed, and the task management processor 40 performs the process T again.

As described above, also in the P-level task, the handshake is performed between the task management processor 40 and the execution processor 14 by the task switch command from the task management processor 40 and the task end interrupt from the execution processor 14 similarly to the interrupt task. The task is performed.

[Problems to be solved by the invention]

In the above-described system in which task management and task execution are serially processed by a single processor, there is a problem that the overhead of task management processing in executing a user program is considerably large.

In addition, in order to reduce the overhead, in addition to the execution processor 14, the task management processor 40 is provided, and in parallel with the execution of the task by the execution processor 14, the task management processor 40 performs a task management process,
Event management, P-level task execution management,
It is not necessary to register / delete in the interrupt queue file 43 and save / restore in the interrupt control file 45, and handshake in the form of a task switch command / task end interrupt between the execution processor 14 and the task management processor 40 at the time of task switching. The processing becomes overhead. In addition, the start management of the interrupt task is performed by the task management processor 40, when an interrupt request is generated, by performing software priority determination with respect to the currently executed task level, and even when one interrupt task ends, the task to be executed next is determined. The task number is determined by notifying an interrupt from the execution processor 14 to the task management processor 40, and the task management processor 40 determines the task by software based on the notification. Contributes.

An object of the present invention is to switch a task corresponding to an interrupt request at a high speed, and to switch a P-level task at a high speed.

[Means for solving the problem]

 FIG. 1 is a diagram illustrating the principle of the present invention.

The present invention includes a task having a plurality of priority levels and a plurality of priority level queues provided in one-to-one correspondence with the respective priority levels, in which the tasks of the priority level are queued, and the level is also high. It is assumed that a task management control method for executing tasks queued in a priority level queue preferentially is performed.

 The means of the first invention described in claim 1 is as follows.

The task executing means 1 is composed of, for example, a microprocessor or the like, and executes the tasks of the respective priority levels.

The task management means 2 comprises, for example, a microprocessor or the like, and has a priority level queue 2-0 for each priority level.
When an execution request for an arbitrary task is made by an interrupt or a program activation, the requested task is placed in a priority level queue 2-0 to 2-N corresponding to the priority level of the task. And turns on the priority level signal of the queued task.

The task selecting means 3 comprises: first storing means 3a for storing all priority levels of tasks currently waiting to be set which are set based on the priority level signal output from the task managing means 2; Second storage means 3b for storing the priority level of the task currently executed by the execution means, and when the queuing priority level information is output from the task management means 2, The priority level indicated by the first storage unit 3a.
, And based on the information stored in the first storage unit 3a and the second storage unit 3b, waiting for the current execution of the priority level of the task currently being executed by the task execution unit 1. Compares the priority level of the task with the task, and if the task waiting to be executed has a higher priority level, it has priority over the task switch command signal requesting task switching and the task currently being executed. Outputs switch priority level information indicating the highest priority level among the priority levels of the tasks waiting to be executed having a higher level. On the other hand, if the currently executing task has a higher priority level, the task switch command is output. No signal is output.

The task execution means 1 sets information indicating the priority level of the task in the second storage means 3b in the execution task selection means 3 when starting execution of the task, and executes the execution task selection means. 3, when the task switch command signal and the switch priority level information are input, the execution of the currently executing task is interrupted, and the priority level queue 2 corresponding to the priority level of the higher-level task is interrupted.
-0 to 2-N, the task queued at the head of the task is newly executed, and at the end of the task execution, the priority level queues 2-0 to 2-N corresponding to the same priority level as the task executed so far. The first storage means 3a of the execution task selecting means 3 determines whether or not the task is queued
If the task is queued, the execution of the task is started.If the task is not queued, the execution of the task interrupted by the input of the task switch command signal is resumed, and the execution of the task is resumed. The information indicating the priority level is written in the second storage unit 3b of the execution selection unit 3.

The means of the second invention described in claim 2 is as follows.

First, in addition to the task execution means 1, the task management means 2, and the task selection means 3 which are the same as those of the first invention, the third
Storage means 4.

The third storage means 4 is composed of, for example, a memory such as a ROM (Read Only Memory) or a RAM (Random Access Memory), and executes and manages a plurality of P-level tasks that are started cyclically. And the task execution means 1 can directly access the information.

The information related to the execution and management of the plurality of P-level tasks includes, for example, the execution order of the P-level tasks and pointers indicating the entry points of the respective P-level tasks.

Then, the task execution unit 1 cyclically executes the plurality of P-level tasks in a predetermined order based on the information related to the execution and management of the plurality of P-level tasks stored in the third storage unit 4. To run.

[Action]

 The operation of the first invention is as follows.

The task management means 2 includes an external interrupt, a task execution means 1
Whenever a task start request due to a program interrupt from the server or a periodic interrupt from an interval timer is added, the task corresponding to the interrupt is
The task is queued in the priority level queue 2-i corresponding to the priority level "i" of the task, and the priority level signal indicating the priority level "i" of the queued task is turned on to the execution task selecting means 3. To

When detecting that the priority level signal has changed from off to on, the execution task selecting means 3 reads the first storage means.
After storing the fact that the task is queued at the priority level "i" in 3a, the queuing priority level of the current task in the priority level queues 2-1 to 2-n stored in the first storage means 3a Based on the information and the priority level information of the task currently being executed by the task executing means 1 stored in the second storage means 3b, the priority of the newly queued task is higher than that of the currently executing task. It is determined whether or not the priority is higher, and if the newly queued task has a higher priority level than the currently executing task, the task switch command signal and the priority level of the newly queued task are changed. The switch priority level information is output to the task execution means 1.

When the task switch command signal is added, if the task is currently being executed, the task execution means 1 interrupts the execution of the task, and the priority level queue 2 corresponding to the priority level "i" indicated by the switch priority level information. -Start execution of the task queued at the head of i.

On the other hand, when the task execution means 1 terminates the execution of the task, the task execution means 1 determines whether or not the task is queued in the interrupt priority level queue 2-i corresponding to the priority level "i" of the task that has been executed so far. If the task is queued, the execution of the task is started. If the task is not queued, the execution of the task interrupted by the input of the task switch command signal is executed. At the same time as resuming, the information indicating the priority level of the task is written in the second storage means 3b.

As described above, the task execution unit 1 does not perform handshaking with other units (the task management processor) as in the related art, and outputs the output information of the execution task selection unit 3 and the interrupt priority level queue 2 in the task management unit 2. -0 to 2-
Since the task to be executed can be known at a high speed by directly referring to N, the task corresponding to the interrupt request can be switched at a high speed.

Further, the second aspect of the present invention provides the function of the first aspect of the invention,
It has the following functions.

The task execution means 1 starts and executes the P-level task when no task with a priority level higher than the P level is queued in the interrupt priority level queues 2-0 to 2-N at the end of the task. 3 by directly reading the information stored in the storage means 4.

As described above, the execution / management of the P-level task is performed by executing the task by another means (the task management processor 40).
Can be performed without intervention, so that the switching of the P-level task can be performed at high speed.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 is a system configuration diagram of a first embodiment according to the present invention.

In this figure, the same blocks as those of the conventional system shown in FIG. 8 described above are given the same numbers, and detailed description of those blocks is omitted.

In the figure, a task level priority determining circuit 100
Is an interrupt request level register 101, an interrupt level mask register 44 for storing an interrupt mask corresponding to the priority level of the task currently being executed, and the two registers
And a priority encoder 102 for performing a level priority determination between 101 and 44.

The P-level task number management file 46 conventionally provided in the task management processor 40 is provided in the data memory 30 '. The task management processor 40 'of this embodiment has no interrupt control file 45 other than the interrupt level mask register 44 and the P level task number management file 46.

Next, the operation of the present embodiment having the above configuration will be described with reference to FIGS.
This will be described with reference to the flowchart in FIG.

Similarly to the conventional example, the execution processor 14 performs the following process E while executing any one task.

E When a normal instruction is fetched and mapped, various data operations and data transfer processing corresponding to the normal instruction are performed.

The execution processor 14 executes this MAP → operation → MAP → operation → ...
While the task management processor 4
For 0 ', the following processing T is performed following the processing T, T described above.

T Turns on the interrupt request level signal corresponding to the interrupt level obtained in the process T, and adds the signal to the interrupt request level register 101 of the task level priority determination circuit 100.

The priority encoder 102 of the task level priority determining circuit 100 includes an interrupt level mask register 44 corresponding to the level of the currently executing task set in advance by the execution processor 14 and a plurality of interrupt requests added from the task management processor 40 '. A priority determination is performed between the interrupt request level register 101 that stores the level signal and the task set in the interrupt request level register 101 has a higher level than the currently executing task.
A task switch command is output to the P control circuit 13, and the task level set in the interrupt request level register 101 is output to the execution processor 14. When interrupt requests from a plurality of tasks having higher levels than the currently executing task are set in the interrupt request level register 101, the priority encoder circuit 102 automatically outputs the level information of the highest interrupt level. And outputs it to the execution processor 14. On the other hand, when the level set in the interrupt request register 101 is lower than the level of the currently executing task, the priority encoder 102 does not output the task switch command to the MAP control circuit 13.

Next, the execution processor 14 is mapped to the task activation interrupt processing by the MAP processing performed by the MAP control circuit 13 similar to the conventional example in response to the task switch command, and performs the processing shown in the flowchart of FIG.

E The interrupt control file 32 corresponding to the interrupt activation task level added from the task level priority determination circuit 100
Then, various task information (program counter, stack pointer, mask information, etc.) of the task of the level executed so far is saved (similar to the process E).

E The interrupt level mask register 44 of the task level priority order determination circuit 100 is set so as to mask the interrupt of the task lower than the task level of the interrupt activation task added from the task switch priority order determination circuit 100.

E A task number to be activated is obtained from the interrupt request queue file corresponding to the above-mentioned interrupt activation task level in the interrupt request queue file 43 in the task management processor 40 '.

E Notify the task management processor 40 'of the task switch acceptance level (interrupt level of the newly activated task) by interruption.

E The start address of the program memory 11 in which the task having the interrupt task number is stored is obtained from the TET 31, the start address is set in the PC 21, and the execution of the new interrupt task is started (MAP → execution → MAP → The normal instruction is executed one instruction at a time by repeating execution.
〉).

The task management processor 40 'performs the processing shown in the flowchart of FIG. 5 when the task switch acceptance interrupt is added from the execution processor 14.

T The task number queued at the head of the queue file of the interrupt request queue file 43 corresponding to the level accepted by the execution processor 14 is deleted (the queue has a first-in first-out structure).

T On the other hand, when the queue file of the corresponding level is empty, the corresponding interrupt request level signal to be applied to the task level priority determining circuit 100 is turned off (OFF). If the queue file is not empty, the process immediately returns to the main routine.

On the other hand, when the execution processor 14 fetches and maps the task end instruction, as shown in the flowchart of FIG. 4, depending on whether the level of the currently executing task is the interrupt level (0 to 4 levels) or the P level, Perform different processing.

{In the case of interrupt level (0 to 4 levels)} E The level of the currently executing task is set to the interrupt level (0
(4 levels), the mask bit of the current execution level is canceled in the mask register 44 of the task level priority determination circuit 100, and then it is checked whether there is a task interrupt request of the same level as the current execution level. If the above-mentioned processes E to E are performed, otherwise, the following process E is performed.

E Restore various lower-level task information (PC, stack pointer, master information, etc.) that was previously executed from the corresponding level of interrupt control file 32, and re-execute MAP → Execute → M
Repeat AP → Execute →….

<< P-level task >> The task number of the next P-level task to be executed is found from the EP-level task number management file 46, and the start address of the storage area of the task in the program memory 11 is obtained from the TET31. To the PC 21 to newly execute the P-level task.

〔The invention's effect〕

As described above, according to the first aspect, means for queuing a task requested to be activated by an interrupt or program activation in the priority level queue, a task currently being executed, a priority level, and a new queue Means for outputting a task switch command signal by comparing with the priority level of the task that has been performed, and the task switch command output process can be performed at high speed in parallel with the task execution. It is possible to perform high-speed task switching.

Even at the end of the task, the task to be executed next can be found by directly referring to the task level priority determining circuit and the priority level queue, so that the task switching speed is increased.

According to the second invention, in addition to the effect of the first invention, the execution and management of the P-level task started cyclically is directly referred to the means for storing information relating to the P-level task. Therefore, overhead can be eliminated and P-level tasks can be switched at high speed.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining the principle of the present invention, FIG. 2 is a system configuration diagram of one embodiment according to the present invention, FIG. 3 is a flowchart for explaining processing of a task management processor, and FIG. FIG. 5 is a flowchart for explaining processing relating to an interrupt request queue file performed by the task management processor. FIG. 6 shows an example of task priority levels and task numbers defined for each priority level. FIG. 7 is a diagram showing an example of task execution management, and FIG. 8 is a diagram showing an example of a conventional task execution management system. 1 ... task execution means, 2 ... task management means, 2-0 to 2-N ... priority level queue, 3 ... execution task selection means, 3a ... first storage means, 3b ... second Storage means, 3c ... encoder, 4 ... third storage means.

Continuation of the front page (72) Inventor Tetsuhito Watanabe No. 1, Fuji-cho, Hino-shi, Tokyo Inside Fuji Facom Control Co., Ltd. (56) References JP-A-59-99553 (JP, A) JP-A-63-296139 ( JP, A) JP-A-62-123530 (JP, A) JP-A-63-308661 (JP, A)

Claims (4)

(57) [Claims] A task having a plurality of priority levels and a plurality of priority level queues provided in a one-to-one correspondence with the respective priority levels, in which the tasks of the priority level are queued, are the highest. In a task management control method for preferentially executing a task queued in a priority level queue, a task execution means (1) for executing the task of each priority level; a priority level queue for each priority level (2-0-2-
N), when an execution request for an arbitrary task is made by interruption or program activation, the task for which the execution request is made is stored in a priority level queue (2-0 to 2-N) corresponding to the priority level of the task. ) And a task management means (2) for outputting queuing priority level information indicating a priority level of the queued task; and the priority level information output from the task management means (2). The first storage means (3) stores all priority levels of tasks currently waiting to be set, which are set based on the first priority level.
a), and second storage means (3b) for storing a priority level of the task currently being executed by the task execution means (1), and the queuing priority level information is transmitted from the task management means (2). Is output, the priority level indicated by the queuing priority level information is stored in the first storage means (3a), and the first storage means (3
a) the priority level of the task currently being executed by the task execution means (1) and the priority level of the task currently waiting to be executed, based on the information stored in the second storage means (3b). Compare the priority level, if the task waiting for execution has a higher priority level, of the task switch command signal requesting task switching and the priority level of the task waiting for execution, Executing task selecting means (3) for outputting switch priority level information indicating the highest priority level, while not outputting the task switch command signal if the currently executing task has a higher priority level; The management means (2) is provided independently of the task execution means (1), and the execution task selection means (3) is provided with the task execution means (1) or The task execution means (1) is provided independently of any of the task management means (2). When starting execution of a task, the task execution means (1) transmits information indicating a priority level of the task to the execution task selection means (3). If the task switch command signal and the switch priority level information are input from the execution task selection means (3) while being set in the second storage means (3b) in ()), the execution of the task currently being executed is interrupted. Then, the task queued at the head of the priority level queue (2-0 to 2-N) corresponding to the priority level of the higher-level task is newly executed, and when the task execution ends, the task is executed up to that time. It is determined whether or not the task is queued in a priority level queue (2-0 to 2-N) corresponding to the same priority level as the task that has been queued. Execution of the task is started, and if the task is not queued, the execution of the task interrupted by the input of the task switch command signal is resumed, and the information indicating the priority level of the task is transmitted to the execution task selecting means. (3) A task management control method, wherein the data is written in the second storage means (3b). 2. The apparatus according to claim 1, further comprising: third storage means (4) for storing information relating to execution and management of a plurality of P-level tasks which are cyclically started and which can be directly accessed by said task execution means (1). The third storage unit (4) is provided independently of the task management unit (2), and the task execution unit (1) is stored in the third storage unit (4). 2. The task management control method according to claim 1, wherein the plurality of P-level tasks are cyclically executed in a predetermined order based on information related to the execution and management of the plurality of P-level tasks. 3. An execution task selection means (3) encodes data stored in said first storage means (3a) and said second storage means (3b) and outputs said task switch command signal. And an encoder (3c) for outputting the switch priority level signal.
Or the task management control method described in 2. A register for storing a priority level of the task currently waiting to be executed in correspondence with an interrupt request level of the task; 4. The task management control method according to claim 3, wherein 3b) is a register for storing information for masking an interrupt of a task having a priority level lower than a priority level of the currently executed task.