JPH0246054Y2 - - Google Patents

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Publication number
JPH0246054Y2
JPH0246054Y2 JP1981138160U JP13816081U JPH0246054Y2 JP H0246054 Y2 JPH0246054 Y2 JP H0246054Y2 JP 1981138160 U JP1981138160 U JP 1981138160U JP 13816081 U JP13816081 U JP 13816081U JP H0246054 Y2 JPH0246054 Y2 JP H0246054Y2
Authority
JP
Japan
Prior art keywords
die
semiconductor element
circuit board
bonding
wiring conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1981138160U
Other languages
Japanese (ja)
Other versions
JPS5842940U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Priority to JP1981138160U priority Critical patent/JPS5842940U/en
Publication of JPS5842940U publication Critical patent/JPS5842940U/en
Application granted granted Critical
Publication of JPH0246054Y2 publication Critical patent/JPH0246054Y2/ja
Granted legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15182—Fan-in arrangement of the internal vias
    • H01L2924/15183—Fan-in arrangement of the internal vias in a single layer of the multilayer substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Description

【考案の詳細な説明】 （産業上の利用分野） 本考案はICなどの半導体素子がダイボンドさ
れる構造の混成集積回路装置に関する。[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a hybrid integrated circuit device having a structure in which semiconductor elements such as ICs are die-bonded.

（従来の技術） 従来、素子裏面を絶縁させる必要のある半導体
素子を回路基板にダイボンドするとき、配線パタ
ーンを簡素化あるいは短縮させる目的で、半導体
素子の下に配線用導体を形成することがある。こ
の場合、第１図に示すように、回路基板１上の配
線用導体２にガラスコーテイング３を施して絶縁
性をもたし、このガラスコーテイング３を含むダ
イボンド部分に接着剤４を塗布し、この接着剤４
により半導体素子５をダイボンドしている。６は
ダイボンド部分の周囲に形成されたボンデイング
パツドで、このパツド６と半導体素子５の所定の
電極との間にリード線をワイヤボンデイングして
いる。このような従来の構造では、半導体素子５
の下部に配線用導体２を形成するにはその導体２
にガラスコーテイング３を施さなければならず、
工程数が増え、コストアツプの要因になつてい
た。(Prior art) Conventionally, when die-bonding a semiconductor element that requires insulation on the back side of the element to a circuit board, a wiring conductor is sometimes formed under the semiconductor element in order to simplify or shorten the wiring pattern. . In this case, as shown in FIG. 1, a glass coating 3 is applied to the wiring conductor 2 on the circuit board 1 to provide insulation, and an adhesive 4 is applied to the die bonding portion including the glass coating 3. This adhesive 4
The semiconductor element 5 is die-bonded. A bonding pad 6 is formed around the die bonding portion, and a lead wire is wire-bonded between this pad 6 and a predetermined electrode of the semiconductor element 5. In such a conventional structure, the semiconductor element 5
To form a wiring conductor 2 at the bottom of the
A glass coating 3 must be applied to the
The number of steps increased, which was a factor in increasing costs.

そこで、半導体素子５を回路基板１にダイボン
ドするにあたり、第１図に示すようなガラスコー
テイング３を施さず、絶縁性接着剤だけでおこな
うこともあつた。第２図はその例である。 Therefore, when die-bonding the semiconductor element 5 to the circuit board 1, sometimes the glass coating 3 as shown in FIG. 1 was not applied, but only an insulating adhesive was used. Figure 2 is an example.

第２図おいて、７は混成集積回路装置の回路基
板で、この回路基板７上には、ダイボンドされる
ICなどの半導体素子８の裏面に対応するダイボ
ンド部分の周囲に形成されたボンデイングパツド
９が形成され、さらにボンデイングパツドを兼ね
る配線用導体１０がダイボンド部分を横切るよう
に形成されている。この配線用導体１０を含むダ
イボンド部分にエポキシ樹脂などの絶縁性接着剤
１１が塗布され、絶縁性接着剤１１により半導体
素子８がダイボンド部分にダイボンドされてい
る。なお、絶縁性接着剤１１は配線用導体１０の
厚みより厚くする。そして、半導体素子８の各電
極と回路基板７上の各パツドとの間にリード線が
ワイヤボンドされている。 In FIG. 2, 7 is a circuit board of a hybrid integrated circuit device, and die bonding is carried out on this circuit board 7.
A bonding pad 9 is formed around a die-bonding part corresponding to the back surface of a semiconductor element 8 such as an IC, and a wiring conductor 10 which also serves as a bonding pad is formed to cross the die-bonding part. An insulating adhesive 11 such as epoxy resin is applied to the die-bonding portion including the wiring conductor 10, and the semiconductor element 8 is die-bonded to the die-bonding portion using the insulating adhesive 11. Note that the insulating adhesive 11 is made thicker than the wiring conductor 10. Lead wires are wire-bonded between each electrode of the semiconductor element 8 and each pad on the circuit board 7.

（考案が解決しようとする課題） しかしながら、第２図のような場合、絶縁性接
着剤１１によつて半導体素子８と配線用導体１０
との絶縁性を確保しているため、絶縁性接着剤１
１の厚みを配線用導体１０の厚みより厚くする必
要がある。そのため、絶縁性接着剤１１は、配線
用導体１０の厚みより厚くする量を塗布する必要
がある。こうした場合、配線用導体１０部分の絶
縁性接着剤１１は配線用導体１０の略厚み分だけ
盛り上がることになる。そのため、半導体素子８
を、回路基板７にダイボンドするために絶縁性接
着剤１１面上に載置したとき、この絶縁性接着剤
１１の盛り上がりにより半導体素子８が傾き、ワ
イヤボンデイング作業がしにくくなるという不都
合が生ずる。特に、配線用導体１０がダイボンド
部分の偏つた位置に形成された場合は、半導体素
子８の傾きが顕著である。そのため、この半導体
素子８が傾かないようにするために絶縁性接着剤
１１の塗布厚みを厳しく管理する必要があつた。(Problem to be solved by the invention) However, in the case shown in FIG. 2, the semiconductor element 8 and the wiring conductor 10 are
Insulating adhesive 1
1 needs to be thicker than the wiring conductor 10. Therefore, it is necessary to apply the insulating adhesive 11 in an amount that is thicker than the thickness of the wiring conductor 10. In such a case, the insulating adhesive 11 on the wiring conductor 10 portion will swell by approximately the thickness of the wiring conductor 10. Therefore, the semiconductor element 8
When placed on the surface of the insulating adhesive 11 for die bonding to the circuit board 7, the swelling of the insulating adhesive 11 causes the semiconductor element 8 to tilt, making wire bonding difficult. Particularly, when the wiring conductor 10 is formed at a lopsided position in the die-bonding portion, the inclination of the semiconductor element 8 is significant. Therefore, in order to prevent the semiconductor element 8 from tilting, it was necessary to strictly control the coating thickness of the insulating adhesive 11.

本考案は、上記問題点に鑑みてなされたもので
あつて、製造工程の簡略化をはかるとともに、絶
縁性接着剤の塗布厚みを厳しく管理しなくてもダ
イボンド時における半導体素子の傾きをなくすこ
とのできる混成集積回路装置を提供させることを
目的にしている。 The present invention was developed in view of the above problems, and aims to simplify the manufacturing process and eliminate the tilting of semiconductor elements during die bonding without strictly controlling the coating thickness of the insulating adhesive. The purpose of this invention is to provide a hybrid integrated circuit device that can perform the following steps.

（課題を解決するための手段） 本考案の混成集積回路装置は、上記目的を達成
するために、半導体素子がダイボンドされる回路
基板を備え、回路基板のダイボンド部分の周囲
に、複数のボンデイングパツドが形成され、回路
基板のダイボンド部分を横切る配線用導体が形成
され、配線用導体を含むダイボンド部分に絶縁性
接着剤によつて半導体素子がダイボンドされる混
成集積回路装置であつて、回路基板の配線用導体
以外のダイボンド部分に、複数のダミーパツドを
分散して設け、半導体素子を回路基板にダイボン
ドしたときに前記分散して設けたダミーパツドに
よりその半導体素子が傾かないようにしたことを
特徴とする。(Means for Solving the Problems) In order to achieve the above object, the hybrid integrated circuit device of the present invention includes a circuit board to which a semiconductor element is die-bonded, and a plurality of bonding pads are arranged around the die-bonding portion of the circuit board. A hybrid integrated circuit device in which a wiring conductor is formed to cross the die bonding portion of the circuit board, and a semiconductor element is die-bonded to the die bonding portion including the wiring conductor with an insulating adhesive, the circuit board A plurality of dummy pads are distributed in a die-bonding part other than the wiring conductor, and when the semiconductor element is die-bonded to the circuit board, the distributed dummy pads prevent the semiconductor element from tilting. do.

（作用） 上記のように、絶縁性接着剤によつて半導体素
子がダイボンドされるため、製造工程の簡略化を
はかることができる。また、回路基板の配線用導
体以外のダイボンド部分に複数のダミーパツドを
分散して設けたことにより、配線用導体の形成さ
れている部分の絶縁性接着剤が配線用導体の略厚
み分だけ盛り上がつたとしても、ダミーパツドの
部分の絶縁性接着剤もダミーパツドの略厚み分だ
け盛り上がるため、半導体素子を絶縁性接着剤面
上に載置したとき、半導体素子が傾かないように
なる。そのため、ワイヤボンデイングを確実に行
うことができる。(Function) As described above, since the semiconductor element is die-bonded using the insulating adhesive, the manufacturing process can be simplified. In addition, by distributing multiple dummy pads on the die-bonding parts of the circuit board other than the wiring conductors, the insulating adhesive in the area where the wiring conductors are formed rises by approximately the thickness of the wiring conductors. Even if the dummy pad wobbles, the insulating adhesive on the dummy pad also rises by approximately the thickness of the dummy pad, so that when the semiconductor element is placed on the insulating adhesive surface, the semiconductor element will not tilt. Therefore, wire bonding can be performed reliably.

（実施例） 以下、本考案の実施例を図面を参照しつつ詳述
する。(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

第３図において、７は混成集積回路装置の回路
基板で、この回路基板７上には、ダイボンドされ
るICなどの半導体素子８の裏面に対応するダイ
ボンド部分の周囲の所定箇所にたとえばAuから
なる複数のボンデイングパツド９が形成され、さ
らにボンデイングパツドを兼ねる配線用導体１０
がダイボンド部分を横切るように形成されてい
る。また、ダイボンド部分の四隅に分散して、複
数のダミーパツド１２が設けられている。この配
線用導体１０を含むダイボンド部分にエポキシ樹
脂などの絶縁性接着剤１１が塗布され、絶縁性接
着剤１１により半導体素子８がダイボンド部分に
ダイボンドされている。なお、絶縁性接着剤１１
は配線用導体１０の厚みより厚くする。本考案に
おいては、上記実施例のように複数のダミーパツ
ド１２を設けることにより、絶縁接着剤１１の塗
布厚みを厳しく管理しなくても、半導体素子８が
傾くことなく、ワイヤボンデイングが確実に行え
る。通常接着剤の塗布はデイスペンス，印刷，ス
タンピング等の手段を用いて行われる。 In FIG. 3, reference numeral 7 denotes a circuit board of a hybrid integrated circuit device. On this circuit board 7, for example, Au is placed at a predetermined location around the die-bonding part corresponding to the back surface of a semiconductor element 8 such as an IC to be die-bonded. A plurality of bonding pads 9 are formed, and a wiring conductor 10 that also serves as a bonding pad is formed.
is formed across the die-bonding part. Further, a plurality of dummy pads 12 are provided distributed at the four corners of the die bonding portion. An insulating adhesive 11 such as epoxy resin is applied to the die-bonding portion including the wiring conductor 10, and the semiconductor element 8 is die-bonded to the die-bonding portion using the insulating adhesive 11. In addition, the insulating adhesive 11
is made thicker than the thickness of the wiring conductor 10. In the present invention, by providing a plurality of dummy pads 12 as in the above embodiment, wire bonding can be performed reliably without tilting the semiconductor element 8 without strictly controlling the coating thickness of the insulating adhesive 11. Adhesive is usually applied by means such as dispensing, printing, stamping, etc.

なお、このダミーパツド１２は、実施例では四
隅に分散して設けられているが、半導体素子８が
傾かない位置に分散して複数設けられていれば特
定の位置に限定されるものではない。また、配線
用導体１０とダミーパツド１２とによつて半導体
素子８が傾かないようにしてもよいことは言うま
でもない。 Although the dummy pads 12 are provided in the four corners in the embodiment, they are not limited to specific positions as long as a plurality of dummy pads 12 are provided in locations where the semiconductor element 8 is not tilted. It goes without saying that the wiring conductor 10 and the dummy pad 12 may be used to prevent the semiconductor element 8 from tilting.

（考案の効果） 本考案の混成集積回路装置は、以上説明したよ
うに構成されているため、製造工程の簡略化をは
かることができるとともに、絶縁性接着剤の塗布
厚みを厳しく管理しなくても半導体素子が傾くこ
となくワイヤボンデイングを確実に行うことがで
きる。(Effects of the invention) Since the hybrid integrated circuit device of the invention is configured as explained above, the manufacturing process can be simplified, and the application thickness of the insulating adhesive does not have to be strictly controlled. Also, wire bonding can be performed reliably without tilting the semiconductor element.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図および第２図は従来の混成集積回路を示
し、第１図ａはその要部平面図、同図ｂはそのＡ
−Ａ線断面図、第２図ａは回路基板の要部平面
図、同図ｂは混成集積回路の要部平面図、同図ｃ
はそのＢ−Ｂ線断面図である。第３図は本考案に
よる混成集積回路の一実施例を示し、同図ａは回
路基板の要部平面図、同図ｂは混成集積回路の要
部平面図、同図ｃはそのＣ−Ｃ線断面図である。 ７……回路基板、８……半導体素子、９……ボ
ンデイングパツド、１０……配線用導体、１１…
…絶縁性接着剤、１２……ダミーパツド。 1 and 2 show a conventional hybrid integrated circuit, FIG. 1a is a plan view of the main part thereof, and FIG.
-A sectional view, Figure 2a is a plan view of the main part of the circuit board, Figure 2b is a plan view of the main part of the hybrid integrated circuit, Figure 2c
is a sectional view taken along the line B-B. FIG. 3 shows an embodiment of a hybrid integrated circuit according to the present invention; FIG. 3a is a plan view of the main part of the circuit board, FIG. FIG. 7... Circuit board, 8... Semiconductor element, 9... Bonding pad, 10... Wiring conductor, 11...
...Insulating adhesive, 12...Dummy pad.

Claims (1)

【実用新案登録請求の範囲】 半導体素子がダイボンドされる回路基板を備
え、回路基板のダイボンド部分の周囲に、複数の
ボンデイングパツドが形成され、回路基板のダイ
ボンド部分を横切る配線用導体が形成され、配線
用導体を含むダイボンド部分に絶縁性接着剤によ
つて半導体素子がダイボンドされる混成集積回路
装置であつて、 回路基板の配線用導体以外のダイボンド部分
に、複数のダミーパツドを分散して設け、半導体
素子を回路基板にダイボンドしたときに前記分散
して設けたダミーパツドによりその半導体素子が
傾かないようにしたことを特徴とする混成集積回
路装置。[Claims for Utility Model Registration] A circuit board to which a semiconductor element is die-bonded is provided, a plurality of bonding pads are formed around the die-bonding part of the circuit board, and a wiring conductor is formed across the die-bonding part of the circuit board. , a hybrid integrated circuit device in which a semiconductor element is die-bonded to a die-bonding part including a wiring conductor using an insulating adhesive, and a plurality of dummy pads are distributed and provided in the die-bonding part of the circuit board other than the wiring conductor. . A hybrid integrated circuit device, characterized in that when a semiconductor element is die-bonded to a circuit board, the semiconductor element is prevented from tilting by the distributed dummy pads.
JP1981138160U 1981-09-16 1981-09-16 Hybrid integrated circuit device Granted JPS5842940U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1981138160U JPS5842940U (en) 1981-09-16 1981-09-16 Hybrid integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1981138160U JPS5842940U (en) 1981-09-16 1981-09-16 Hybrid integrated circuit device

Publications (2)

Publication Number Publication Date
JPS5842940U JPS5842940U (en) 1983-03-23
JPH0246054Y2 true JPH0246054Y2 (en) 1990-12-05

Family

ID=29931394

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1981138160U Granted JPS5842940U (en) 1981-09-16 1981-09-16 Hybrid integrated circuit device

Country Status (1)

Country Link
JP (1) JPS5842940U (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58207655A (en) * 1982-05-28 1983-12-03 Hitachi Ltd Semiconductor device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5444773A (en) * 1977-09-16 1979-04-09 Nippon Cetu Kk Method of mounting electronic parts to printed board
JPS5797634A (en) * 1980-12-11 1982-06-17 Canon Inc Hybrid integrated circuit

Also Published As

Publication number Publication date
JPS5842940U (en) 1983-03-23

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