JP2804146B2 - Lead frame and semiconductor device - Google Patents
Lead frame and semiconductor deviceInfo
- Publication number
- JP2804146B2 JP2804146B2 JP2064113A JP6411390A JP2804146B2 JP 2804146 B2 JP2804146 B2 JP 2804146B2 JP 2064113 A JP2064113 A JP 2064113A JP 6411390 A JP6411390 A JP 6411390A JP 2804146 B2 JP2804146 B2 JP 2804146B2
- Authority
- JP
- Japan
- Prior art keywords
- groove
- mounting portion
- chip mounting
- semiconductor device
- length
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
- H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】 ［発明の目的］ （産業上の利用分野） 本発明は、リードフレームおよび半導体装置に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a lead frame and a semiconductor device.
（従来の技術） 以下、第３図、第４図を参照して従来技術によるリー
ドフレームおよび半導体装置について説明する。(Prior Art) Hereinafter, a lead frame and a semiconductor device according to the related art will be described with reference to FIGS. 3 and 4. FIG.
第３図に示すように、リードフレームはチップ載置部
１とリード13から成る。このチップ載置部１上の各素子
載置領域にトランジスタチップ２が接着剤６で、ICチッ
プ３が接着剤７で、導体配線５が載置された配線シート
４が接着剤８でそれぞれ接着されている。そして、リー
ド13とトランジスタ２、ICチップ３、導体配線５がそれ
ぞれ金ワイヤー９で結ばれている。そして、これら全体
がモールド10でおおわれている。つまり、この半導体装
置は、複数個の半導体素子を１個のチップ載置部１上に
接着し、この素子の電極とリードフレームの電極とを金
ワイヤー９で接続することによって、回路上多機能をも
たせたものである。As shown in FIG. 3, the lead frame includes a chip mounting portion 1 and leads 13. The transistor chip 2 is bonded to the element mounting area on the chip mounting portion 1 with the adhesive 6, the IC chip 3 is bonded with the adhesive 7, and the wiring sheet 4 on which the conductor wiring 5 is mounted is bonded with the adhesive 8. Have been. The lead 13 is connected to the transistor 2, the IC chip 3, and the conductor wiring 5 by gold wires 9. These are all covered with a mold 10. In other words, this semiconductor device has a multifunctional circuit by bonding a plurality of semiconductor elements on one chip mounting portion 1 and connecting the electrodes of the elements and the electrodes of the lead frame with gold wires 9. It is the one with.
しかしながら、従来の半導体装置では半導体素子チッ
プ載置部１に接着剤を介して接着した時に、同種接着剤
の場合には、チップ載置部１から素子上面まで接着剤が
はい上がり、素子上面のワイヤボンディングエリアを覆
ってしまい、ショートや配線不能が生じる。また、異種
接着剤を使用する場合は、前記の現象の他に、第４図に
示すように接着剤７、８が干渉しあい、素子の傾きや濡
れ不足を生じ、例えば、素子が傾いた場合は、素子の高
さが変化するためにワイヤボンディング不良となり、濡
れ不足の場合は素子と接着剤の接触部分が小さくなるた
めに熱抵抗が大きくなるという問題があった。However, in the conventional semiconductor device, when the same type of adhesive is used to bond the semiconductor device chip mounting portion 1 to the semiconductor device chip mounting portion 1 via an adhesive, the adhesive goes up from the chip mounting portion 1 to the upper surface of the device, and The wire bonding area is covered, and a short circuit or a wiring failure occurs. When a different kind of adhesive is used, in addition to the above-mentioned phenomenon, the adhesives 7 and 8 interfere with each other as shown in FIG. However, there is a problem that wire bonding failure occurs due to a change in the height of the element, and in the case of insufficient wetting, a contact portion between the element and the adhesive becomes small, so that thermal resistance increases.
（発明が解決しようとする課題） このように、半導体装置のチップ載置部上に接着剤で
複数個の半導体素子を接着する場合、接着剤のはねあが
り現象、接着剤の干渉現象によりショート、配線不能、
ワイヤボンディング不良、熱抵抗の増大などの問題があ
った。(Problems to be Solved by the Invention) As described above, when a plurality of semiconductor elements are bonded on a chip mounting portion of a semiconductor device with an adhesive, a short circuit occurs due to an adhesive splashing phenomenon and an adhesive interference phenomenon. , Unroutable,
There were problems such as poor wire bonding and an increase in thermal resistance.
本発明は、以上の点に鑑み、接着剤のはねあがり現
象、接着剤の干渉現象などを防止して、ショート、配線
不能、ワイヤボンディング不良、熱抵抗の増大などの問
題を解決するリードフレームおよび半導体装置を提供す
ることを目的とする。SUMMARY OF THE INVENTION In view of the above, the present invention has been made in view of the above, and has been made to solve the problems such as short-circuiting, inability to wire, poor wire bonding, and increased thermal resistance by preventing the adhesive splashing phenomenon, adhesive interference phenomenon, and the like. And a semiconductor device.
［発明の構成］ （課題を解決するための手段） 本発明によるリードフレームは、リードおよびチップ
載置部を備えたリードフレームにおいて、前記チップ載
置部上の隣接する各素子載置領域間に、溝または突起部
を設け、かつ前記溝または前記突起部の長さを前記素子
載置領域間の対向領域長以上に形成したことを特徴とす
る。あるいは、リードおよびチップ載置部を備えたリー
ドフレームにおいて、前記チップ載置部上の隣接する各
素子載置領域間に、溝と前記溝の上端部に突起部を設
け、かつ前記溝と前記突起部の長さを前記素子載置領域
間の対向領域長以上に形成したことを特徴とする。[Constitution of the Invention] (Means for Solving the Problems) A lead frame according to the present invention is a lead frame provided with a lead and a chip mounting portion, between the adjacent device mounting regions on the chip mounting portion. , A groove or a protrusion, and the length of the groove or the protrusion is formed to be equal to or greater than the length of the facing region between the element mounting regions. Alternatively, in a lead frame including a lead and a chip mounting portion, a protrusion is provided at an upper end of the groove between the adjacent device mounting regions on the chip mounting portion, and the groove and the The length of the protruding portion is formed to be longer than the length of the opposing region between the element mounting regions.
また、本発明による半導体装置は、チップ載置部と前
記チップ載置部上に接着剤を介して接着された複数の素
子とを備えた半導体装置において、前記チップ載置部上
の隣接する各素子載置領域間に、溝または突起部を設
け、かつ前記溝または前記突起部の長さを前記素子載置
領域間の対向領域長以上に形成したことを特徴とする。
あるいは、チップ載置部と前記チップ載置部上に接着剤
を介して接着された複数の素子とを備えた半導体装置に
おいて、前記チップ載置部上の隣接する各素子載置領域
間に、溝と前記溝の上端部に突起部を設け、かつ前記溝
と前記突起部の長さを前記素子載置領域間の対向領域長
以上に形成したことを特徴とする。Further, the semiconductor device according to the present invention is a semiconductor device comprising a chip mounting portion and a plurality of elements bonded on the chip mounting portion via an adhesive, wherein each of the adjacent devices on the chip mounting portion is provided. A groove or a projection is provided between the element mounting regions, and the length of the groove or the projection is formed to be equal to or greater than the length of the facing region between the element mounting regions.
Alternatively, in a semiconductor device including a chip mounting portion and a plurality of elements bonded on the chip mounting portion via an adhesive, between each of the adjacent device mounting regions on the chip mounting portion, A protrusion is provided at the groove and at the upper end of the groove, and the length of the groove and the protrusion is formed to be equal to or greater than the length of the facing region between the element mounting regions.
（作用） この半導体装置では、チップ載置部上の隣接する各素
子載置領域間に溝を設けるか、または突起部を設ける
か、または溝を設けかつ溝の上端に突起部を設け、かつ
溝または突起部の長さを素子載置領域間の対向領域長以
上にすることが、接着剤のはねあがり現象、干渉現象を
防止する。(Operation) In this semiconductor device, a groove is provided between adjacent element mounting regions on the chip mounting portion, or a protrusion is provided, or a groove is provided and a protrusion is provided at an upper end of the groove; By setting the length of the groove or the protrusion to be equal to or longer than the length of the facing region between the element mounting regions, the splashing-out phenomenon and the interference phenomenon of the adhesive are prevented.
（実施例） 以下、本発明の実施例を第１図、第２図を参照して説
明する。(Embodiment) Hereinafter, an embodiment of the present invention will be described with reference to FIGS.
第１図は実施例の要部断面図を示したものである。本
実施例の半導体装置のリードフレームはチップ載置部１
とリード13から成る。このチップ載置部１上に様々な素
子が接着剤を介して接着される。第１図では、ICチップ
３が接着剤７で、導体配線５の載置された配線シート４
が接着剤８でチップ載置部１上に接着されている。ここ
で、導体配線５とは例えばASICに用いられていて、配線
パターンを変更するために設けられている。そして、IC
チップ３と導体配線５が金ワイヤー９で結ばれている。
それに加え、チップ載置部１上の隣接する素子載置領域
間にＶ型の溝11およびその上端部に突起部12を設け、溝
11と突起部12の長さをICチップ３と導体配線５の対向領
域長以上に形成する。そして、これら全体がモールド10
で覆われている。FIG. 1 is a sectional view of a main part of the embodiment. The lead frame of the semiconductor device of this embodiment is
And lead 13. Various elements are bonded on the chip mounting portion 1 via an adhesive. In FIG. 1, an IC chip 3 is an adhesive 7 and a wiring sheet 4 on which conductor wiring 5 is placed.
Are adhered on the chip mounting portion 1 with an adhesive 8. Here, the conductor wiring 5 is used, for example, in an ASIC and is provided for changing a wiring pattern. And IC
The chip 3 and the conductor wiring 5 are connected by a gold wire 9.
In addition, a V-shaped groove 11 is provided between adjacent device mounting areas on the chip mounting portion 1 and a protrusion 12 is provided at an upper end thereof to form a groove.
The length of the protrusion 11 and the length of the protrusion 12 are set to be equal to or greater than the length of the facing region between the IC chip 3 and the conductor wiring 5. And these are all molded 10
Covered with.
第２図は、チップ載置部１の要部の上面図を示したも
のである。Ｖ型の溝11およびその上端部の突起部12は、
隣接する各素子載置領域間の対向領域長以上に形成され
ている。つまり各素子載置領域間のすべてを区切るよう
にＶ型の溝11およびその上端部の突起部12を必ずしも設
ける必要はない。FIG. 2 is a top view of a main part of the chip mounting unit 1. FIG. The V-shaped groove 11 and the projection 12 at the upper end thereof
The length is formed to be equal to or greater than the facing region length between adjacent element mounting regions. That is, it is not always necessary to provide the V-shaped groove 11 and the protruding portion 12 at the upper end thereof so as to divide all between the element mounting regions.
これにより、突起部12で接着剤の流れを止め、流れ出
した場合でも溝11でその流れが止まるため、従来問題で
あった接着剤のはね上がり現象、干渉現象を防止し、シ
ョート、配線不能、ワイヤボンディング不良、熱抵抗の
増大などの問題が解決できる。As a result, the flow of the adhesive is stopped at the protruding portion 12, and even when it starts flowing, the flow is stopped at the groove 11. Problems such as bonding failure and increase in thermal resistance can be solved.
なお、本実施例では、溝およびその上端部に突起部を
設けたが、溝または突起部のみでよい。In the present embodiment, the groove and the protrusion are provided at the upper end thereof, but only the groove or the protrusion may be provided.
［発明の効果］ 以上の結果から、本発明を用いることによって、チッ
プ載置部上の隣接する各素子載置領域間の接着剤のはね
上がり現象、干渉現象などを防止して、ショート、配線
不能、ワイヤボンディング不良、熱抵抗の増大などの問
題を解決することができる。[Effects of the Invention] From the above results, by using the present invention, it is possible to prevent the phenomenon of adhesive splashing and interference between adjacent element mounting areas on the chip mounting portion, and to prevent short-circuiting and wiring failure. Thus, problems such as poor wire bonding and an increase in thermal resistance can be solved.
第１図は本発明の実施例に係わる半導体装置の断面図、
第２図は本発明の実施例に係わる半導体装置の要部上面
図、第３図は従来技術による製品例の断面図、第４図は
従来技術による半導体装置の要部断面図である。 １……チップ載置部、３……ICチップ、４……配線シー
ト、５……導体配線、７……接着剤、８……接着剤、９
……金ワイヤー、11……溝、12……突起部、13……リー
ド。FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention,
FIG. 2 is a top view of a main part of a semiconductor device according to an embodiment of the present invention, FIG. 3 is a cross-sectional view of a product example according to the prior art, and FIG. 4 is a cross-sectional view of the main part of the semiconductor device according to the prior art. DESCRIPTION OF SYMBOLS 1 ... Chip mounting part, 3 ... IC chip, 4 ... Wiring sheet, 5 ... Conductor wiring, 7 ... Adhesive, 8 ... Adhesive, 9
…… Gold wire, 11 …… Groove, 12 …… Protrusion, 13 …… Lead.
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 23/12,23/50 H01L 25/04──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 6 , DB name) H01L 23 / 12,23 / 50 H01L 25/04
Claims (4)
フレームにおいて、前記チップ載置部上の隣接する各素
子載置領域間に、溝または突起部を設け、かつ前記溝ま
たは前記突起部の長さを前記素子載置領域間の対向領域
長以上に形成したことを特徴とするリードフレーム。In a lead frame provided with a lead and a chip mounting portion, a groove or a projection is provided between adjacent element mounting regions on the chip mounting portion, and the groove or the projection is formed. A lead frame having a length equal to or longer than a length of a facing region between the element mounting regions.
フレームにおいて、前記チップ載置部上の隣接する各素
子載置領域間に、溝と前記溝の上端部に突起部とを設
け、かつ前記溝と前記突起部の長さを前記素子載置領域
間の対向領域長以上に形成したことを特徴とするリード
フレーム。2. A lead frame provided with a lead and a chip mounting portion, wherein a groove and a projection at an upper end of the groove are provided between adjacent element mounting regions on the chip mounting portion, and A lead frame, wherein the length of the groove and the protrusion is formed to be equal to or greater than the length of a facing region between the element mounting regions.
剤を介して接着された複数の素子とを備えた半導体装置
において、前記チップ載置部上の隣接する各素子載置領
域間に、溝または突起部を設け、かつ前記溝または前記
突起部の長さを前記素子載置領域間の対向領域長以上に
形成したことを特徴とする半導体装置。3. A semiconductor device having a chip mounting portion and a plurality of elements bonded to the chip mounting portion via an adhesive, wherein each of adjacent element mounting areas on the chip mounting portion is provided. A semiconductor device, wherein a groove or a protrusion is provided therebetween, and the length of the groove or the protrusion is formed to be equal to or greater than the length of a facing region between the element mounting regions.
剤を介して接着された複数の素子とを備えた半導体装置
において、前記チップ載置部上の隣接する各素子載置領
域間に、溝と前記溝の上端部に突起部とを設け、かつ前
記溝と前記突起部の長さを前記素子載置領域間の対向領
域長以上に形成したことを特徴とする半導体装置。4. In a semiconductor device having a chip mounting portion and a plurality of elements bonded on said chip mounting portion via an adhesive, adjacent element mounting areas on said chip mounting portion. A semiconductor device, wherein a groove and a protrusion are provided at an upper end of the groove, and the length of the groove and the protrusion is formed to be equal to or greater than the length of a facing region between the element mounting regions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2064113A JP2804146B2 (en) | 1990-03-16 | 1990-03-16 | Lead frame and semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2064113A JP2804146B2 (en) | 1990-03-16 | 1990-03-16 | Lead frame and semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03266459A JPH03266459A (en) | 1991-11-27 |
| JP2804146B2 true JP2804146B2 (en) | 1998-09-24 |
Family
ID=13248694
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2064113A Expired - Lifetime JP2804146B2 (en) | 1990-03-16 | 1990-03-16 | Lead frame and semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2804146B2 (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0895287A3 (en) * | 1997-07-31 | 2006-04-05 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and lead frame for the same |
| JP2971449B2 (en) * | 1997-07-31 | 1999-11-08 | 松下電子工業株式会社 | Semiconductor device, manufacturing method thereof, and lead frame of semiconductor device |
| JP3362249B2 (en) * | 1997-11-07 | 2003-01-07 | ローム株式会社 | Semiconductor device and method of manufacturing the same |
| JP4502489B2 (en) * | 2000-09-27 | 2010-07-14 | ローム株式会社 | Multi-chip semiconductor device |
| JP4306772B2 (en) | 2006-10-05 | 2009-08-05 | 日亜化学工業株式会社 | Light emitting device |
| JP5453713B2 (en) * | 2007-07-06 | 2014-03-26 | 日亜化学工業株式会社 | Semiconductor device and method for forming the same |
| DE102014104819A1 (en) * | 2014-03-26 | 2015-10-01 | Heraeus Deutschland GmbH & Co. KG | Carrier and / or clip for semiconductor elements, semiconductor device and method of manufacture |
| EP3975244A1 (en) * | 2020-09-28 | 2022-03-30 | Infineon Technologies Austria AG | Semiconductor package and method of manufacturing a semiconductor package |
-
1990
- 1990-03-16 JP JP2064113A patent/JP2804146B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03266459A (en) | 1991-11-27 |
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