JPH0244157B2 - - Google Patents

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Publication number
JPH0244157B2
JPH0244157B2 JP58037653A JP3765383A JPH0244157B2 JP H0244157 B2 JPH0244157 B2 JP H0244157B2 JP 58037653 A JP58037653 A JP 58037653A JP 3765383 A JP3765383 A JP 3765383A JP H0244157 B2 JPH0244157 B2 JP H0244157B2
Authority
JP
Japan
Prior art keywords
conductor
plating layer
plating
conductive
conductive ring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58037653A
Other languages
Japanese (ja)
Other versions
JPS59163889A (en
Inventor
Eiichi Tsunashima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP3765383A priority Critical patent/JPS59163889A/en
Publication of JPS59163889A publication Critical patent/JPS59163889A/en
Publication of JPH0244157B2 publication Critical patent/JPH0244157B2/ja
Granted legal-status Critical Current

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  • Electroplating Methods And Accessories (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Description

【発明の詳細な説明】 産業上の利用分野 本発明は印刷基板上の導体への選択的めつき層
形成方法、とりわけ、印刷基板上で互いに分離さ
れて配設された導体群の一部に電解めつき法によ
つて部分的にめつき層を形成する基板上導体への
部分的めつき形成方法に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for selectively forming a plating layer on a conductor on a printed circuit board, and in particular, a method for forming a selective plating layer on a conductor on a printed circuit board. The present invention relates to a method for partially forming a plating layer on a conductor on a substrate by partially forming a plating layer by electrolytic plating.

従来例の構成とその問題点 印刷基板(プリント配線板、厚膜印刷回路板も
同義で呼ばれる)上に設けられた導体に、防錆、
電気接触性向上あるいははんだ付け向上の目的を
高度に達成するために、局部的なめつき層を形成
することは、従来から、しばしば用いられてい
る。このような導体への局部めつき層の形成に
は、電解過程によるめつき方法、すなわち、電気
めつき法が適している。この場合、印刷基板上に
配設された導体は互いに分離され、いわゆる非導
通状態にあるから、それらの各導体を電解系の陰
極電極体に共通接続する必要があり、また、各導
体と陰極電極体との接続には、十分な電気的接触
性とともに、耐液性、作業容易性が要求される。
Conventional structure and its problems The conductor provided on the printed circuit board (printed wiring board and thick film printed circuit board are also referred to interchangeably) has anti-rust,
In order to highly achieve the purpose of improving electrical contact or soldering, forming a localized plating layer has often been used in the past. A plating method using an electrolytic process, that is, an electroplating method is suitable for forming a local plating layer on such a conductor. In this case, the conductors arranged on the printed circuit board are separated from each other and are in a so-called non-conducting state, so it is necessary to commonly connect each conductor to the cathode electrode body of the electrolytic system. Connection with the electrode body requires sufficient electrical contact as well as liquid resistance and ease of work.

発明の目的 本発明は印刷基板上導体への部分的めつき層形
成にあたり、基体と陰極電極体との接続を容易に
して、作業性も良好なめつき層形成方法を提供す
るものである。
OBJECTS OF THE INVENTION The present invention provides a method for forming a plating layer that facilitates connection between a base and a cathode electrode body and has good workability when forming a partial plating layer on a conductor on a printed circuit board.

発明の構成 本発明は要約するに、基板上の環状域に導体の
一部を露出させ、前記露出導体に導電性環体を接
触させて、前記導体の一部に電解めつきを施す工
程をそなえた基板上導体への部分的めつき形成方
法であり、これによれば、基板上で分離された導
体群と良好な電気的接触が行なわれ、容易、確実
に電解めつき法で部分的めつき層形成が実現でき
る。
Composition of the Invention The present invention summarizes the steps of exposing a part of a conductor in an annular area on a substrate, bringing a conductive ring into contact with the exposed conductor, and electrolytically plating the part of the conductor. According to this method, good electrical contact is made with conductors separated on the substrate, and partial plating can be easily and reliably formed using electrolytic plating. It is possible to form a plating layer.

実施例の説明 第1図は本発明実施例に用いた印刷配線基板の
要部を示し、第1図Aは平面図、第1図Bはその
a−a′断面図である。この例では、絶縁基板1上
に導体群2を所定配線形状に設けたものである。
いま、導体群2の一端部が集中する部分、すなわ
ち各導体端2−a,2−b,2−c,2−dの部
分に選択的にめつき層を形成する方法について述
べる。
DESCRIPTION OF EMBODIMENTS FIG. 1 shows the main parts of a printed wiring board used in an embodiment of the present invention, FIG. 1A is a plan view, and FIG. 1B is a sectional view taken along line a-a'. In this example, a conductor group 2 is provided on an insulating substrate 1 in a predetermined wiring shape.
Now, a method of selectively forming a plating layer on a portion where one end of the conductor group 2 is concentrated, that is, the portion of each conductor end 2-a, 2-b, 2-c, and 2-d will be described.

第2図A,Bは、前記第1図A,Bに対応する
絶縁基板1の導体2に、その一部を露出させ、他
部をおおう樹脂層3が設けられ、かつ、前記一部
の露出導体群に対して、その環状域4の部分で導
電性リング5を接触させた状態を示す平面図、そ
のa−a′断面図である。導電性リング5は、基板
1の表面側を環状域4の範囲で露出させ、その露
出面に存する導体群2に圧接されて導電接触され
る。そして、これらを電解めつき浴内に配し、導
電性リング5を陰極として電解めつき過程を進行
させれば、導体群2の各表面には所定のめつき層
6が得られる。
2A and 2B show that the conductor 2 of the insulating substrate 1 corresponding to FIGS. 1A and 1B is provided with a resin layer 3 that exposes a part and covers the other part, and FIG. 2 is a plan view showing a state in which a conductive ring 5 is brought into contact with an annular region 4 of the exposed conductor group, and a cross-sectional view taken along the line a-a'. The conductive ring 5 exposes the front surface of the substrate 1 within the annular region 4 and is pressed into conductive contact with the conductor group 2 existing on the exposed surface. Then, by placing these in an electrolytic plating bath and proceeding with the electrolytic plating process using the conductive ring 5 as a cathode, a predetermined plating layer 6 is obtained on each surface of the conductor group 2.

第3図A,Bは、導電性リング5を、導体端2
−aのみ内環部に配し、他の導体端2−b,2−
c,2−dに対して外環部で接触させた状態の平
面図、そのa−a′断面図である。このようにすれ
ば、付着するめつき層の性質を環内外で違えるこ
とが可能で、通常、内環部の導体端2−aには厚
く、外環部の導体端2−b,2−c,2−dには
薄く、それぞれ異なつた粒質のめつき層が得られ
る。この事実は導電性リング5の内と外とで電流
密度が異なることに起因する。この方法は例え
ば、導体端2−aの部分を固体回路素子接着部と
し、導体端2−b,2−c,2−dを金属細線接
続部として用いる場合のように、めつき層の出来
上りを調整したいときに、一挙に仕上げられる利
点を有する。
3A and 3B show the conductive ring 5 and the conductor end 2.
-a only is arranged in the inner ring part, and the other conductor ends 2-b, 2-
FIG. 3 is a plan view of a state in which the outer ring portion is brought into contact with c and 2-d, and a cross-sectional view thereof taken along the line a-a'. In this way, it is possible to make the properties of the attached plating layer different on the outside and outside of the ring, and usually it is thicker on the conductor end 2-a of the inner ring part, and thicker on the conductor ends 2-b, 2-c of the outer ring part. , 2-d, a thin plated layer with different grain quality is obtained. This fact is due to the difference in current density between the inside and outside of the conductive ring 5. This method can be used, for example, when the conductor end 2-a is used as the solid-state circuit element bonding part and the conductor ends 2-b, 2-c, and 2-d are used as the thin metal wire connection parts. It has the advantage that when you want to make adjustments, you can finish them all at once.

第4図は、電解めつき過程で保持される導体群
2と導電性リング5との当接関係を概略的に表わ
した斜視図であり、導電性リング5は電解系の負
極(陰極)側に接続され、導体群2とは、その環
状域4内で電気的接触が行なわれている。
FIG. 4 is a perspective view schematically showing the contact relationship between the conductor group 2 and the conductive ring 5 that are held during the electrolytic plating process, and the conductive ring 5 is on the negative electrode (cathode) side of the electrolytic system. The conductor group 2 is electrically connected to the conductor group 2 within the annular region 4 thereof.

第5図は、絶縁基板1上に導電性リング5が多
数に取り付けられ、これが共通の陰極に接続され
たものを概略的に示す断面図であり、多数個の印
刷基板配線部の処理により、生産効率を高めるこ
とをねらつたものである。
FIG. 5 is a cross-sectional view schematically showing a large number of conductive rings 5 mounted on an insulating substrate 1 and connected to a common cathode. The aim is to increase production efficiency.

第6図は、導電性リング5を、導電性シリコン
ゴム7を介して板状支持体8で押えるようになし
ものの断面図であり、これによつて、導電性リン
グ5と導体群2との電気的接触は一段と改善さ
れ、めつき工程の安定化がはかれる。なお、この
場合、導電性ゴム7および板状支持体8にも、め
つき液が浸透できる孔9を設けておかなければな
らない。
FIG. 6 is a cross-sectional view of the conductive ring 5 held by the plate-like support 8 via the conductive silicone rubber 7, which allows the conductive ring 5 and the conductor group 2 to be connected to each other. Electrical contact is further improved and the plating process is stabilized. In this case, the conductive rubber 7 and the plate-shaped support 8 must also be provided with holes 9 through which the plating solution can penetrate.

本発明実施例で、絶縁基板1には樹脂層で絶縁
被覆されたアルミニウム板(厚さ1.0mm)が用い
られ、導体群2には、厚さ約70μの銅箔貼合せ層
からのエツチング加工配線体が用いられる。ま
た、めつき層6には、金、銀あるいはニツケル
が、厚さ1〜5μmに形成されて用いられる。さ
らに、絶縁樹脂層3には、たとえば、芳香族アミ
ン系硬化剤添加のエポキシ樹脂が適し、約15μm
の厚さに塗布、130℃〜150℃、30分程度の硬化処
理で、ピンホールもなく、かつ、適度の可撓性を
有し、アルカリ性めつき液に対してもすぐれた耐
性をもつており、永久使用の場合にも、十分に耐
久性をそなえている。導電性リング5は、銅また
はステンレス鋼製を用いて、これを直接に導体群
2と当接させてもよく、また、導電性シリコンゴ
ムのような弾性体を介在物として用いてもよい。
なお、導電性ゴムを用いる場合、陰極電極体を内
部に埋め込んで用いると、耐液性の面で有益であ
る。
In the embodiment of the present invention, an aluminum plate (1.0 mm thick) insulated with a resin layer is used as the insulating substrate 1, and the conductor group 2 is formed by etching a copper foil laminated layer with a thickness of approximately 70 μm. A wiring body is used. The plating layer 6 is made of gold, silver, or nickel and has a thickness of 1 to 5 μm. Furthermore, for the insulating resin layer 3, for example, an epoxy resin containing an aromatic amine curing agent is suitable, and the thickness is about 15 μm.
It is coated to a thickness of 300℃ and cured at 130℃ to 150℃ for about 30 minutes, resulting in no pinholes, moderate flexibility, and excellent resistance to alkaline plating solutions. It is sufficiently durable even for permanent use. The conductive ring 5 may be made of copper or stainless steel and brought into direct contact with the conductor group 2, or an elastic body such as conductive silicone rubber may be used as an intervening material.
Note that when using conductive rubber, it is advantageous in terms of liquid resistance to embed the cathode electrode body inside.

本発明の実施例は、単一固体の印刷基板に適用
されるのみならず、たとえば、フイルムキヤリア
方式の実装技術で使用されるフイルム面上の導体
群にめつき層を形成することにも、十分、適用可
能である。
Embodiments of the present invention are applicable not only to a single solid printed circuit board, but also to forming a plating layer on a group of conductors on a film surface used in, for example, film carrier mounting technology. Sufficiently applicable.

発明の効果 以上の実施例で詳しくのべたように、本発明に
よれば、印刷基板上の導体への部分的めつき層の
形成が作業性よく達成される。とくに、導体群に
対して、導電性リングで接触させるから、電解過
程における電流分布の安定化がはかられ、めつき
層の均一性、あるいは制御性が向上する。また、
導体群に対して、導電性リングを導体端が内環部
と外環部とにそれぞれ露出するように接触させて
電解めつき過程を進行させることにより、それぞ
れの導体端に付着するめつき層の性質を環内外で
違えることができ、そのめつき層を内環部で厚
く、外環部で薄く形成できる。
Effects of the Invention As described in detail in the above embodiments, according to the present invention, formation of a partial plating layer on a conductor on a printed circuit board can be achieved with good workability. In particular, since the conductor group is brought into contact with the conductive ring, the current distribution during the electrolytic process is stabilized, and the uniformity or controllability of the plating layer is improved. Also,
By bringing the conductive ring into contact with the conductor group so that the conductor ends are exposed to the inner ring part and the outer ring part, and proceeding with the electrolytic plating process, the plating layer attached to each conductor end can be formed. The properties can be made different between the inside and outside of the ring, and the plating layer can be formed thicker on the inner ring and thinner on the outer ring.

【図面の簡単な説明】[Brief explanation of drawings]

第1図Aは本発明実施例に用いた印刷基板の要
部平面図、同図Bはそのa−a′断面図、第2図A
はその電解めつき過程における状態を示す要部平
面図、同図Bはそのa−a′断面図、第3図Aは他
の実施例の状態を示す要部平面図、同図Bはその
a−a′断面図、第4図は本発明実施過程の状態を
示す概略斜視図、第5図、第6図は本発明各実施
例過程を示す断面図である。 1……基板、2……導体群、3……絶縁樹脂
層、4……環状域、5……導電性リング、6……
めつき層、7……導電性シリコンゴム、8……板
状支持体、9……孔。
FIG. 1A is a plan view of the main part of the printed circuit board used in the embodiment of the present invention, FIG.
3 is a plan view of the main part showing the state in the electrolytic plating process, FIG. FIG. 4 is a schematic perspective view showing the process of implementing the present invention, and FIGS. 5 and 6 are cross-sectional views showing the steps of each embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Substrate, 2... Conductor group, 3... Insulating resin layer, 4... Annular region, 5... Conductive ring, 6...
Plating layer, 7... Conductive silicone rubber, 8... Plate support, 9... Hole.

Claims (1)

【特許請求の範囲】[Claims] 1 基板上のほぼ全域に延長配設された導体を同
基板の所定内域面のみに一部分露出させるととも
に、同所定内域面の中で前記導体に接触する導電
性環体を配置して、前記導体の一部に電解めつき
を施す工程をそなえた基板上導体への部分的めつ
き形成方法。
1. A conductor extended over almost the entire area of the board is partially exposed only on a predetermined inner surface of the board, and a conductive ring is placed in contact with the conductor within the predetermined inner surface, A method for forming partial plating on a conductor on a substrate, comprising a step of electrolytically plating a part of the conductor.
JP3765383A 1983-03-08 1983-03-08 Method of partially plating conductor on substrate Granted JPS59163889A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3765383A JPS59163889A (en) 1983-03-08 1983-03-08 Method of partially plating conductor on substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3765383A JPS59163889A (en) 1983-03-08 1983-03-08 Method of partially plating conductor on substrate

Publications (2)

Publication Number Publication Date
JPS59163889A JPS59163889A (en) 1984-09-14
JPH0244157B2 true JPH0244157B2 (en) 1990-10-02

Family

ID=12503601

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3765383A Granted JPS59163889A (en) 1983-03-08 1983-03-08 Method of partially plating conductor on substrate

Country Status (1)

Country Link
JP (1) JPS59163889A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS639997A (en) * 1986-06-30 1988-01-16 イビデン株式会社 Surface mounting printed wiring board
JP6366509B2 (en) * 2012-12-27 2018-08-01 日本碍子株式会社 Electronic component and manufacturing method thereof

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55104496A (en) * 1979-01-29 1980-08-09 Matsushita Electric Ind Co Ltd Partial plating method

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5647980Y2 (en) * 1976-11-15 1981-11-10

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55104496A (en) * 1979-01-29 1980-08-09 Matsushita Electric Ind Co Ltd Partial plating method

Also Published As

Publication number Publication date
JPS59163889A (en) 1984-09-14

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