JPH0242466U - - Google Patents
Info
- Publication number
- JPH0242466U JPH0242466U JP12245688U JP12245688U JPH0242466U JP H0242466 U JPH0242466 U JP H0242466U JP 12245688 U JP12245688 U JP 12245688U JP 12245688 U JP12245688 U JP 12245688U JP H0242466 U JPH0242466 U JP H0242466U
- Authority
- JP
- Japan
- Prior art keywords
- transparent substrate
- cog
- cutting
- substrate
- board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 6
- 239000004020 conductor Substances 0.000 claims 1
- 230000002093 peripheral effect Effects 0.000 claims 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
Landscapes
- Structure Of Printed Boards (AREA)
Description
第１図は本考案の一実施例を説明する上面図、
第２図Ａ乃至第２図Ｃは本考案を用いたＣＯＧ基
板の分割を説明する断面図である。
１はガラス等より成るＣＯＧ基板、２は配線パ
ターン、３は切削用合わせマーク、４はダイヤモ
ンドカツターである。
FIG. 1 is a top view illustrating an embodiment of the present invention;
FIGS. 2A to 2C are cross-sectional views illustrating division of a COG substrate using the present invention. 1 is a COG substrate made of glass or the like, 2 is a wiring pattern, 3 is a cutting alignment mark, and 4 is a diamond cutter.
Claims (1)
の導電材料より成るパターンとを備え、前記透明
基板の周縁部に切削用合わせマークを設けたこと
を特徴とするＣＯＧ基板。 (2) 前記合わせマークは切削幅だけ離間した２
本の線で形成されることを特徴とする請求項１記
載のＣＯＧ基板。[Claims for Utility Model Registration] (1) The invention is characterized by comprising a transparent substrate and a pattern made of a plurality of conductive materials formed on the transparent substrate, and an alignment mark for cutting is provided on the peripheral edge of the transparent substrate. COG board. (2) The alignment marks are separated by the cutting width.
The COG substrate according to claim 1, characterized in that it is formed of regular lines.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12245688U JPH0242466U (en) | 1988-09-19 | 1988-09-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12245688U JPH0242466U (en) | 1988-09-19 | 1988-09-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0242466U true JPH0242466U (en) | 1990-03-23 |
Family
ID=31370407
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12245688U Pending JPH0242466U (en) | 1988-09-19 | 1988-09-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0242466U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08160406A (en) * | 1994-11-29 | 1996-06-21 | Korea Electron Telecommun | Preparation of plate display with large area using side facejunction |
| JP2015026719A (en) * | 2013-07-26 | 2015-02-05 | ルネサスエレクトロニクス株式会社 | Semiconductor device manufacturing method |
-
1988
- 1988-09-19 JP JP12245688U patent/JPH0242466U/ja active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08160406A (en) * | 1994-11-29 | 1996-06-21 | Korea Electron Telecommun | Preparation of plate display with large area using side facejunction |
| JP2015026719A (en) * | 2013-07-26 | 2015-02-05 | ルネサスエレクトロニクス株式会社 | Semiconductor device manufacturing method |
| US10032745B2 (en) | 2013-07-26 | 2018-07-24 | Renesas Electronics Corporation | Method of manufacturing semiconductor device |
| US10192851B2 (en) | 2013-07-26 | 2019-01-29 | Renesas Electronics Corporation | Method of manufacturing semiconductor device |