JPH0241430U - - Google Patents

Info

Publication number
JPH0241430U
JPH0241430U JP1988119029U JP11902988U JPH0241430U JP H0241430 U JPH0241430 U JP H0241430U JP 1988119029 U JP1988119029 U JP 1988119029U JP 11902988 U JP11902988 U JP 11902988U JP H0241430 U JPH0241430 U JP H0241430U
Authority
JP
Japan
Prior art keywords
power supply
substrate
wire
loop
lead frames
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1988119029U
Other languages
English (en)
Other versions
JPH069508Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1988119029U priority Critical patent/JPH069508Y2/ja
Publication of JPH0241430U publication Critical patent/JPH0241430U/ja
Application granted granted Critical
Publication of JPH069508Y2 publication Critical patent/JPH069508Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/49105Connecting at different heights
    • H01L2224/49109Connecting at different heights outside the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】
第1図は本考案の実施例に係るパツケージの平
面図。第2図はキヤツプで封止した状態の縦断面
図。第3図は従来のサークアツドパツケージの平
面図。第4図は多層セラミツクパツケージで各層
ごとに電源面を設けたものの例を示す縦断面図。
第5図は本考案の他の実施例に係るパツケージの
平面図。 1…ECL素子、2…リードフレーム、3…基
板、4…封止ガラス、5…アルミワイヤ、6…ル
ープ状電源メタライズ線、7…素子搭載部、8…
セラミツクキヤツプ、、9…メタライズ層、20
…セラミツク枠、VEE,VBB,VCC…電源
、E,B,C…各電源につながるリードフレーム

Claims (1)

    【実用新案登録請求の範囲】
  1. Nを3以上の整数、nを2以上の整数とし、N
    種類の電源を必要としひとつの電源について各辺
    ごとにn以上の電極を有する正方形の素子を収容
    するためのパツケージであつて、正方形状の、セ
    ラミツク或は金属板上に絶縁層を形成した基板3
    と、基板3の四辺外縁部に塗布された封止ガラス
    4と、基板3の中央の素子1を搭載すべき素子搭
    載部7の四周であつて、封止ガラス4の内端に取
    り付けられる正方形のセラミツク枠20と枠20
    の上に設けられるN本のループ状電源メタライズ
    線6と、封止ガラス4によつて内方端部が固定さ
    れた多数のリードフレーム2とよりなり、リード
    フレーム2のうち最外方にある適数本のリードフ
    レームが前記N本のループ状電源メラタイズ線6
    とワイヤ5で結線され、素子1の各辺上のn個の
    電源電極はその直近のループ状電源メタライズ線
    6とワイヤ5で結線されるようにした事を特徴と
    する多電源素子用パツケージ。
JP1988119029U 1988-09-09 1988-09-09 多電源素子用パツケージ Expired - Lifetime JPH069508Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1988119029U JPH069508Y2 (ja) 1988-09-09 1988-09-09 多電源素子用パツケージ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1988119029U JPH069508Y2 (ja) 1988-09-09 1988-09-09 多電源素子用パツケージ

Publications (2)

Publication Number Publication Date
JPH0241430U true JPH0241430U (ja) 1990-03-22
JPH069508Y2 JPH069508Y2 (ja) 1994-03-09

Family

ID=31363903

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988119029U Expired - Lifetime JPH069508Y2 (ja) 1988-09-09 1988-09-09 多電源素子用パツケージ

Country Status (1)

Country Link
JP (1) JPH069508Y2 (ja)

Also Published As

Publication number Publication date
JPH069508Y2 (ja) 1994-03-09

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