JPH0239868B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and in particular to a complementary insulated gate field effect transistor (hereinafter referred to as
(abbreviated as MOS).

BACKGROUND ART Conventionally, miniaturization and higher integration of MOS devices have led to larger memory capacities and higher functionality of microprocessors. Along with this, it is necessary to reduce the width and spacing of the diffusion layer, gate electrode layer, and metal wiring layer. If the length, width, and thickness of the wiring layer are reduced using the same wiring material according to the proportional reduction law (reduction rate is S, 0<S<1), the wiring resistance will be 1/S times as large as before reduction. Become. In addition, in order to integrate more sophisticated devices into a chip that is approximately the same size as the chip size before reduction, the length of the wiring layer remains the same as before reduction, only the width and thickness are reduced, and the inside of the chip is reduced. The delay in signal transmission between devices only increases as long as the same electrode and wiring materials, such as a layer of polycrystalline silicon containing impurities, are used. As a way to reduce this wiring resistance,
Wiring materials with lower specific resistance, such as high-melting point metals and metal silicides, have been introduced as wiring layer and gate electrode materials.

Until now, MOS devices have been announced that incorporate high-melting point metals and metal silicides as low-resistance wiring materials, but at present,
A doped polycrystalline silicon layer is in contact with the gate insulating film, and a gold layer such as MOSi ₂ is placed on top of the doped polycrystalline silicon layer, which has a small variation in V _T (threshold voltage) and no change in work function difference from a silicon gate device. Many use a two-layer structure with a silicide layer, that is, a polycide structure.

Here, we will begin with an explanation of a conventional method for manufacturing an N-channel transistor having a gate electrode with a polycide (polysilicon coated with metal silicide) structure, and then explain the manufacturing method.
We will discuss the disadvantages that arise when applied to CMOS devices.

First, FIGS. 1a to 1e show cross-sectional views of the manufacturing process of an N-channel transistor having a polycide gate.

A channel stopper is placed on the P-type substrate 1.
After forming the P ⁺ layer 2, a field oxide film 3 is formed by selective oxidation. After this, a gate oxide film 4 with a thickness of, for example, 300 to 500
Next, a polycrystalline silicon layer 5 containing N-type impurities is grown to a thickness of about 5000 Å over the entire surface. This polycrystalline silicon layer 5 may be made N-type by a method such as phosphorus diffusion after growth. Furthermore, the surface of the polycrystalline silicon layer 5 is covered with a thin oxide film 6 of about 500 Å, and a nitride film 7 is grown thereon to a thickness of, for example, 500 to 1000 Å by CVD.

Next, a photoresist 8 is formed in areas that are to become gate electrodes and wiring. This state cross-sectional diagram is the first
Shown in Figure a.

Next, using the photoresist 8 as a mask, the nitride film 7, oxide film 6, and polycrystalline silicon film 5 in areas where no resist exists are sequentially removed.

Then, the photoresist 8 used as a mask is removed, and then ions such as arsenic are implanted at a dose of, for example, 5×10 ¹⁵ to 1×10 ¹⁶ cm− ² , and
This is carried out at an energy of 150 KeV to form N ⁺ source/drain diffusion layers 9, 9'. A cross-sectional view at this time is shown in FIG. 1b.

Then, for example, 2000
Oxidation is performed to form oxide films 10, 10' of approximately Å thick. At this time, since the upper surface of polycrystalline silicon 5 is masked with nitride film 7, the oxide film does not become thick. On the sides of the polycrystalline silicon, there is an oxide film 11, 1 with approximately the same thickness as on the source and drain where arsenic is introduced to oxidize the polycrystalline silicon in which phosphorus has been diffused.
1' is formed. A cross-sectional view at this time is shown in FIG. 1c.

Next, the nitride film 7 and oxide film 6 remaining on the polycrystalline silicon 5 are removed by etching to expose the upper surface of the gate polycrystalline silicon layer 5. At this time, the oxide films 10 and 10' on the source and drain are partially etched to a thickness of about 1000 Å. Next, the metal for forming the metal silicide is a noble metal such as Pt, or Mo, Ti.
A high-melting point metal such as is deposited on the surface by sputtering or the like. At this time, only the upper surface of the polycrystalline silicon 5 of the gate is in contact with the silicon layer on the surface side of the substrate 1 and the metal. This state is shown in FIG. 1d.

Next, heat treatment (sintering) is performed to silicide the region where the metal 12 and the polycrystalline silicon 5 are in contact. For example, for platinum (Pt) and polycrystalline silicon, temperatures of 450°C to 500°C are used for sintering. In this way, metal silicide layer 13 is formed. Thereafter, an operation is performed to remove the metal 12 that has not been silicided. For example, if it is platinum, removal work is performed using aqua regia. Next, the wafer surface is heated at a low temperature of about 400℃.
Oxide film 14 with a thickness of 5000 to 10000 Å by CVD method
grow. Furthermore, contact 1 is placed in the desired area.
Holes are opened at 5 and 15' to form an aluminum wiring layer 16. After that, a film is formed to protect the chip.
The device is completed by passing through a step to expose only the pad area.

The method for manufacturing an N-channel transistor using a two-layer structure (polycide) of metal silicide and polycrystalline silicon as a gate electrode has been described above.

FIG. 2 is a cross-sectional view of the completed device after introducing this silicide forming process into a CMOS device. In this figure, a P-channel transistor is shown on the left, and an N-channel transistor is shown on the right. A P well 18 is provided on an N type substrate 17, and a P channel transistor and an N channel transistor are formed in each region. At this time, 19 is a channel stopper P ⁺ layer, 20 is a field oxide film, 21 and 21' are gate oxide films,
22, 22' are gate polycrystalline silicon, 23, 2
3' is a source/drain diffusion layer of a P-channel transistor, 24, 24' is a source/drain diffusion layer of an N-channel transistor, 25, 26 is a metal silicide layer, 27 is an interlayer insulating film 28, 28',
Reference numerals 29 and 29' indicate contact windows opened in the sources and drains of the P-channel and N-channel transistors, respectively, and 30 indicates an aluminum wiring layer.

Here, the manufacturing method for creating this structure is to make the gate polycrystalline silicon of the P-channel transistor the same N type as the gate polycrystalline silicon of the N-channel transistor, and before gate patterning, the entire polycrystalline silicon layer is coated with phosphorus. The method explained in Figure 1a and b can be applied not only to N-channel transistors but also to P-channel transistors.
This is applied to channel transistors.
Furthermore, by adding the P-well process necessary for CMOS and the process of selectively introducing P-type impurities into the P-channel and type impurities into the N-channel, the state shown in Figure 2 can be achieved using almost the same manufacturing method. Can be done.

However, when the process described above is applied to a CMOS in which the gate polycrystalline silicon of a P-channel transistor is P-type and the gate polycrystalline silicon of an N-channel transistor is N-type, an oxide film formed on the gate polycrystalline silicon Since it is necessary to introduce impurities into the polycrystalline silicon layer from above the nitride film at the same time as the introduction of impurities into the source and drain, the above two-layer film has the same blocking effect on ions as an oxide film with a thickness of approximately 2000 Å. capable,
The disadvantage was that it was difficult to introduce heavy mass ions such as _AS into polycrystalline silicon at a sufficiently high concentration. For this reason, it is desirable to first introduce impurities into the gate polycrystalline silicon layer. This method has the disadvantage that it requires a separate process for the gate polycrystalline silicon of the channel transistor, which lengthens the manufacturing process. Also,
When removing the oxide film under the nitride film, it is necessary to grow an oxide film of approximately 2000 Å on the source/drain diffusion layer so that the surface of the source/drain is not exposed. Both the surface and the silicon surface into which boron has been introduced undergo accelerated oxidation by high-dose implantation, but because the oxidation rates are different, there is a difference in etching between the N-channel side and the P-channel side during contact etching. Due to this oxidation, boron in the P ⁺ diffusion layer was eaten away, resulting in an increase in layer resistance.

The structure of the present invention provides an effective semiconductor device that eliminates the above-mentioned disadvantages.

The present invention is characterized in that the semiconductor substrate surface has a first conductivity type region and a second conductivity type region, and the first conductivity type region has a first field effect transistor of a second conductivity type channel and the second conductivity type region. forming a second field effect transistor of a first conductivity type channel in the region, a gate electrode of the first transistor being formed of a first polycrystalline silicon layer of a second conductivity type;
In a complementary insulated gate field effect transistor in which the gate electrode of the second transistor is formed of a second polycrystalline silicon layer of a first conductivity type, the first and second polycrystalline silicon layers including the gate electrode A metal silicide layer is deposited only on the top surface and both side surfaces of each of the two sides, and the first and second polycrystalline silicon layers are electrically connected by the metal silicide layer on the side surfaces. It is found in semiconductor devices.

FIG. 3 shows the structure of a CMOS device according to an embodiment of the present invention. The difference from FIG. 2 is that the gate polycrystalline silicon and the polycrystalline silicon layers 22, 2
Metal silicide layer 25' on the side surface instead of the top surface of 2',
25'', 26', and 26'' are adjacent to each other.
Such a structure not only has the advantage of reducing wiring resistance due to metal silicide, but also eliminates the need for a contact for electrically connecting P-type polycrystalline silicon and N-type polycrystalline silicon. For example, P
The channel gate polycrystalline silicon layer 22 and the N-channel gate polycrystalline silicon layer 22' are CMOS.
In an inverter, it is electrically connected as an input, but it was always necessary to provide a contact window between P ⁺ polycrystalline silicon and N ⁺ polycrystalline silicon via metal wiring, but with the structure of the present invention, There is always a metal silicide layer 25' on the side surface of the crystalline silicon layer.
Since 26' is formed, there is no need for a connection portion using metal wiring. As a result, the distance between the P ⁺ diffusion layer - N type substrate - P well - N ⁺ diffusion layer, which is the isolation region unique to CMOS, has been changed from the conventional P - N
This distance, which was determined by the polycrystalline silicon contact area, can be reduced to the limit of the electrical characteristics. Also, since there is no longer a need for a contact window at the connection between P ⁺ polycrystalline silicon and N ⁺ polycrystalline silicon, there is more flexibility in the layout of the boundary between P ⁺ and N ⁺ , and the contact at the boundary can be made more flexible. It eliminates the need to check whether it is present or not, and has many advantages from a design standpoint.

In addition, in the case of a P-type polycrystalline silicon gate P-channel transistor, like a P-channel transistor with an N-type polycrystalline silicon gate, P-type impurities are pumped back to the channel part due to the work function, and the surface There is no need to lower the concentration to make V _TP appropriate, and the N-type impurity concentration in the channel region can be set at a higher concentration than in the case of N ⁺ polycrystalline silicon, which is also advantageous for shortening the channel.

In addition, since metal silicide exists only on the side surfaces of polycrystalline silicon, the contact is opened in the polycrystalline silicon area, so the metal silicide is not exposed and processing can be performed in an oxidizing atmosphere. be.

In other words, it is easy to remove by etching the oxide film that oxidizes the polycrystalline silicon in the openings that is generated during the open-hole format in an oxidizing atmosphere, but the etching removal method for the oxide film that oxidizes the metal silicide is complicated. It is. Furthermore, if metal silicide is formed on the polycrystalline silicon layer, the ohmic contact property in connection with the upper layer wiring will be poor.
From this point of view as well, it is necessary to deposit metal silicide only on the side surfaces of the polycrystalline silicon layer.

Next, a manufacturing method for forming the structure of the present invention will be described.

4a to 4j are cross-sectional structures of a CMOS having a polycide gate according to the present invention.

Figure 4a: On the N-type substrate 32, P such as boron is added.
After providing a P-type well region 33 by introducing type impurities and pushing them, the surface of the substrate 32 is heated to
An oxide film 34 of about 1000 Å and a nitride film 35 of about 1000 to 1500 Å are grown in sequence. Thereafter, using a photoresist 36, the resist is left in desired regions such as transistors, and the nitride film in other regions is removed by plasma etching or the like. Next, in order to insert a channel stopper 38 only in the N channel region, the P channel side is masked with a resist 37. Channel stopper 38 is introduced by boron ion implantation or the like.

FIG. 4b: Next, the resists 36 and 37 are completely removed, and an oxide film 39 having a thickness of, for example, about 1 μm is formed in the field region. Then, all of the nitride film 35 and oxide film 34 left in the transistor region are removed. Then, a gate oxide film 40 is formed.
Next, ion implantation can be performed to optimize the V _T of the P channel transistor.

FIG. 4c: Next, the polycrystalline silicon layer 41 is
The layer is grown to a thickness of, for example, 5000 Å using the CVD method, and its surface is covered with a thin oxide film 42 having a thickness of, for example, 500 to 1000 Å. Next, the photoresist 43 is patterned to leave the polycrystalline silicon layer in desired areas.

FIG. 4d: The oxide film is selectively removed with buffered hydrofluoric acid, and then the polycrystalline silicon layer is removed, for example, by parallel plate anisotropic etching. Then, the resist 43 on the polycrystalline silicon layer/nitride film is removed. At this time, a gate oxide film 40 remains on the source/drain, and an oxide film 42 remains on the gate polycrystalline silicon.

Figure 4e: P channel transistor source/drain 44, 44' and polycrystalline silicon 41',
In order to introduce P-type impurities only into 41, the N channel side is covered with a film 45 such as a resist. Next, P-type impurity boron is ion-implanted at about 10 ¹⁵ cm ^-2 to 10 ¹⁶ cm ^-2 to form the source and drain diffusion layers 44 and 4.
4' and a P-type polycrystalline silicon layer are formed.

FIG. 4f: Next, remove the film 45 such as resist,
A mask film 46 for newly introducing N ⁺ impurities is formed in the P channel transistor region, and N ⁺ impurities, such as arsenic, are introduced by ion implantation of about 10 ¹⁶ cm ^-2 to form source/drain 47, 47' and N type impurities. Form a silicon layer. Source drain diffusion layer 4
7 and 47' so that even after the silicide layer is formed, the edge of the N ⁺ layer is under the polycrystalline silicon layer region, so that the portion with a different work function difference does not become a channel region.

FIG. 4g: Next, a metal 48 is grown on the entire surface by sputtering or the like to form metal silicide. Such metals include platinum, molybdenum, and tungsten. This metal 48 is the polycrystalline silicon layer 4
Only the sides of the silicon layer are in contact with 1', 41'', and 41.

Figure 4h: Next, metal 48 and polycrystalline silicon 4
A metal silicide layer 49 is formed by sintering only on the side surfaces 1', 41'', and 41 in contact with each other.

FIG. 4i: An interlayer insulating film 50 is grown on the entire surface by CVD. Contacts 51, 51', 52, 5 are then placed on desired diffusion layers and polycrystalline silicon layers.
Holes 2' and 53 are drilled. At this time, the silicide layer 49 in the opening is not exposed.

FIG. 4j: Next, the CMOS device is completed by forming the metal wiring layer 54. The manufacturing method according to the present invention has been described above.

In addition to what has been mentioned above, an advantage of forming the silicide layer of the present invention on the side surface is that the silicide layer is not exposed even if a contact hole is made in the polycrystalline silicon layer, so the silicide layer is less likely to be oxidized even in an oxidizing atmosphere. Also, when using two-layer polycrystalline silicon wiring, the polycrystalline silicon of the first wiring layer is exposed in the contact area, making it easier to make ohmic contact with the second polycrystalline silicon layer. There is also.

That is, if metal silicide is formed on the upper surface of the polycrystalline silicon layer and exposed in the opening, the metal silicide will be oxidized and it will be difficult to remove the resulting oxide. It is also conceivable that the metal silicide and the upper second polycrystalline silicon may undesirably form a Schottky barrier. Furthermore, it may progress to the inside of the metal silicide, which may undesirably increase the resistance of the contact portion. The disadvantage of metal silicide on such a polycrystalline silicon layer is that nitrogen (N ₂ )
A similar situation can be considered in the case of a natural oxide film due to oxygen contained therein.

Furthermore, although the present invention has been described with respect to a CMOS device in which a P-type well is formed on an N-type substrate, a similar structure can also be applied to a CMOS device in which an N-type well is formed on a P-type substrate or a CMOS device formed on an insulating film. Needless to say, it can be applied.

[Brief explanation of drawings]

Figure 1 is a cross-sectional view of a manufacturing method in which metal silicide is introduced into a conventional N-channel silicon gate device, and Figure 2 is a cross-sectional view of a CMOS device with metal silicide formed by applying the conventional method.
FIG. 3 is a plan view and a cross-sectional view of a CMOS device using metal silicide according to an embodiment of the present invention;
FIG. 4 is a cross-sectional view showing a manufacturing method for forming a structure according to an embodiment of the present invention. In the figure, 1...P-type substrate, 2, 19,
38... Channel stopper P ⁺ layer, 3, 20,
39...Field oxide film, 4, 21, 21',
40, 40'...gate oxide film, 5, 22, 41,
41', 41'', 41... Gate polycrystalline silicon layer, 6... Oxide film, 7, 35... Nitride film, 8, 3
6, 43, 45, 46...photoresist, 9,
9', 24, 24', 47, 47'...N ⁺ diffusion layer,
23, 23', 44, 44'...P type diffusion layer, 1
0,10',11,11'...Oxide film, 12,48
...Metal for silicide, 13, 25, 25', 2
6,26',49...metal silicide, 14,2
7, 50... interlayer insulating film, 15, 15', 28,
28', 29, 29', 51, 51', 52, 5
2', 53...Contact window, 16, 30, 54
...It is a metal wiring layer.

Claims (1)

[Claims] 1 having a first conductivity type region and a second conductivity type region on the surface of the semiconductor substrate, a first field effect transistor of a second conductivity type channel in the first conductivity type region and a first conductivity type channel in the second conductivity type region; forming a second field effect transistor of type channel, the gate electrode of the first transistor being formed by a first polycrystalline silicon layer of a second conductivity type, and the gate electrode of the second transistor being of a first conductivity type. In a complementary insulated gate field effect transistor formed by a second polycrystalline silicon layer of the same type, each of the first and second polycrystalline silicon layers including the gate electrode has a top surface and both side surfaces. 1. A semiconductor device, wherein a metal silicide layer is deposited only on the side surface, and the first and second polycrystalline silicon layers are electrically connected by the metal silicide layer on the side surface.