JPH0239439A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate a damaged layer of a diffused layer region and reduce a leakage current in the diffused layer by eliminating a process in which a silicon substrate in the diffused layer region is exposed to a plasma atmosphere by dry etching. CONSTITUTION:A field oxide film 2, a gate oxide film 3, a polycrystalline silicon layer 4a, an oxide film 5 and a silicon nitride film 6 are successively formed on a semiconductor substrate 1. Then the films are patterned to form a gate electrode 4. After the oxide film on a diffused layer is removed by oxide film wet etching, thermal oxide films 7 and 3 are formed on the side wall part of the gate electrode and the diffused layer region. Then ions are implanted with the gate electrode 4 as a mask to form a high impurity concentration diffused layer 9. Then the oxide film 7 on the sidewall part of the gate electrode 4 and the gate oxide film 3 on the diffused layer region are removed with oxide film wet etchant. After thermal oxide films 7a and 3 are formed on the side wall part of the gate electrode 4 and on the diffused layer region, the silicon nitride film 6 is removed and ions are implanted with the gate electrode 4 as a mask to form a low impurity concentration diffused layer 10. After an insulating film 11 is formed over the whole surface, electrode windows are drilled and metal wirings 13 are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing an insulated field effect transistor type semiconductor device.

[Conventional technology]

Conventionally, L D D (Lightly Doped D
A semiconductor device having a rain type MOS transistor has been manufactured as follows.

FIGS. 3(a) to 3(d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a conventional method of manufacturing an LDD type MOS transistor.

First, as shown in FIG. 3(a), a field oxide film M2 and a gate oxide film 3 are formed on a silicon substrate 2 using a conventional technique.
After forming the gate electrode 4 of polycrystalline silicon, impurity ions 31 of the opposite conductivity type to the silicon substrate 1 are implanted to form a lightly-concentrated diffusion layer 10.

Next, as shown in FIG. 3(b), an oxide film 5 is deposited over the entire surface by CVD.

Next, as shown in FIG. 3(c), anisotropic etching is performed to leave sidewall oxide films 5a on the sidewalls of gate electrode 4.

Then, using the field oxide film 2, the gate voltage rfi, 4, and the sidewall oxide film 5a as masks, impurities of a conductivity type opposite to that of the silicon substrate are ion-implanted at a high concentration to form a highly concentrated diffusion layer 9.
form.

Next, as shown in FIG. 3(d), an insulating film 11 is deposited by the CVD method, and a window is opened to form a metal electrode 13.

In the LDD type MOS transistor formed in this way, since the lightly-concentrated diffusion layer 10 is formed near the gate electrode 4, the electric field directly under the gate electrode is relaxed during transistor operation, and the deterioration of the transistor is improved. be done.

[Problem to be solved by the invention]

In the semiconductor device having the conventional LDD type MOS transistor described above, as shown in FIG. 3(C), the CVD oxide film 5 for forming the sidewall oxide film is etched back by anisotropic adhesive active ion etching. When etching the silicon substrate after completely removing the oxide film on the diffusion layer 10, a damaged layer is formed in the diffusion layer region, resulting in an increase in leakage current in the diffusion layer.

In addition, since the width of the sidewall oxide film 5a is determined by the amount of etchback, the width of the sidewall oxide film 5a changes due to variations in etchback, and the width of the diffusion layer with a low impurity concentration changes. The disadvantage is that the characteristics vary.

[Means to solve the problem]

The method for manufacturing a semiconductor device of the present invention includes the steps of forming a polycrystalline silicon layer doped with impurities after forming a field oxide film and a gate oxide film on a semiconductor substrate, and forming an oxide film and a nitride film on the polycrystalline silicon film. A step of sequentially forming a silicon film, a step of sequentially patterning the silicon nitride film, an oxide film, and a polycrystalline silicon film to form a gate electrode, and after removing the gate oxide film on the diffusion layer region by wet etching. The sidewalls of the gate electrode are formed by forming an oxide film on the sidewalls of the gate and the diffusion layer region by thermal oxidation, performing ion implantation to form a diffusion layer with a high impurity concentration, and wet etching the oxide film. a step of removing the oxide film on the portion and the diffusion layer region, a step of forming an oxide film on the sidewall portion of the gate electrode and the diffusion layer region by thermal oxidation and then removing the silicon nitride film, and performing ion implantation. The method includes a step of forming a diffusion layer with a low impurity concentration, a step of forming an insulating film on the entire surface, and a step of forming a metal electrode by forming a window for forming an electrode in the insulating film.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1(a) to 1(i) are cross-sectional views of semiconductor chips arranged in the order of steps for explaining a first embodiment of the present invention.

First, as shown in FIG. 1(a), after forming a field oxide film 2 on a semiconductor substrate 1, a gate acid (arsenic) film 3 is formed, and phosphorus-doped polycrystalline silicon q 4 a is formed on the gate acid film 3.
, an oxide film 5, and a silicon nitride film 6 are formed in this order.

Next, as shown in FIG. 1(b), patterning is performed using photolithography to form the gate electrode 4.

Next, as shown in FIG. 1(c), after removing the oxide film in the diffusion layer region by oxide film wet etching, an oxide film is formed on the goo 1 to electrode sidewall portion and the diffusion layer region by thermal oxidation. . In this thermal oxidation, the oxide film 7 formed on the sidewalls of the gate electrode is formed on the phosphorus-doped polycrystalline silicon, so it is considerably thicker than the oxide film formed on the single crystal silicon in the diffusion region. It gets thicker.

Next, as shown in FIG. 1(d), impurity ions are implanted in a high concentration using the gate electrode 4 as a mask to form a highly concentrated diffusion layer.

Next, as shown in FIG. 1(e), the sidewall oxide film 7 of the gate electrode 4 and the gate oxide film 3 on the diffusion region are removed using an oxide film wet etchant.

Next, as shown in FIG. 1(f), oxide films 7a and 3 are formed on the side wall portions of the gate electrode 4 and the diffusion layer region by thermal oxidation, and then the silicon nitride film 6 is removed.

Next, as shown in FIG. 1(g), using the gate electrode 4 as a mask, a thin layer of impurity is implanted into a low concentration diffusion layer 1.
form 0.

Next, as shown in FIG. 1(h), an insulating film 11 is formed on the entire surface.

Next, as shown in FIG. 1(i), an electrode window is opened in the insulating film 10, and a metal electrode 13 is formed.

When the above manufacturing method is used, the silicon substrate in the diffusion layer region is not exposed to a plasma atmosphere by dry etching, so no damaged layer is formed in the diffusion layer region. In addition, since the width of the diffusion layer 9 with a low impurity concentration is determined by the oxide film 7 on the side wall of the gate electrode formed by thermal oxidation, by controlling the thickness of the thermal oxide film formed on the phosphorus-doped polycrystalline silicon, , variations can be suppressed to a large extent, resulting in stable transistor characteristics.

FIGS. 2(a) to 2(i) are cross-sectional views of semiconductor chips arranged in the order of steps for explaining a second embodiment of the present invention.

The second embodiment is an example in which the present invention is applied to a CMO3 device.

First, as shown in FIG. 2(a), a P-type silicon substrate 1
After forming a diffusion layer for forming the N-well 2, the steps shown in FIGS. 3. Form a gate electrode 4, an oxide film 5, and a silicon nitride film 6.

Next, as shown in FIG. 2(b), an oxide film 7 is formed on the side wall of the gate electrode by thermal oxidation.

Next, as shown in FIG. 2(c), the upper part of the N well side is covered with a photoresist 16, and N type ions are implanted to form an N+ diffusion layer 15.

Next, as shown in FIG. 2(d), the N-well side is covered with a photoresist 18 so as to be exposed, and P-type ions are implanted to form a P-expansion tikJm17.

Next, as shown in FIG. 2(e), the oxide film 7 on the side walls of the gate electrode 4 is removed by etching.

Next, as shown in FIG. 2(f>), after thermal oxidation is performed to form an oxide film 7a again on the side walls of the gate electrode 4, the silicon nitride M6 is removed.

Next, as shown in FIG. 2(g), the N-well side is again covered with photoresist 20, and N-type ions are thoroughly implanted.
Expand fin! form 19.

Next, as shown in FIG. 2(h), the N-well side is covered with a photoresist 22 so as to be exposed, and P-type ions are implanted to form a P- diffusion layer 21.

Next, as shown in FIG. 2 (i>), the entire surface is covered with an insulating film 11, a window is opened by photolithography, and a metal electrode 13 is attached.

〔Effect of the invention〕

As explained above, in the present invention, since the silicon substrate in the diffusion layer region is not exposed to a plasma atmosphere by dry etching, a damaged layer is not formed in the diffusion layer region, and leakage current in the diffusion layer is reduced. It is possible,
This has the effect of leading to improved performance of semiconductor devices.

Further, since variations in the quality of the diffusion layer with a low impurity concentration can be suppressed, the characteristics of the transistor are stabilized, leading to an improvement in the yield and reliability of the semiconductor device.

[Brief explanation of the drawing]

FIGS. 1(a) to (i) are cross-sectional views of semiconductor chips arranged in the order of manufacturing steps to explain the first embodiment of the present invention, and FIGS. Cross-sectional views of semiconductor chips arranged in the order of manufacturing steps for explaining the second embodiment, and FIGS. 1 is a cross-sectional view of a semiconductor chip. 1...Silicon substrate, 1'...P-type silicon substrate,
2...Field oxide film, 3...Gate oxide film, 4
...gate electrode, 4a...polycrystalline silicon, 5...
・Oxide film, 6...Silicon nitride film, 7, 7a...
Oxide film, 8... Oxide film, 9... Dense diffusion layer, lO.
...Thin diffusion layer, 11...Insulating film, 13...Metal electrode, 14...N well, 15...N+ diffusion layer, 16
...Photoresist, 17...P+ diffusion layer, 18...
Photoresist, 1... N-diffusion layer, 20... Photoresist, 21... P-enlargement layer, 22... Photoresist.

Claims (1)

[Claims] a step of forming a polycrystalline silicon layer doped with impurities after forming a field oxide film and a gate oxide film on a semiconductor substrate; a step of sequentially forming an oxide film and a silicon nitride film on the polycrystalline silicon film; A process of sequentially patterning a silicon nitride film, an oxide film, and a polycrystalline silicon film to form a gate electrode, and removing the gate oxide film on the diffusion layer region by wet etching, and then removing the gate sidewall portion and the diffusion layer by thermal oxidation. A step of forming an oxide film on the layer region, a step of performing ion implantation to form a diffusion layer with a high impurity concentration, and a step of wet-etching the oxide film remove the oxidation on the sidewall portion of the gate electrode and the diffusion layer region. a step of removing the film; a step of forming an oxide film on the side wall portion of the gate electrode and the diffusion layer region by thermal oxidation and then removing the silicon nitride film; and a step of performing ion implantation to form the diffusion layer with a thin impurity concentration. 1. A method for manufacturing a semiconductor device, comprising the steps of: forming an insulating film over the entire surface; and forming a metal electrode by forming a window for forming an electrode in the insulating film.