JP2001185722A - Method of manufacturing semiconductor integrated circuit apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To secure the reliability of a MISFET in which a gate insulating film is composed of an insulating film other than silicon oxide. SOLUTION: Only the gate insulating film 4 under a narrowed gate electrode 10 (polycrystalline silicon film 5) is made to function as the insulating film by narrowing the gate electrode 10 (polycrystalline silicon film 5), after thinly removing the side wall of the polycrystalline silicon film 5 that comprises part of the gate electrode 10, without making the gate insulating film 4 at the side- wall edge of the gate electrode 10 that is damaged by etching when the gate is manufactured function as an insulating film.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for manufacturing a semiconductor integrated circuit device, and more particularly, to a MISFET (Metal Inslat) in which a gate insulating film is formed of an insulating film other than silicon oxide.
The present invention relates to a technology which is effective when applied to the manufacture of a semiconductor integrated circuit device having a semiconductor field effect transistor (or semiconductor field effect transistor).

[0002]

2. Description of the Related Art An outline of a conventional gate processing process is as follows. First, a semiconductor substrate (hereinafter, simply referred to as a substrate) is thermally oxidized to form a gate oxide film on its surface.
Next, after depositing a gate electrode material on the gate oxide film, the gate electrode is formed by patterning the gate electrode material by dry etching using a photoresist film as a mask.

[0003] Thereafter, the photoresist film is removed by ashing (ashing), and dry etching residues and ashing residues remaining on the substrate surface are removed by wet etching using an etching solution such as hydrofluoric acid.

However, when the above-described etching is performed, the gate oxide film in a region not covered with the gate electrode is shaved, and the gate oxide film on the side wall edge of the gate electrode is also isotropically etched to form an undercut. Occurs. As a result, problems such as a decrease in the withstand voltage of the gate electrode may occur, and the substrate is thermally oxidized again to form an oxide film on the surface in order to improve the profile of the undercut side wall of the gate electrode. (Hereinafter referred to as a light oxidation process).

[0005] For example, Japanese Patent Application Laid-Open No. 7-94716 discloses that after forming a gate electrode on a substrate via a gate oxide film,
A technique for performing light oxidation in an atmosphere in which a reducing gas (hydrogen) and an oxidizing gas (steam) is diluted with nitrogen is disclosed.

[0006]

In order to realize a high-speed and high-performance MISFET, it is necessary to reduce the thickness of the gate oxide film in proportion to the miniaturization of the MISFET. In the following MISFET, 5
A gate oxide film having a thickness smaller than nm is required.

[0007] However, when the thickness of the gate oxide film is thinner than 5 nm, a reduction in the withstand voltage due to the generation of direct tunnel current or hot carriers due to stress becomes apparent. As a countermeasure for avoiding the decrease in the dielectric strength, there is an option to increase the effective thickness of the gate insulating film by using silicon nitride, tantalum oxide, or the like having a higher dielectric constant than silicon oxide.

However, when the gate insulating film is formed of a material other than silicon oxide, the profile of the edge of the side wall of the gate electrode cannot be improved by the above-described light oxidation process. Further, even if a material other than silicon oxide is oxidized by any method, such an oxide film cannot reduce the leak current of the gate insulating film or ensure the reliability.

An object of the present invention is to provide a technique capable of securing the reliability of a MISFET in which a gate insulating film is formed of an insulating film other than silicon oxide.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0011]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) A method of manufacturing a semiconductor integrated circuit device according to the present invention includes the following steps: (a) After forming a gate insulating film made of a first insulating film on a main surface of a semiconductor substrate, Forming a first conductive film on the gate insulating film, (b) forming a gate electrode by patterning the first conductive film by dry etching using a photoresist film as a mask, and (c) forming a gate electrode. A step of thinning the gate electrode by removing the first conductive film on a side wall of the gate electrode.

(2) A method of manufacturing a semiconductor integrated circuit device according to the present invention includes the following steps: (a) After forming a gate insulating film made of a first insulating film on a main surface of a semiconductor substrate, Forming a first conductive film on the gate insulating film, (b) forming a gate electrode by patterning the first conductive film by dry etching using a photoresist film as a mask, and (c) forming a gate electrode. Removing the gate insulating film at the end of the side wall of the gate electrode; (d) forming a second insulating film on the main surface of the semiconductor substrate, thereby removing the gate insulating film in the step (c). Recovering the thickness of the film.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle except when necessary.

(Embodiment 1) MIS according to the present embodiment
The method of manufacturing the FET will be described in the order of steps with reference to FIGS.

First, as shown in FIG. 1, an element isolation groove 2 is formed in an element isolation region of a substrate 1 made of, for example, p-type single crystal silicon having a specific resistance of about 10 Ωcm. After ion implantation of (boron) to form the p-type well 3, a gate insulating film 4 made of a silicon nitride film (first insulating film) having a thickness of about 4 nm is deposited on the substrate 1.
This silicon nitride film may be deposited by a CVD method. For example, JV in which monosilane and nitrogen are discharged in plasma.
By depositing by the method D (see IEEE ED45, p680), a gate insulating film 4 with less leakage current can be obtained.

Next, as shown in FIG.
A polycrystalline silicon film (first conductive film) 5 having a thickness of about 90 to 100 nm is deposited on the upper portion of the polycrystalline silicon film 5 by a CVD method, and a WN (tungsten nitride) film having a thickness of about 5 nm is formed on the polycrystalline silicon film 5 by a sputtering method. Film 6 and W having a thickness of about 50 nm
(Tungsten) film 7 and a silicon nitride film 13 having a thickness of about 200 nm on the W film 7 by CVD.
Is deposited. The polycrystalline silicon film 5 is doped with about 2 × 10 ²⁰ cm ⁻³ of phosphorus to suppress depletion of the gate electrode.

Next, as shown in FIG. 3, the silicon nitride film 8 is patterned by dry etching using the photoresist film 9 as a mask, and after the photoresist film 9 is removed, as shown in FIG. By patterning the W film 7, the WN film 6, and the polycrystalline silicon film 5 by dry etching using the silicon nitride film 8 as a mask, a gate electrode 10 having a gate length of about 0.13 μm is formed.
Thereafter, the substrate 1 is wet-etched to remove dry etching residues and the like remaining on the surface of the substrate 1 (gate insulating film 4).

When the above-mentioned etching (dry etching and wet etching) is performed, the gate insulating film 4 in a region other than the lower portion of the gate electrode 10 is also shaved to some extent, and becomes a thin gate insulating film 4a. In addition, the gate electrode 10
Since the gate insulating film 4 at the end of the side wall is damaged by etching, problems such as a decrease in the breakdown voltage of the gate electrode 10 and an increase in the leak current of the gate insulating film 4 occur.

Therefore, in the present embodiment, as shown in FIG. 5, the side wall of the polycrystalline silicon film 5 forming a part of the gate electrode 10 is thinly removed to thereby form the gate electrode 10.
(Polycrystalline silicon film 5) is thinned. As a result, the damaged gate insulating film 4 (the location indicated by the arrow) outside the side wall end of the thinned polycrystalline silicon film 5 does not substantially function as the gate insulating film, but is thinned. Only the undamaged gate insulating film 4 under the polycrystalline silicon film 5 substantially functions as a gate insulating film.

In order to remove the side wall of the polycrystalline silicon film 5 thinly, the surface of the substrate 1 may be wet-etched using an etching solution composed of, for example, a mixed solution of nitric acid (HNO ₃ ) and hydrofluoric acid (HF). . The damage of the gate insulating film 4 due to the etching during the gate processing described above is caused by the gate electrode 1
0, the removal amount of the side wall of the polycrystalline silicon film 5 may be of the order of several nm.
With this amount of removal, MI due to dimensional variation in gate length
There is no deterioration of the characteristics of the SFET.

Here, only the side wall of the polycrystalline silicon film 5 forming a part of the gate electrode 10 is thinly removed, but the WN film 6 and the WN film forming the other part of the gate electrode 10 are removed.
There is no problem even if the side wall of the film 7 is thinly removed together with the polycrystalline silicon film 5.

Next, as shown in FIG. 6, about 1 × 10 ¹⁴ cm ⁻² of n-type impurities (for example, arsenic) are ion-implanted into the substrate 1 (p-type well 3) to thereby form a gate electrode 10 on both sides. The n ⁻ -type semiconductor region 11 having a low impurity concentration is formed in the p-type well 3. As described above, the polycrystalline silicon film 5
Since the amount of side wall shaving is small, no offset occurs between n ⁻ type semiconductor region 11 and gate electrode 10.

Next, as shown in FIG.
The silicon nitride film deposited by the method D is anisotropically dry-etched to form a sidewall spacer 12 having a thickness of about 80 nm on the side wall of the gate electrode 10. Then, the substrate 1
(P-type well 3) is ion-implanted with an n-type impurity (for example, arsenic) of about 2 × 10 ¹⁵ cm ⁻² , and a high impurity concentration n ⁺ -type semiconductor region 13 is formed in the p-type well 3 on both sides of the gate electrode 10.
By forming the (source, drain), an n-channel type MISFET Qn is completed.

(Embodiment 2) MIS according to the present embodiment
The method of manufacturing the FET will be described in the order of steps with reference to FIGS.

First, as shown in FIG. 8, a gate insulating film 4 made of a silicon nitride film is deposited on a substrate 1 in the same manner as in the first embodiment, and then a polycrystalline film deposited on the gate insulating film 4 is formed. The gate electrode 10 is formed by patterning the silicon film 5, the WN film 6, the W film 7, and the silicon nitride film 13. Thereafter, the substrate 1 is wet-etched to remove dry etching residues and the like remaining on the surface of the substrate 1 (gate insulating film 4). The steps so far are the same as those in the first embodiment.

When the above etching is performed, the gate electrode 1
The gate insulating film 4 in a region other than the region below the zero is also cut to some extent, and becomes a thin gate insulating film 4a. In addition, since etching damage occurs in the gate insulating film 4 at the side wall end portion of the gate electrode 10, problems such as a decrease in breakdown voltage of the gate electrode 10 and an increase in leak current of the gate insulating film 4 are caused. Occurs.

Therefore, in the present embodiment, as shown in FIG. 9, the damaged gate insulating film 4 at the side wall end of the gate electrode 10 is removed using an etching solution such as hot phosphoric acid. Since the damage to the gate insulating film 4 occurs within a range of about several nm from the end of the side wall of the gate electrode 10, the removal amount of the gate insulating film 4 may be about several nm. As a result, only the undamaged gate insulating film 4 remains under the gate electrode 10.

Next, as shown in FIG. 10, a silicon nitride film 15 having a thickness of about several nm is deposited on the substrate 1. As a result, a silicon nitride film 15 having a thickness substantially equivalent to the thickness of the gate insulating film 4 removed by the above-mentioned etching is deposited also on the side wall edge of the gate electrode 10. The thickness recovers to the thickness before etching. This silicon nitride film 15 may be deposited by a CVD method,
The film is deposited by the above-described JVD method which can obtain a film having a smaller leak current.

Thereafter, as shown in FIG. 11, after a sidewall spacer 12 is formed on the side wall of the gate electrode 10 in the same manner as in the first embodiment, about 2 × 10 5 ¹⁵ cm ^-2 n-type impurity (for example, arsenic)
Is implanted into the p-type wells 3 on both sides of the gate electrode 10.
Forming an n ⁺ -type semiconductor region 13 (source and drain) with a high impurity concentration in
ETQn is completed.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment, and various modifications may be made without departing from the gist of the invention. It goes without saying that it is possible.

In the above embodiment, the n-channel MIS
The case where the present invention is applied to the manufacture of an FET has been described.
Needless to say, it can be applied to the production of a channel type MISFET.
It is. In the above embodiment, the gate insulating film is
Although the case of silicon nitride was explained,
If tantalum oxide (Ta_TwoO_Five) Film and titanium oxide (Ti
O _Two) Higher dielectric constant than silicon oxide, such as film
The present invention can also be applied to a case where an insulating material is used.

[0033]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

According to the present invention, even when the gate insulating film of the MISFET is formed of an insulating material other than silicon oxide, the defect of the gate insulating film generated at the end of the side wall of the gate electrode during the gate processing can be reliably repaired. , It is easy to apply an insulating material having a higher dielectric constant than silicon oxide to the gate insulating film.
Higher speed and higher performance of the SFET can be promoted.

[Brief description of the drawings]

FIG. 1 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method for manufacturing a MISFET according to a first embodiment of the present invention.

FIG. 2 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the MISFET according to the first embodiment of the present invention.

FIG. 3 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the MISFET according to the first embodiment of the present invention.

FIG. 4 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the MISFET according to the first embodiment of the present invention.

FIG. 5 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the MISFET according to the first embodiment of the present invention.

FIG. 6 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the MISFET according to the first embodiment of the present invention.

FIG. 7 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the MISFET according to the first embodiment of the present invention.

FIG. 8 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the MISFET according to the second embodiment of the present invention.

FIG. 9 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the MISFET according to the second embodiment of the present invention.

FIG. 10 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the MISFET according to the second embodiment of the present invention.

FIG. 11 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the MISFET according to the second embodiment of the present invention;

[Explanation of symbols]

REFERENCE SIGNS LIST 1 semiconductor substrate 2 element isolation groove 3 p-type well 4 gate insulating film 4 a gate insulating film 5 polycrystalline silicon film 6 WN film 7 W film 8 silicon nitride film 9 photoresist film 10 gate electrode 11 n ^- type semiconductor region 12 sidewall Spacer 13 n ⁺ type semiconductor region (source, drain) Qn n channel type MISFET

 ──────────────────────────────────────────────────続 き Continued on front page F-term (reference) 4M104 AA01 BB01 BB40 CC05 DD04 DD37 DD43 DD55 DD64 DD65 DD91 EE03 EE06 EE09 EE14 EE17 FF13 GG09 5F040 DC01 EC02 EC04 EC07 ED03 ED04 EF02 EK05 FA03 FA07 FA17 FA18 FA19 FB03

Claims (7)

[Claims] A method for manufacturing a semiconductor integrated circuit device including the following steps: (a) forming a gate insulating film made of a first insulating film on a main surface of a semiconductor substrate, and then forming a first insulating film on the gate insulating film; Forming a conductive film, (b) forming a gate electrode by patterning the first conductive film by dry etching using a photoresist film as a mask, and (c) forming a first electrode on a side wall of the gate electrode. A step of thinning the gate electrode by removing the conductive film. 2. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein said first insulating film is made of an insulating material other than silicon oxide. 3. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein said first insulating film is made of an insulating material having a higher dielectric constant than silicon oxide. . 4. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the thinning of the gate electrode is performed by wet-etching the conductive film forming the gate electrode. Of manufacturing a semiconductor integrated circuit device. 5. A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: (a) forming a gate insulating film made of a first insulating film on a main surface of a semiconductor substrate and then forming a first insulating film on the gate insulating film; (B) forming a gate electrode by patterning the first conductive film by dry etching using a photoresist film as a mask, and (c) forming a gate electrode on the side wall edge of the gate electrode. Removing the gate insulating film, and (d) recovering the thickness of the gate insulating film removed in the step (c) by forming a second insulating film on the main surface of the semiconductor substrate. 6. The method for manufacturing a semiconductor integrated circuit device according to claim 5, wherein said first insulating film is made of an insulating material other than silicon oxide. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 5, wherein said first insulating film is made of an insulating material having a higher dielectric constant than silicon oxide. .