JPH0238892A - Voice timepiece with snooze - Google Patents

Abstract

PURPOSE:To facilitate vocal explanation and confirmation and attractive demonstration for a timepiece which generates different multiple signal sounds in the emission of an alarm signal and the operation of a snooze switch by emitting a required voice signal according to switching of a monitoring state. CONSTITUTION:A monitoring state is changed over to positions I and II through a mode switching circuit 63 according to a change of a mode switch. Then, in the position I, a start signal is outputted from a monitoring start signal generation circuit 82 and when a voice selection counter 74 reaches a fixed value, a voice stop detection pulse is outputted from a monitoring voice switching pulse generation circuit 76 and the counter 74 is stepped to output multiple sound signals sequentially from a voice circuit. According to an output of a snooze mode signal generation circuit 64, a snoozing state is given repeatedly. Likewise, in the state II, a voice is outputted each time a snooze switch anti SN2 is operated. This enables vocal explanation and confirmation and attraction demonstration with a simple switch operation even for a timepiece which generates different multiple signal sounds in the operation of a snooze switch.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial LQ l'f1 field) The present invention relates to an audio clock with snooze function that generates different sounds for each snooze operation, and in particular, the present invention relates to an audio clock with a snooze function that generates a different sound for each snooze operation.
Alert by operating the snooze switch? There is also one type of notification that can be switched between a notification that is sequentially generated automatically and a notification that is sequentially generated with a different notification sound each time the snooze switch is operated.

(Prior Art) A watch has been commercialized that has a snooze function that stops the generation of an alarm sound for a certain period of time.

This snooze function is a function that stops the generation of the alarm sound for a certain period of time, so in order to explain or confirm the function and the notification sound after pausing at the store, you have to wait for a certain period of time to actually elapse. I had to.

Therefore, like the clock disclosed in Japanese Patent Publication No. 61-4071, the contents of the clock circuit for counting the snooze time are configured to be fast-forwarded, so that the snooze mode can be performed without having to hold the snooze mode for a long time. It has been proposed that this can be done.

On the other hand, in recent years, clocks that notify alarms by sound have been commercialized, and among them, clocks that change the sound each time the snooze operation is performed, such as the clock disclosed in Japanese Patent Publication No. 18997/1983, have also been proposed. There is.

(Problem to be Solved by the Invention) In the case of a watch that emits a single notification sound, such as a general snooze watch, the snooze timing circuit is fast-forwarded as described above to emit the notification sound once. You can explain or confirm the snooze by simply triggering it, but if the sound emitted by each snooze changes like the watch mentioned above, all the sounds will be heard unless you repeat the fast forward operation many times. can only occur.

As a result, explanations at stores take too much time.

In addition, it forced store staff and customers to perform extremely cumbersome operations, making it necessary to change stops.

Furthermore, although demonstrations are sometimes carried out at stores by emitting audible notification sounds one after another, conventional clocks have had the problem of requiring the mooring shell to be operated one after the other.

The purpose of the present invention is to provide a watch that changes the sound that is notified each time the snooze operation is performed. To provide an audio clock with a snooze function that does not require a monitor notification and can switch the form of monitor notification.

(Means for Solving the Problems) The audio clock with snooze of the present invention includes a clock section, a reference switch, a ringing stop switch, and a first clock part that allows an ON signal from the reference switch to pass through when in a non-ringing state. a gate, an alarm-on signal generation circuit that outputs an alarm-on signal when the on-signal is generated and a first and second 1 to 1-rega signal when the on-signal is generated and disappears, a snooze switch, and a snooze switch that outputs an alarm-on signal when the on-signal is generated, and a first and second 1 to 1 trigger signal when the on-signal is generated, and a snooze switch that responds to the operation of the snooze switch. a snooze signal generation circuit that generates first and second snooze signals; a snooze mode signal generation circuit that outputs a snooze mode signal in response to generation of the second snooze signal when an alarm on signal is generated; A power-on signal generation circuit that outputs a power-on signal when only one of the mode signals is generated.

Counts only when an alarm-on signal and a snooze mode signal are generated (7) A snooze counter that outputs a count-up signal that stops generating a snooze mode signal after a certain period of time, a second 1-rega signal, a count-up signal, and an alarm-on signal No. 43 A start signal generation circuit outputs a start signal in response to the generation of a second snooze signal when the second snooze signal is generated, and a second trigger signal, an alarm on signal, and a stop signal when the first snooze signal is generated. , a stop signal generation circuit that generates a stop signal, and a callan 1 to amplifier signal or alarm on (the first snooze 43 when the Δ signal occurs).
an audio selection counter that performs counting in response to the occurrence of a start signal; an audio circuit that stores multiple types of audio notification data and outputs an audio signal corresponding to the occurrence of a start signal and a display output signal indicating its output; A mode for generating first and second monitor mode signals by external operation in an audio clock with a snooze function, which includes a notification circuit that notifies audio in response to an audio signal from the audio circuit only when an on signal is generated; A switching circuit detects the stoppage of generation of the display output signal from the l'f voice circuit from the time when the first and second monitor mode signals are generated until the count value of the voice selection counter reaches a predetermined value, and controls the juice iz selection counter. A monitor audio switching pulse generation circuit outputs a detection signal to step forward, and a snooze mode signal generation circuit outputs a snooze mode signal in response to generation of a second snooze signal when the first and second monitor mode signals are generated. Detection from the monitor mode switching circuit, the first monitor mode (when the count output of the sound μm selection counter reaches a constant value when the signal a is generated, and the detection from the monitor audio switching pulse generation circuit when the second monitor mode signal is generated) a notification end Y detection circuit that stops the generation of the snooze mode signal from the snooze mode signal generation circuit in response to the generation of the signal, and a second snooze signal when the snooze mode signal is not generated on the condition that the first monitor mode signal is generated. Then, when the snooze mode I signal is generated, a start signal is sent to the start signal generation circuit in response to the generation of the detection signal from the monitor audio switching pulse generation circuit, and when the second monitor mode signal is generated, in response to the generation of the second snooze signal. A monitor start signal generation circuit that outputs the count output signal from the middle stage of the snooze counter is input, and only when the second monitor mode signal is generated, the count output signal from the middle stage is output from the count output signal of the all audio selection counter (clear the direct). and a count signal switching circuit that outputs it as a signal.

(Operation) The audio clock with snooze consisting of the above bq components automatically switches to the current state with a single operation of the snooze switch when the first monitor mode signal is output from the mode switching circuit. The state is set to monitor (2) where audio is reported, and when the second monitor mode signal is output, the state is set to monitor (2) where audio is reported each time the snooze switch is operated.

That is, when the monitor state is entered, the monitor start signal generation circuit causes the start signal generation circuit to output a start signal, and the audio stop detection circuit increments the count of the audio selection counter to output multiple audio signals from the audio circuit. Output one after another.

Also, almost at the same time, the monitor mode switching circuit outputs a snooze mode signal from the snooze mode signal generating circuit, and repeatedly automatically puts the device in the snooze state.

Thereby, voices are announced one after another until the voice selection counter reaches a predetermined count number.

Then, when the audio selection counter reaches a predetermined count, the notification end detection circuit stops generating the snooze mode signal and ends the monitoring operation.

In addition, when the monitor ■ state is entered, the monitor start toy No. 3 generating circuit outputs a start signal from the start signal generating circuit in response to the snooze signal of 5S2 output from the snooze signal generating circuit by operating the snooze switch, and the audio circuit output an audio signal from.

When the output of this audio signal stops, a detection signal is output from the monitor audio switching pulse generation circuit.

As a result, the count number of the voice selection counter is incremented. Then, each time the snooze switch is operated, voice notification is made one after another, and each time, the count number of the voice selection counter is incremented to switch the voice to be notified.

The count value of this voice selection counter returns to the initial count value when it reaches a predetermined count number or when a predetermined time has elapsed since the snooze switch was operated.

The sounds notified by the above operation are as shown in Table I, for example.

That is, a plurality of sounds are normally switched and reported each time a snooze operation is performed, but when the monitor I is used, all the sounds are automatically notified by one operation of the snooze switch.

When set to monitor H, the audio changes and alerts you every time you press the snooze switch.

(Example) The present invention will be described in detail below based on the drawings.

FIG. 1 is a block diagram showing a circuit configuration of a main part of an audio clock with snooze according to an embodiment of the present invention, and FIG. 2 is a diagram showing a schematic configuration of an audio clock with snooze according to this embodiment.

In FIG. 2, reference numeral 2 denotes a clock section, which generates a reference signal using a crystal oscillator 4, and a clock IC 6 which synthesizes a motor drive signal of 1 + (Z) from this reference signal, and a motor driven by the motor drive signal. 8, a train 10 driven by the motor 8, and a display section 12 that displays the time using a pointer driven by the train 10.

Note that the clock section 2 in this embodiment includes a frequency divider 14 that divides the frequency of 17 pulses <a for driving the motor into 1/2.

16 is an IC for notification control which is a main part of the present invention, and V
Power supply for DD and VSS input, RC oscillation circuit 20 for O5C1-05C2 manual power. The AL11 input includes a reference switch 22 that turns on when the time of the clock section 2 reaches a set value;
Snooze switch 24 for SNZ input. For ALI2 manual operation there is a noise stop switch 26, and for the MON input there is a mode switch 28.0.5L for switching to monitor mode.
The clock section 2 is connected to each of the tz large inputs.

In addition, the powo output of this notification control IC 16 outputs a power-on signal for operating the notification circuit, which will be described later, and the 0-I2 output outputs a signal for selecting and instructing the audio signal to be output from the audio circuit, which will be described later. output, s'
The stop and start signals for stopping and starting the output of audio signals are output from the r op and LOAD outputs, respectively.

3o is an audio circuit, which is composed of an audio signal synthesis IC 32.

This audio signal synthesis IC 32 includes the XI.

A crystal oscillator 34 for obtaining a reference signal is connected to x2 manual power, 0 to 2 manual power, RESET input and ST large input notification control IC1, 6 IO to ■2 output, 5 TOP output and LOA D The outputs are connected respectively and VD
D. A power supply is connected to the VSS input.

In addition, an audio signal is output from the AVO output of this audio signal synthesis IC 32, and a display output signal indicating that an audio signal is output from the BUSY output is applied to the B IJSY input of the notification control IC 16. be done.

This audio signal synthesis IC 32 stores in advance a plurality of audio notification data such as audio A to H shown in Table I.
A voice signal is synthesized and output based on the voice notification data corresponding to the signal input to 0 to 12 human power.

38 is a notification circuit which inputs the audio signal from the AVO output of the audio signal synthesis IC to the INA input and outputs the
The notification IC 40 that drives the speaker 42 connected to the A, OUT, and B outputs, and the VD of this notification IC 10.
p of the notification control IC 16 provided between the D input and the power supply.
An outline of the operation of a voice clock with a soothing sound having a quintic configuration including a power-on circuit 44 made of a transistor whose conduction or non-conduction is determined by a power-on signal from the owo output will be explained.

Normally, when the ring stop switch 26 is in the alarm on state and the guide switch 22 is turned on, a start signal is output from the LOAD output of the notification control IC 16, and at the same time, a start signal is output from the IO~■2 output. A code signal corresponding to voice A shown in (2) is output.

Moreover, the audio signal synthesis IC 32 has its ST input and I
An audio signal representing audio A is output from the AVO output in response to the signal input to the O to 12 inputs.

The notification IC 40 that inputs this audio signal to the TNA input is connected to the power source by the power-on signal outputted from the powo output of the notification control IC 16 when the notification starts, and the power-on circuit 44 becomes conductive. The speaker 42 is driven to generate the sound A based on the sound signal.

When the sound A is generated in this way, the notification control IC 16
A stop signal is output from the 5TOP output, and the audio signal synthesis IC 32, which inputs this to the RESET input, is reset and stops outputting the audio signal.

Further, following this sound A, sound B is generated in the same manner as the above operation, and this is repeated alternately until the snooze switch 24 is turned on, and when the snooze switch 24 is turned on, sound C is generated. The audio notification will be temporarily stopped. The subsequent operations are the same as those described above, and the order of the sounds generated is as shown in Table 3.

On the other hand, when the ring stop switch 26 is in the off state, the mode switch 28 is operated to switch to the monitor mode (monitor ■ state) 5. When the snooze switch 24 is further turned on, the outputs from the IO to 2 outputs of the notification control TC 16 are The G numbers corresponding to the sounds A to H are output one after another in the same order as the normal output order.

In addition, start and stop signals are output from the L OAD output and the 5TOP output at timings corresponding to the start and stop of generation of each voice, respectively.

The audio signal synthesis IC 32 to which these signals are input outputs audio signals corresponding to the instructed audio one after another from the A■○ output.

As a result, the notification circuit 38 generates sounds one after another in the order shown in Table I.

In addition, when the I+N and stop switch 26 are in the on state, operating the mote switch 28 to switch to the monitor mode (monitor ■ state), and then operating the snooze switch 24 on, the snooze switch ′: and 4 are operated. From the 10th to 12th outputs of the notification control ICL 6, audio A −
) The signals corresponding to i are sequentially output.

For this reason, in this monitor state (2), in response to the operation of the snooze switch 24, the sounds shown in Table 1 are generated in the order shown in Table 1.

Next, the detailed circuit configuration of the notification control IC 16 shown in FIG. 2 will be explained using FIG. 1.

5o is the RC oscillation circuit 20 via 05CI-O8C3
This is an oscillation circuit connected to the oscillator and outputs a reference signal.

52 is a frequency dividing circuit which divides the frequency of the reference signal and outputs the clock signal φ4. Outputs φ2.

Reference numeral 54 denotes a first gate consisting of an AND gate which inputs signals from the reference switch 22 and the ring stop switch 26 via the AL11 input and the ALI2 manual input and outputs an on signal.

56 is a chattering prevention circuit which inputs the ON signal from the first gate 54.

58 is an alarm-on signal generation circuit, which inputs the on-signal A from the first gate 5.1 and the tally signal φ2 via the chattering prevention circuit 56, and generates the alarm-on signal A, L01AL when the on-signal A is generated. ○ and the first trigger signal R5T2 are output, and the alarm-on signal ALO1A is output.
When LO disappears, a second trigger signal RST3 is output.

60 is a chattering prevention circuit that inputs the signal from the snooze switch 24 via the SNZ input.

62 is a snooze signal generation circuit, and in response to signal B: snooze signal 5NZI of JS1 and second snooze signal (,
No. 5 5NZ2 is sequentially outputted at the timing of the clock signal φ2.

Reference numeral 63 denotes a mode switching circuit, which outputs monitor mode signals M6 and M5 of the 1st degree:jS2 in accordance with the operation of the ring stop switch 26 and the motor switch 28.

61 is a snooze mode signal generation circuit, which generates a snooze mode signal SNO in response to the generation of the second snooze signal 5NZ2 when the alarm-on signal ALO is generated.
, SNO, and stops the output in response to a signal 4M generated when a predetermined snooze time has elapsed.

Furthermore, during monitoring, the snooze mode signal S N 01SNO is activated in response to the generation of the second snooze signal 5NZ2.
The output is stopped in response to the generation of the signal R5 indicating the end of notification.

6G is a power-on signal generation circuit, which generates alarm-on signals ALO, ALO and snooze mode signals SNO, SNO.
Only when one of them occurs and the other does not occur, B
Based on the signal BtJ3 indicating the operation/non-operation of the snooping signal synthesis IC 32 inputted via the USY input, a power-on signal is outputted via the PoW◯ output.

68 is a snooze counter, which receives the signal Q2 from the intermediate stage.
Then, the signal Q1 at the time of count up is output.

69 is a count signal switching circuit, which outputs the signal Q1 as a run I/up signal 4M when an alarm is notified;
During monitor mode (2), signal Q2 is output as signal 32S.

70 is a start signal generation circuit, when the first trigger signal R5T2 is generated (when alarm notification starts), when the count amplifier signal 4M is generated (when alarm notification is resumed after snooze),
When the second snooze signal is generated (when the snooze switch 24 is operated) when the alarm-on signal AL○ is generated, the start signals L OA D and L OA D are generated, respectively.
Output l.

Note that in this embodiment, two types of sounds are alternately repeated as shown in Table 1 during normal alarm notification, so the signal generated when the generation of one sound output from the sound stop detection circuit, which will be described later, ends. Start signal L OA D also occurs when BUS2 occurs.

LOAD 1 is output.6 However, in this case, the conditions are that the alarm-on signal ALO is generated and the snooze mode signal SNO is not generated.

In addition, in the monitor mode, 672 is a stop signal generation circuit that generates start signals LOAD and LOADL in response to the generation of the second snooze signal and the generation of signal Bus 2. When the first snooze signal is generated (snooze switch 2
A stop signal 5TOI is generated in response to the second trigger signal (when the alarm notification ends) and when the second trigger signal is generated (when the alarm notification ends).

Further, in the monitor (2) state, the stop signal 5TOI is generated when the signal SM, which is generated in response to the operation of the snooze switch 24, is generated only in this state.

In addition, in this embodiment, 2
Since the different types of audio are repeated alternately, and the audio is output one after another at monitor 1, the audio signal synthesis IC32
is reset for each audio output, in response to the STAR 1 to signal LOAD1 that start the audio notification, the stop signal 5 is sent from the 5TOP output just before each audio notification starts.
Output TOP.

Reference numeral 74 is an audio selection counter, which is used when the signal 4M is generated (when the count-up signal 4M is generated, that is, when the alarm notification is restarted after snooze), when the first snooze signal 5NZI is generated when the alarm-on signal AL○ is generated (snooze switch 2
4), advance the count.

In addition, in the monitor mode, a signal M is generated each time the output of each audio is finished only in this mode.
The count advances in response to S.

Reference numeral 76 denotes a monitor audio switching pulse generation circuit, which generates a display output signal B T indicating the output state of the audio signal from the BUSY output of the audio signal synthesis IC 32 in the monitor mode.
Based on J3, the stoppage of generation of each output voice is detected and a detection signal MS is output.

Reference numeral 80 denotes a notification end detection circuit, which outputs a signal RS in response to the count value of the audio selection counter 74 reaching a constant value in the monitor ■ state or in response to a detection signal from the monitor audio switching pulse generation circuit 76 in the monitor ■ state. The generation of the snooze mode signals SNO and SNO outputted from the snooze mode signal generation circuit 64 is stopped.

Reference numeral 82 denotes a monitor start signal generation circuit, and in the monitor mode, when the snooze mode signal SNO is not generated, the start signal L OA )) is generated from the start signal generation circuit 70 in response to the generation of the second snooze signal 5NZ2.
L OA D L is output, and when the slow mode signal SNO is generated, the start f word LO is output in response to the generation of the detection signal B IJ S 2 that occurs when the output of each voice is stopped.
Output AD and LOADI.

8.1 is 1/2 frequency division, and IC32 for audio signal synthesis
A signal indicating the output state of the # voice signal output from BU
3 is divided by 1/2 and is generated after the snooze time has elapsed during normal alarm notification (signal B is reset by ffi No. 4 ?vi and is generated when the count of the audio selection counter 74 reaches a predetermined value during monitoring). T, T
It is reset by 4.

A decoder 86 converts the count value of the audio selection counter 74 into a code signal.

Next, an outline of the operation of the notification control ICL 6 having the above configuration will be explained.

When the set alarm time comes and the standard switch 22 is turned on, the alarm-on signal generation circuit 58 outputs alarm-on signals A, LO, A, and L◯.

In response to the alarm-on signals ALO and AL○, the power-on signal generating circuit 66 outputs a power-on signal powo.

In addition, the signal generation port 170 to star 1 outputs the alarm-on signal ALO output from the alarm-on signal generation circuit 58.
and the start signal L in response to the first trigger signal length ST2.
Outputs OA and D.

As a result, signals are applied from the POW○ output and the LOAD output to the audio circuit 30 and the notification circuit 38, respectively, and audio notification starts.

The audio selection counter 74 outputs a first snooze signal 5NZI, which is output from the snooze signal generation circuit 62 each time the snooze switch 24 is operated, when the alarm-on signal ALO is generated.

The count advances in response to a signal 4M generated when the snooze counter 68 counts up. Therefore, when the snooze switch 24 is operated, the decoder 86 outputs a signal indicating the next sound from the TO-12 output, and when the snooze counter 68 counts up, it further outputs a signal indicating the next sound.

Note that the audio signal synthesis IC in this embodiment needs to be reset once after outputting the audio signal and before outputting the primary audio signal. It is reset by the stop signal 5TOP output from the stop signal generation circuit 72.

Furthermore, since it becomes necessary to apply the start signal LOAD every time each audio signal is output, this start signal LOAD is also generated every time each audio signal is output.

When the reference switch 22 or the ring stop switch 26 is turned off, the generation of the alarm-on signals ALO and ALO stops, and the power-on signal powo and start signal LOAD are turned off.
The occurrence of the alarm also stops and the notification ends.

On the other hand, when the mode switch 28 is turned on when the noise stop switch 26 is in the OFF state, the signal M6 is output from the mode switching circuit 63 and the mode switch 28 is turned on, and the mode switch 28 is turned on.
When turned on, signal M5 is output and the monitor status becomes ■.

If the snooze-C switch 24 is further operated in the monitor statuses ■ and ■, the first and second snooze signals S NZ 1 are generated from the snooze signal generation circuit 26.

5NZ2 is output, and this second snooze signal 5NZ2
In response to this, the monitor start signal generation circuit 82 starts (the a-number generation circuit 70 outputs the start signal LOAD).

Further, in response to the start signal LOADl from the start signal generation circuit 70, the stop signal generation circuit 72 also outputs a stop signal 5TOP.

Further, the monitor mode switching circuit 78 causes the snooze mode signal generation circuit 64 to output the snooze mode signal 5NO1SNO in response to the second snooze signal 5NZ2.

In response to the snooze mode signals SNO and SNO, the power-on signal generation circuit 66 outputs the power-on signal powo.

In this way, when the snooze switch 24 is operated in the monitor conditions ■ and ■, the start signal LOAD is activated.

A stop signal 5TOP and a power-on signal POIJO are output, and audio notification begins.

Further, in the monitor state, the monitor audio switching pulse generation circuit 76 detects the stoppage of generation of each audio signal output by the audio signal synthesis IC 32, and outputs the signals BUS4 and MS.

This signal MS is generated in succession in the monitor I state, and is generated every time one sound is generated in the monitor II state, and is applied to the sound selection counter 74 to increment its count value.

As a result, in the monitor R state, the sound is output while being switched one after another, and in the monitor -2 state, the sound is switched and output every time the snooze switch 24 is operated.

When such a monitoring operation is performed and the count value of the audio selection counter 74 reaches a predetermined value in the monitor state, the notification end detection circuit 80 detects this and outputs the signal R.
3 and outputs a signal R3 every time the signal BUS4 is generated in the monitor (2) state.

The snooze mode signal generating circuit 64 stops generating the snooze mode signals SNO and SNO in response to this signal R5, and the power-on signal generating port v166 thereby stops generating the power-on signal POWO, and the operation ends. .

Next, the detailed circuit configuration and operation of each of the above circuits will be explained.

FIG. 3 is a circuit diagram of the mode switching circuit 63 shown in FIG. 1.

88.90 is Noah Gate, Noah Gate 88 is A
L I 2 inputs the signal from the MON input and outputs the second monitor mode signal M5, and the NOR gate 90 outputs the AL
A signal from the I2 manual input is inputted via the inverter 92, and a signal from the MON input is also inputted to output the first monitor mode signal M6.

94 is an OR gate which inputs signals M5 and M6 and outputs a composite signal M5+M6.

In this mode switching circuit 63, the noise stop switch 2
6 is in the OFF state and the MOTO 1' switch 28 is in the ON state, the first monitor mode signal M6 becomes 1 (level),
Mode switch 28 is turned on when the noise stop switch 2G is on.
is also on, the second monitor mode signal M5 becomes H.
It is set to be level.

FIG. 4 is a circuit diagram of the alarm-on signal generation circuit 58 and power-on signal generation circuit 66 shown in FIG. It is a time chart at the time of notification.

The alarm-on signal generation circuit 58 includes a flip-flop (hereinafter abbreviated as rFFJ) 100 that inputs the on-signal A and the clock signal φ2 to the human power D and the clock human power φ, respectively.
and an FF 102 which inputs the signal No. 3 φ2 from the output Q to the manual input φ and the clock input φ, respectively.
A NOR gate 104 inputs the signal from the output Q of the FF 400, the signal from the output Q of the FF 102, and the clock signal φ2, and outputs the trigger signal R3T3 to the second 1, and the FF 100.
A NOR gate 106 inputs the signal from the output Q of the FF 102, the signal from the output Q of the FF 102, and the glock signal φ2 and outputs the first trigger signal R5T2, and the first and second trigger signals R8T2. OR gate 10 that inputs and outputs R5T3
8 and the latch circuit 110, and the first and second trigger signals RST2. Input R5T3 to send alarm on signal AL
A NOR gate L12.1111 that outputs O, ALO,
It consists of

Further, the power-on signal generation circuit 66 includes the latch circuit 11
Inverters 116 and 118 that input alarm-on signals ALO and ALO from 0, respectively, Nantes gates 120 and 122 that manually input their output signals and snooze mode signals SNO and SNO, and their output signals and BUSY.
Input human input signal BU3 and power on signal P
and an AND gate 124 that outputs OW○.

In a normal alarm notification state, when the on signal A indicating that the reference switch 22 is in the on state becomes H level, the FF1OO1102 sequentially switches off its output state in response to the clock signal φ2, and during this time, the NOR gate 1
06 generates a pulse in the first trigger signal R3T2.

In response to the pulse of the first trigger signal R5T2, the latch circuit 110 outputs an alarm-on signal ';'TA
Set LO and AL○ to H and L levels, respectively.

This results in the alarm notification state as described above.

Also, this alarm-on signal AL○, AL○.

It is inverted by inverters 116 and 118 and applied to Nandt gates 120 and 122. Therefore, the output of the Nant gate 120 is held at the r level, and the Nant gate 122 keeps its output at the level 1 until the snooze mode signal SNO goes to the L level.

Therefore, the AND gate 124 becomes open, and its output signal powo becomes L level, resulting in a power-on state.

When the snooze switch 24 is operated and the snooze mode signal SNO becomes L level, the Nantes gate 122
sets its output to H level, and AND gate 124 becomes open. The L level pulse generated in the signal BU3 at this time corresponds to the sound/JC2E, G generated when the snooze switch 2/1 is operated, and the AND gate 124 is also activated during this L level pulse. The output becomes L level and the power-on state is maintained.

After that, when the on signal A goes to the L level, a pulse is generated in the second trigger signal RS T 3 output by the NOR gate 104, and the launch circuit 110 responds to this pulse by turning on the alarm on signal ALO1ALO. , switch to H level and return to the initial state.

As a result of 19, the outputs of the Nant gates 120 and 122 both go to the I level, and the output of the AND gate 124 is also held at the (■) level, turning the power off.

On the other hand, when the snooze switch 26 is in the OFF state, if you operate the mote switch 28 to set the monitor mode to ■, and then turn on the snooze switch 24, Fig. 56 (A
), the snooze mode signals SNO and SNO go to H and L levels, respectively.

Therefore, the output of the Nant gate 120 becomes L level, and the Nant gate 1-124 becomes closed.

The power will turn on.

This state is maintained until all audio notifications are completed and the snooze mode signals SNO, SNO return to their initial states.

Furthermore, when the ring stop switch 26 is in the on state, if the mode switch 28 is operated to set the monitor ■ state and the snooze switch 24 is further turned on, as shown in FIG. 6(B).
As shown in the above operation, the snooze mode signal S
N○ and SNO go to H and L levels, respectively, and the power is turned on. 8 In this monitor ■ state, the generation ends every time 1 audio notification is made and the snooze mode signal 5N is output.
When the OS: VO returns to the initial state, the power is turned off, and when the snooze switch 24 is operated, the power is turned on again.

FIG. 7 shows the times m of the snooze signal generation circuit G2 shown in FIG.
1, and FIG. 8 is a time chart thereof.

126 to 130 are FFs, and FF1Z6 inputs signal B indicating the operating state of the snooze switch 24;
The other FF128 and 130 input the signal from the output Q of the curve.

Okay, the clock of the second FF 12G to 130 is manually input (Norotsuno signal 9. is applied to 2).

132.13-1 is Noah Gate, Noah Game +-1
32 inputs each (No. 5 and clock (No. 13 φ2) from the output Q of FF12G and the output Q of FF128 and outputs the first snooze signal 5NZI, and also the NOR gate 1;
inputs each signal from the output Q of the FFL 28, the output tJQ of the FF 130, and the tarlock signal φ2, and outputs the second snooze signal 5NZ2.

FF126 to 130 in this snooze signal generation circuit 62
When the signal B becomes H level, the output state is sequentially extended at the timing of the clock signal φ2.

As a result, one heliga pulse is generated in the first snooze signal 5NZI, and a trigger pulse is generated in the second snooze signal 5NZ2 with a slight delay.

FIG. 9 shows the snooze mode signal generation circuit 6 shown in FIG.
1014 and FIG. 11 (A), (
B) is a time chart at the time of alarm notification and monitor notification.

The snooze mode signal generation circuit 64 generates a snooze mode signal SNO, a first monitor mode signal M6 indicating monitor r, and a second snooze signal S! A Nant gate 136 which inputs T22, an AND gate 138 which inputs its output signal, a signal 4M generated at the end of the snooze operation, a signal R5 indicating generation or termination of notification, a snooze mode signal SNO and a first monitor mode signal. Ant game 1-139 which manually operates M6, alarm on signal ALO, signal from AND gate 139 and monitor ■
OR gate L4 inputs the monitor mode signal M5 of
0, its output signal and the second snooze No. 45 S:N
The Nandgate 1-142 that inputs Z2, and the Nandgate 142 and Antgate 1 that constitute the latch circuits 1 and 14
Nando game h that inputs the signal from 38 146.1.4
8, an inverter 150 that inverts its output signal, an inverter 150 that inputs its output signal, a clock signal φ, and a signal RS to the clock input φ and reset input R, and an inverter 150 that inverts its output signal. An FF 154 inputs the signal, clock signal φ2, and signal R5 to the manual input, clock input φ, and reset input R, respectively, and outputs the snooze mode signals SNO and SN○ from the outputs Q and Q;
AND gate 1 which inputs the snooze signal 5NZL, the snooze mode signal SNO, and the signal M6 and outputs the signal SM.
It is composed of 56.

When the alarm notification time comes, the alarm-on signal ALO and the signal R8 from the notification end detection circuit 80 go to H level, as shown in FIG. For this reason, and gate 13
The output of No. 8 becomes H level.

Here, when the snooze switch 24 is turned on and a trigger pulse is generated in the second snooze signal 5NZ2 as described above, this trigger pulse
Generated as an L level trigger pulse at the output of l2,
In response to this, the latch circuit 144 changes its output signal δ to L
level.

This signal is inverted by the inverter 150 and sent to the FF152.
FFL52.154 is sequentially applied to clock signal φ
The output is switched at timing 2, and the snooze mode signals SN○ and SNO become H and L levels.

In this way, when the snooze mode is entered, alarm notification is temporarily stopped.

After that, when the snooze counter 68 counts up and an L level trigger pulse is generated on the signal 4M, this trigger pulse is generated at the output of the AND gate 138, and in response, the latch circuit 144 changes the output signal to the H level. Make it.

As a result, FF152 and 154 switch their output states, and the snooze mode signals SNO and SNO are
level, and the alarm notification starts again.

On the other hand, as shown in FIG. 11(A), in the monitor state (2), the first monitor mode signal M6 goes to H level, and thereby the ant gate 139 is in the open state.

Here, when the snooze switch 24 is turned on and a trigger pulse is generated in the second snooze signal 5NZ2,
This i-Riga pulse is applied to the output of the Nandt gate 142.
In response to this, the latch circuit 14.1 sets its output signal to L level. Therefore, the operation is the same as described above (p, snooze mode signal SN○, SNO is I().

■When the level is reached, monitor notification begins.

After that, when the monitor notification is finished and an L-level 1~Riga pulse is generated in the signal R8, this trigger is generated at the output of the Antogame 1-138, and in the same manner as described above, the snooze mode signal 5NO1SNO is set to r7,
Return to Rubel.

In the monitor r state, when the snooze switch 24 is turned on during monitor notification, the trigger pulse generated in the first snooze signal 5NZI is generated at the output a 'f S M of the AND gate 156 which is in the open state. However, this will stop the monitor notification.

Further, as shown in FIG. 11(B), in the monitor ■ state, the second monitor mode signal M5 becomes the ■] level, and when a trigger pulse is generated in the second snooze signal 5NZ2, this trigger pulse Also Nando game (~1
This occurs at the output of 42.

In the same way as the above operation, snooze mode signal 5NO1SN
○ becomes I(, L level, and monitor notification starts.

After that, when a trigger pulse is generated in the signal R3, the snooze mode signal 5NO3NO is activated similarly to the operation described in section 1'4.
returns to L and H levels.

In this way, in the monitor ■ state, each time the snooze switch 24 is operated, the signals SN○ and SNO from snooze mode 1 to I],
Become L level.

FIG. 12 is a circuit diagram of the snooze counter 68 shown in FIG.

158 is a counter which inputs a signal of 0.5t (z) to the clock input φ and sets the output Q to H level after counting 4 minutes.

159 inputs the signal R5T2+R3T3 and the first snooze signal SNZl to manually reset the counter 158 R.
It is a NOR gate that applies a signal to .

The counter 158 starts counting when it is reset by a trigger pulse generated in the first snooze signal 5NZI when the snooze switch 24 is turned on.

This counter 158 counts up and the output signal goes high.
When the level is reached, a trigger pulse is output from a count signal switching circuit 69, which will be described later, and the alarm notification is restarted by this trigger pulse.

FIG. 13 is a circuit diagram of the count signal switching circuit 69 shown in FIG. 1, and FIGS. 14 and 15 are time charts at the time of alarm notification and monitor notification.

160 is an AND gate that inputs the alarm-on signal ALO and the snooze mode signal SN○, and 162 and 164 are Nante gates that receive the signal Q1 from the snooze counter 68, the output signal of the AND gate 160, and the signal from the snooze counter 68, respectively. Q2 and a second monitor mode signal M5 are input.

166 is a Nantes gate which manually inputs the output signals of the Nantes gates 162 and 164.

168 and 170 are FFs, and FF168 inputs the output signal of Nantes gate 166 as an input, and FF ]
, 70 inputs the signal from the output Q of the FF 168 to the input terminal, and inputs the clock signal φ and the signal RE from the snooze counter 68 to the clock output φ and the reset input R, respectively.

Reference numeral 172 denotes a NOAR game 1 to which inputs a signal from the output Q of the FF 168 and a signal from the output Q of the FF 170.

174.175 is an and gate, and gate 1
74 inputs the output signals of the NOR gate 172 and the AND gate 160 and outputs the signal 4M, and the AND gate 175
inputs the output signal of the NOR gate 172 and the signal M5 and outputs the signal 32S.

When the alarm is on, as shown in Figure 14,
Since the alarm-on signal AL○ and the snooze mode signal SNO are at the H level, the output signal of the AND gate 160 is at the H level.

Here, when a trigger pulse is generated in the signal Ql indicating the count up from the snooze counter 68, this trigger pulse is transmitted to the FF 168 via the Nant gates 162 and 166.
is applied to the input of

As a result, the outputs of the FFs 168 and 170 are switched, and a trigger pulse is generated at the output of the NOR gate 172 at the timing of the clock signal φ1.
4 to the signal 4M.

On the other hand, in the monitor ■ state, as shown in FIG. 15, the sound changes and is output every time the snooze switch 24 is operated, but for a predetermined period of time (for example, 32 seconds) after the snooze switch 24 is operated. After the elapse of time, a trigger pulse is generated in the signal Q2 from the middle stage of the counter 158 of the snooze counter 68. This trigger pulse is
Since the signal M5 indicating the monitor ■ state is at H level, it is generated at the output of the Nant gate 164 and is further applied to the FFL 68 via the Nant gate 166. Therefore, a trigger pulse is generated at the output of the NOR gate 172 in the same manner as in the operation described above, and this trigger pulse is generated at the output signal 32S of the ant gate 175 in the open state.

FIG. 16 is a circuit diagram of the start signal generation circuit 70 and the monitor start signal generation circuit 82 shown in FIG.
7 and FIGS. 18(A) and 18(B) are time charts at the time of alarm notification and monitor notification.

The start signal generation circuit 70 generates a first − trigger signal R5.
Inverters 176 and 178 for inverting T2 and the count-up signal IM, and a Nantes gate 180 for inputting the alarm-on signal ALO, the snooze mode signal SNO, and the signal BUS2 from the monitor audio switching pulse generation circuit 76. , a Nantes gate 182 that inputs the alarm-on signal ALO and the second snooze signal 5NZ2, an inverter 176° 178, and a Nantes gate 180.182.
and a Nant gate 184 that inputs the signal from the monitor start signal generation circuit 82, an inverter 186 that inverts the output signal, and an inverter 186 that inverts the output signal.The output signal LOADI is input to the set human power S, and the human power is grounded, and further the clock human power φ is input. FFL88 to which the clock signal φ2 is input, FF190 to which the signal from its output Q is inputted, the signal LOAD1 to the set input S, and the tarok signal φ2 to the clock input φ, and the output Q of the FF188.
It is composed of a Nant gate 192 that inputs a signal from the output Q of the FF 190 and a signal from the output Q of the FF 190.

In this embodiment, the output signal LO of the inverter 186
ADI and the output signals L○, 8F] of the Nant gate 192 act as start signals.

The monitor start signal generation circuit 82 is connected to the Nant Gate 1
Consisting of 94.195.196, Nantes Gate 19.1
is the snooze mode signal SNO and the second snooze signal 5N
Z2 and the signal M5 indicating the monitor ■ are input, and the Nantes gate 195 inputs the snooze mode signal SNO and the second
snooze signal 5NZ2 and first monitor mode signal M
Furthermore, the Nant gate 196 receives an inverted version of the snooze mode signal SN○, a signal B U 2, and a signal M 5 +M 6.

As shown in FIG. 17, when the alarm is on, the alarm on signal ALO becomes H level.

A trigger pulse is generated in the first trigger signal R5T2.

This trigger pulse is generated as an L-level trigger pulse in the start signal LOAD 1 via the Nant gate 184 and the inverter 186.

The FFs 188 and 190 enter the set state in response to this trigger pulse, and then sequentially switch their output states in response to the clock signal φ2 and return to the original state.

During this time, the output of the Nant gate 192 becomes L level,
A pulse having a pulse width equivalent to one period of the clock signal φ2 is generated in the start signal LOAD.

Further, when the generated voice stops, a pulse is generated in the signal BUS2, and this pulse is generated in the signal LOAD1 via the Nant gates 180 and 184 and the inverter 186.

As a result, in the same manner as the above operation, the start signal LOA
A pulse is also generated at D.

Furthermore, when the snooze switch 24 is turned on, the second
A pulse is generated in the snooze signal 5NZ2, and this pulse is also generated in the signal L OA D l via the Nant gates 182, 184 and the inverter 186.

Therefore, in this case as well, the start signal L
A pulse is generated on OAD.

Also, the snooze counter 68 counts up, and the count annobuy No. 3 4 from the count signal switching circuit 69
When a pulse is generated in M, this pulse is also generated in the signal LOAD1 via the inverter 9178, the Nant gate 184, and the inverter 186, and in the same way, the start signal L
A pulse is generated on OAD.

As mentioned above, pulses are generated in the signal LOAD1 when alarm notification starts, when each generated sound stops, when the snooze counter is operated, and when re-notification after snooze, and the signal L
In the OAD, a pulse for actually operating the audio signal synthesis IC 32 is generated following each pulse of the signals LO and 8D1.

As shown in FIG. 18(A), in the monitor ■ state, (signal M6 is at H level, and when the snooze switch 24 is turned on, the second snooze signal is sent to the output of the Nante gate 195. The trigger pulse generated at 5NZ2 is generated as an L level trigger pulse.

This trigger pulse is generated in the signal LOAD1 via the Nant gate 184 and the inverter 186, and pulses are generated in the signals LOA and D in the same manner as described above.

At this time, the snooze mode signal S N Ol! The signal BUS2 becomes L level, and thereafter, all the pulses of the signal BUS2 that are generated every time the generated audio stops are generated at the output of the Nant gate 196.

This pulse is connected to the Nant gate 184 and the inverter 186.
The start signal LOAD1 is generated as a pulse through the start signal LOAD1, and therefore, as described above, a pulse is generated in the start signal LOAD.

Further, as shown in FIG. 18(B), in the monitor ■ state, the signal M5 is at the I (level), and the snooze switch 24 is operated to generate the second snooze signal 5N.
When a trigger pulse is generated at Z2, it is generated at the output of the Nant gate 194 as an L level trigger pulse.

This trigger pulse is also generated on signal LOAD l via Nant gate 184 and inverter 186, and
A pulse is also generated at AD.

After that, this monitor ■ state! Even in the imaginary, the signal B [
The pulse generated at J S 2 is generated at the output of the Nant gate 196 and is applied to the signal LOAL in a manner similar to the operation described above.
)1, a pulse is generated on L OA D.

FIG. 19 is a circuit diagram of the stone buoy No. 5 generating circuit 72 shown in FIG. A and FIGS. 21(A) and 21(B) are time charts at the time of alarm notification and monitor notification.

Reference numeral 198 is an AND gate that manually generates the alarm-on signal 48LO and the first snooze signal 5NZL.

200 is the output signal of the ant gate 198, the second trigger signal R5T3 that generates a pulse when the alarm ON signal ALO disappears, and the pulse that occurs when the snooze switch 2/1 is turned on during monitor notification in the monitor I state. This is a NOR gate that manually inputs the signal SM and outputs the signal STOL.

202 inputs the signal ST○1 and the signal L OA D 1 from the start signal generation circuit 70 described above, and generates the signal 5TOP.
It is an AND gate that outputs .

Normally, the signal 5TOI output by Noah games 1 to 200 is H.
level, the ant gate 202 is in an open state, and the L level pulse generated in the signal LOA1) is output as is as shown in FIG. 20 or FIGS. 21(A) and (B). Output signal s' of gate 202
Occurs on r o p.

Noah Gate 200 determines whether the snooze switches 2 and 1 are turned on when the alarm-on signal ALO is at level 1 and a pulse is generated in the first snooze signal 5NZI (temporary stop due to snooze), or when the alarm-on signal AL○ is L
level and a pulse is generated in the second 1-rega signal RST3 (the 1-coin switch 22 is turned off), or the snooze switch 271 is turned on during monitor notification in the monitor ■ state and the signal S~1 When a pulse occurs (monitor notification stops), the output signal 5TOI
generate a pulse.

FIG. 22 is a circuit diagram of the audio selection counter 74 shown in the Manjo diagram, and FIGS. 23 and 24 (A) and (!3) are time charts at the time of alarm notification and monitor notification.

204 is a Nantes gate into which the alarm-on signal AL○ and the first snooze signal 5NZI are input.

206 inputs the output signal of Nanto Game 1" 204, the signal 4>, 4 which generates a pulse when the snooze counter 68 counts up, and the signal MS which generates a pulse every time each generated sound stops only in the monitor state. Nantes Gate.

208 is an inverter that inverts the output signal of the NAND game-1-20G, and 210 is a shift 1 to register that inputs the output signal to the clock input φ and sequentially switches the output.

212 is an inverter that inverts the signal φ, 21
11 is the output signal of the inverter 212 and the shift register 2
NOR gate 216 inputting the output signal 8 of the final stage of 10
．． 218 is a latch circuit, 220 is a latch circuit 21
・This is an inverter that inverts the output signal of 1.

222 is the first snooze signal S N Z 2 and the monitor I
f! : Antogame 1 which inputs the signal M6 shown in FIG.

22.1 is the alarm-on signal A, a signal that generates a pulse when LO occurs and disappears RS T2 + RS T
:3 and.

A signal from the count signal switching circuit 69; 32S, the output of the AND gate 222 (No. 5, and a NOR gate that inputs the output signal 9 of the inverter 220;
1 is applied to the reset input R of the shift register 210.

Alarm on (When the symbol ALO goes to H level and the alarm is on, the signal RS is activated as shown in 2!).
A trigger pulse is generated at T 2 + RS T 3,
This generates a signal 1 (1) as an L level trigger pulse and resets the shift register 210.

After that, whether the snooze switch 24 is operated and a pulse is generated in the first snooze (3-') SNZ1.

Alternatively, when the snooze counter 68 counts up and pulses are generated in the signal 4M, these pulses are applied to the shift register 210 via the Nant gate 206 and the inverter 208, and the output thereof is sequentially switched.

This output signal is audio A when signal 1 is at H level,
, ) 3, signal 2 is voice C1 signal 3 is voice statement 7A, D
, signal 1 is audio E, and double signals are audio A and F.

Signal 6 indicates voice G, and signal 7 indicates voices A and H, respectively.

When the signal 8 from the final stage of the shift register 210 becomes H level, this signal 8 is converted by the launch circuit 214 to No. 43 No. 9 which becomes H level at the timing of clock < No. 3 φ, and passes through the NOR gate 224. 7 generated on signal R1. This causes shift register 210 to be reset again.

In the monitor ■ state, since the signal M6 is at H level, the pulse generated in the first snooze signal SNZ1 is generated at the output of the ant gate 222, and is output as an L level pulse at the output of the NOR gate 224. Occur.

This resets the shift register 210.

After that, a pulse is generated in the signal MS every time the generated sound stops, and this pulse is transmitted to the Nant gate 206 and the inverter 20.
8 to the shift register 210 and sequentially switches its output.

When the signal 8 from the shift register 210 becomes H level, the shift register 210 performs the same operation as described above.
will be reset.

In addition, in the monitor ■ state, the shift register 210 is controlled by a pulse generated in the signal MS every time each generated sound stops.
switches its output, and when the signal 8 becomes H level or a pulse occurs on the signal 32S, the shift register 2
10 is reset.

FIG. 25 is a circuit diagram of the monitor audio switching pulse generation circuit 76 shown in FIG. 1, and FIG. 26 is a time chart thereof.

228 to 232 are FFs, the clock signal φ2 is applied to the clock input φ, and the FI228 receives the signal BU from the BUSY input via the inverter 226
3 into the input field, and FF230.2:32 is 1)? 1
The signal from the output Q of the FF in the stage is input manually.

234 is an inverter that inverts the signal 9; 236 is an inverter that inverts the output signal of the inverter 234;
This is an AND gate applied to R.

238.240 is Noah Gate, Noah Gate 238
inputs the signal from the output Q of FF228, the signal from the output Q of FF230, and the clock signal φ2, and the NOR gate 240 inputs the signal from the output Q of FF230 and the signal from the output Q of FF230, and the clock signal φ2.
The signal from the output Q and the solo logic (No. 6 > 2) are input.

2421 Sat Signal 2 from the shift register 210 described above
, 4.6 is an OR gate.

2.14.2.16 are Nant gates, Nant gate 271.1 inputs the output signal of OR gate 242 and signal BUS 1 from NOR gate 238, and Nant gate 246 receives No. 43 BUS 1 and 1/2 frequency division. The signal BU2 from the device 84 is input.

248.250 is also Nantes Gate, Nantes Gate 2
48 inputs the output signals of the Nant gates 244 and 246, and the Nant gate 250 inputs the output signal BUS5 and the signals M5+M6 and outputs the signal MS.

The above-mentioned FFs 228 to 232 sequentially switch their output states in response to a pulse generated in the signal BU3 indicating the generation state of the audio signal output by the audio signal synthesis device C32.

As a result, a pulse is generated in the output of the NOR gate 238 (No. a Bus) when the output of each audio signal is stopped, and the output signal BUS2 of the NOR gate 240 is generated with the signal BUSI in order to ensure the operation of other circuits. The pulse is generated one cycle of the clock signal φ2 later than the pulse.

On the other hand, signals 2, 4.6 input to the OR gate 242 indicate voices C, E, and G, respectively.

The output signal of the OR gate 242 and the signal BUSI are synthesized by the Nant gate 244, and when the voices C, E, and G stop, an L level pulse is generated in the output signal BUS4.

Further, the Nant gate 246 divides the frequency of the signal BU3 by 1/2, and when the sound A is generated, always synthesizes the signal BU2 and the signal BUSI, which are at the I (level).
Outputs a signal that generates an L level pulse when audio A, B, audio A, D, audio A, F, audio A, H stops.

This A word and signal BUS4 are further connected to the Nantes gate 248.
The synthesized signal is generated as the output signal MS of the NAND games 1 to 250 only when the signal MS-1 to M6 indicating the monitor state is at the H level.

FIG. 27 is a circuit diagram of the notification end detection circuit 80 shown in FIG. 1, and FIGS. 28 and 29 (A) and (B) are time charts at the time of alarm notification and monitor notification.

252 is a NOR gate, which is input to the alarm-on signal ALO and signals M5 and M6 indicating the monitor status.

253.254 is an and gate, and gate 2
53 inputs the signal M5 and the signal BUS4, and the AND gate 254 inputs the signal M6 and the signal 9 from the audio selection counter 74.
is being entered.

A NOR gate 256 inputs the output signals of the NOR gate 252 and AND gates 253 and 254, and the first and second trigger signals R3T2+R5T3, and outputs a signal R3.

In the alarm-on state, as shown in FIG. 28, the alarm-on signal ALO becomes H level, which causes the output of NOR gate 252 to become L level. This signal and the trigger pulse generated in the signals R5T2+R3T3 are combined in the NOR gate 256, and the signal R5 becomes level 1 during the alarm ON state.

In addition, in the monitor ■ state, as shown in FIG. 29(A), the signal M6 is at the H level, so the output of the NOR gate 252 is held at the L level, and the AND gate 254 is in the open state. There is. Therefore, the output signal R3 of the NOR gate t-256 is kept at the H level until a pulse is generated in the signal 9, and when the pulse is generated in the signal 9, this pulse is generated as an L level pulse in the signal R3.

In the monitor H state, the signal M5 becomes H level as shown in FIG.
The output of 252 is held at L level, and the AND gate 2
53 becomes open. Here, a pulse is generated when the voices C, E, and G are generated (when a pulse is generated on the j-no. BUS 4, this pulse is generated on the no. 43 RS as an L-level pulse).

FIG. 30 is a circuit diagram of the 1/2 frequency divider shown in FIG.
FIGS. 31 and 32 (A) and (B) are time charts at the time of alarm notification and monitor notification.

258 is 17F, and its clock power φ is BU
Signal from S Y input B U 3 & human power,
Outputs Q and Q output signals BU2 and BO2, respectively.

260.262 is an and gate, and ant game-1-
260 inputs the signal 4M, which generates a pulse when the snooze counter 68 counts up, and the signal LOAD2 from the star 1 signal generation circuit 70, and outputs the AND gate 26.
2 is a signal R1 that generates a pulse when audio generation stops;
Signal B that generates a pulse when audio C, E, and G end.
Input US4 and the output signal of AND gate 260,
An output signal is applied to the reset input R of the FF 258.

When the FF258 is in the alarm on state, the signal B U
3 is divided into 1/2 and output, and the snooze counter 6
It is reset when 8 counts up.

In this embodiment, the sound generated after snoozing is always the sound A, and correspondingly, when the No. 4 BU2 is also output to the sound, it always goes to the L level.

On the other hand, during monitoring, this FF 258 is reset after the sounds C, E, and G are generated. For this reason, voice C,
After E and G, the signal BU2 always goes to the L level, which coincides with the timing at which the sound A is generated.

FIG. 33 is a diagram showing more detailed input/output of the decoder 86 shown in FIG. 1.

This decoder 86 inputs the output signals 1 to 8 of the multi-connected voice selection counter 74, converts them into code signals corresponding to each voice, and outputs the code signals from the IO to 2 outputs.

Signals L to 8 correspond to different voices, but signals 1.3 and 5.7 in this example correspond to voices A, B, M iTA, D, respectively, as shown in FIG.
It corresponds to voice A, F, voice A, ■(.

Therefore, when the decoder 86 in this embodiment receives the signals 1, 3, 5, and 7, it outputs a code signal according to the state of the signal BU2 from the 1/2 frequency divider 84 described above.

For example, when signal 1 is at H level and signal BU2 is at L level, a code signal for voice A is output, and when signal 1 is at H level and signal BU2 is at H level, a code signal for voice B is output.

In this way, decoder 86 outputs signals 1-8 and signal BU2.
In response to the sound, a code signal corresponding to the sounds A to () is output.

(Effects of the Invention) According to the present invention, even if a clock generates a plurality of different sounds when notifying an alarm or operating a snooze switch, when the watch is set to the monitor state, the sounds will be automatically sent one after another in the normal order of alarm notifications. A sound will be generated and the sound will be switched depending on the snooze switch operation when the monitor is in the ■ state.

Therefore, it is easy to explain or confirm the sounds generated at the store, and it is also easy to conduct demonstrations to attract customers.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the circuit configuration of the main parts of an audio clock with snooze according to an embodiment of the present invention. FIG. 2 is a diagram showing a schematic configuration of the audio clock with snooze according to the present embodiment, and FIG. 3 is a circuit diagram of the mode switching circuit shown in FIG. 1. The IUA is a circuit diagram of the alarm-on signal generation circuit and power-on signal generation circuit shown in Figure 1, Figures 5 and 6 (
A) and (B) are the time charts of the signals in FIG. 4, FIG. 7 is the circuit diagram of the snooze signal generation circuit shown in FIG. 1, 8i2I is the time chart of the signals in FIG. 7, and 9 [A is 2 is a circuit diagram of the snooze mode signal generation circuit shown in FIG. 1. FIG. 10 and 11 (A) and (B) are time charts of the signals in FIG. 9, and FIG. 12 is a circuit diagram of the snooze counter shown in FIG. 1. Figure 13 is a circuit diagram of the count ('JU number switching circuit) shown in Figure 1. Figures 14 and 15 are time charts of number 45 in Figure 13. Figure 16 is the start signal generation shown in Figure 1. Circuit and monitor start signal generation circuit circuit diagrams, Figures 17 and 18
Figures (6.\) and (B) are time charts of the signals in Figure 16. Figure 19 is a circuit diagram of the stop signal generation circuit shown in Figure 1, Figures 20 and 21 (A) and (B) are time charts of the signals in Figure 19, and Figure 22 is shown in Figure 1. A circuit diagram of the audio selection counter. Figures 2 and 3 and Figures 24 (A) and (B) are time charts of signals in Figure 22. FIG. 25 is a circuit diagram of the monitor audio switching pulse generation circuit shown in FIG. 1. FIG. 26 is a time chart of the signals in FIG. 25. Section 27 is a circuit diagram of the notification end detection circuit shown in FIG. Figures 28 and 29 (A) and (B) are time charts of the signals in Figure 27; Figure 30 is a circuit diagram of the 1/2 frequency divider shown in Figure 1;
32 (A, ) and (B) are time charts 1- of the signals in FIG. 30. FIG. 33 is a diagram showing detailed input/output of the decoder shown in FIG. 1. 2...Clock part, 16...Notification control IC
122・Reference switch, 24・Snooze switch, 26・Sound stop switch. 28...Mode switch, 30...Audio circuit, 38...
- Notification circuit, 50 - Oscillation circuit, 52 - Frequency dividing circuit, 511 - First gate, 58 - Alarm-on signal generation circuit. 62...Start signal generation circuit, (3.1 Suspension mode signal generation circuit, 6(5...
Power-on signal generation circuit, 68... Suzuzu counter. 69...Count signal switching circuit, 70...Start signal generation circuit, 72...Stop signal generation circuit, 7.1...Audio selection counter, 76...Monitor audio switching pulse generation circuit, 80 Nisuchi End detection circuit. 82...Monitor start signal generation circuit. 84...1/2 frequency divider, 86...decoder. 4th circle 5th circle Ano-K) state 1 ST3, f6 times (B) 7 ar ■ direction. , f6 Encircle (A) and 4- L; (B) 11th round (A) O 9th round 10th round - Muongyi 51° 12th ST3 M SNO 714 questions 7 U - tA4 n-shaped turtle; 't' 15th round 8th r, Pezen stage 18th round (B) 19th round NZ2 Pa 18th round (A) 220th round LO Y Ram λn translation゛21st round (B) Monitor 14 shaku) Kei Nita ■, 23rd round R5T2 + R5T: ] Y To Lam A, the top ψme qn ~ - 240th (B) 1 monitor 1 reef 1 24th (A) 226 questions 1 bottle of monitor (Introduction 31st Go-tA > Bottle! Soup 32 Time (B) Mo; Gamer, i 〉29 questions (A) A. M5+M6 R5T2+R5T3 Monitor ■ US4 S

Claims (1)

[Scope of Claims] A clock unit that generates a reference signal to measure and display the time, a reference switch that is turned on when the time from the clock unit reaches a set time, a ring stop switch, and the ring stop switch. a first gate that allows the ON signal from the standard switch to pass through when the alarm is not in a non-sounding state; an alarm-on signal generation circuit that generates a first trigger signal and outputs a second trigger signal when the alarm-on signal disappears; a snooze switch; a snooze signal generating circuit that outputs a snooze mode signal in response to generation of the second snooze signal only when the alarm on signal is generated; A power-on signal generation circuit outputs a power-on signal only when one mode signal is generated and the other is not generated, and a reference signal from the clock section is counted only when the alarm-on signal and the snooze mode signal are generated. , a snooze counter that outputs a count-up signal that stops generating the snooze mode signal after a certain period of time; a start signal generation circuit that outputs a start signal when the second trigger signal, the alarm on signal and the first snooze signal are generated; a stop signal generation circuit that generates the stop signal when the second trigger signal, the alarm on signal and the first snooze signal are generated; and the count up signal or alarm on signal generation a voice selection counter that counts in response to the generation of the first snooze signal at the time; and a voice selection counter that stores a plurality of types of voice notification data and corresponds to the count value of the voice selection counter in response to the generation of the start signal. An audio circuit with snooze, comprising: an audio circuit that outputs an audio signal and a display output signal indicating the audio signal output; and a notification circuit that notifies audio in response to the audio signal from the audio circuit only when the power-on signal is generated. The watch further comprises: a mode switching circuit that generates first and second monitor mode signals by an external operation; a monitor audio switching pulse generation circuit that detects stoppage of display output signal generation from the audio circuit and outputs a detection signal that increments the audio selection counter; a monitor mode switching circuit that causes the snooze mode signal generation circuit to output a snooze mode signal in response to generation of a snooze signal; and when the count output of the audio selection counter reaches a constant value when the first monitor mode signal is generated; and a notification end detection circuit that stops generating the snooze mode signal from the snooze mode signal generation circuit in response to generation of the detection signal from the monitor audio switching pulse generation circuit when the second monitor mode signal is generated; 1 monitor mode signal is generated, when the snooze mode signal is not generated, the second snooze signal is generated, and when the snooze mode signal is generated, the second snooze signal is generated in response to the generation of the detection signal from the monitor audio switching pulse generation circuit, and the second snooze signal is generated. When the monitor mode signal is generated, the second
a monitor start signal generation circuit that outputs a start signal to the start signal generation circuit in response to the generation of the snooze signal; and a monitor start signal generation circuit that receives a count output signal from an intermediate stage of the snooze counter and generates the second monitor mode signal. 1. A sound clock with snooze, comprising: a count signal switching circuit that outputs a count output signal from the middle stage only at the time as a signal for clearing the count value of the sound selection counter.