JPH0240591A - Voice clock with snooze - Google Patents

Abstract

PURPOSE:To make IC common in use and to reduce the cost by switching a circuit having a function of generating a snooze stop confirmation sound and a one not having this function. CONSTITUTION:A mode switching circuit 53 outputs a switching mode signal, a first snooze operation start detecting circuit 76 outputs a first snooze start signal as a step advance signal to a voice selection counter 74. In response to the generation of a second snooze start signal at the time when the switching mode signal is generated, a second snooze operation start detecting circuit 70 makes a start signal outputted from a start signal generating circuit 68. A skip selecting circuit 78 supplies the second snooze start signal as a step advance signal to the voice selection counter 74, in place of an incremental signal, at the time when the switching mode signal is not generated. According to this constitution, the voice as a snooze stop operation confirmation sound is not generated when the switching mode signal is not generated, while different voices are generated at the time of the operation of a snooze switch when the switching mode signal is generated.

Description

[Detailed Description of the Invention] (Field of Industrial Application) The present invention relates to the improvement of a watch with a snooze function, and in particular, a watch with a snooze pause operation confirmation sound generation function and a watch without the snooze function. 6. Concerning devices that can be switched using integrated circuits (Prior art) Conventionally, like the clock disclosed in Japanese Utility Model Publication No. 11670/1983, a confirmation sound is generated every time the snooze switch is operated. Something has been devised to make it happen.

By generating the confirmation sound in this manner, it becomes possible to easily confirm whether or not the switch has been operated.

(Problem to be Solved by the Invention) When the notification sound is a simple electronic sound as in the conventional case, it is necessary to design an IC to uniformly generate a confirmation sound and adapt it to multiple types of watches. However, depending on the content of the sound, it may be better not to add a pause operation confirmation sound, or it may be sufficient to do without the confirmation sound, depending on the content of the sound that has been commercialized in recent years. There are various devices that can tell when a switch has been operated, etc., and a new IC must be redesigned each time, which poses the problem of increased costs.

An object of the present invention is to make it possible to switch between a device with a function of generating a snooze pause confirmation sound and a device without a function with a simple operation, to use a common IC, and to reduce costs.

(Means for Solving the Problems) The audio clock with snooze of the present invention includes a clock section, a reference switch that outputs an alarm-on signal, a ringing stop switch, and a ringing stop switch that allows the alarm-on signal to pass when in a non-sounding state. a first gate, an operation signal generation circuit that outputs an operation signal in response to an alarm-on signal, a snooze switch, and a snooze start signal that outputs first and second snooze start signals in response to an on operation of the snooze switch. a generating circuit, a snooze counter that counts in response to a first snooze start signal and outputs a count-up signal, and a snooze mode that prevents generation of an operation signal from the time when the second snooze signal is generated until the time when the count-up signal is generated. A snooze mode signal generation circuit that outputs a signal, a start signal generation circuit that outputs a start signal in response to the generation of an alarm-on signal and a count-up signal, an audio selection counter that counts the count-up signal, and a start signal generation circuit that outputs a start signal in response to generation of an alarm-on signal and a count-up signal. an audio circuit that responds by outputting an audio signal corresponding to the count value of the audio selection counter and stops operating when a snooze start signal is generated or when the operating signal disappears; and a notification circuit that inputs the audio signal and notifies the audio; An audio clock with snooze function, comprising: a mode switching circuit that outputs a switching mode signal; a first snooze operation start detection circuit that outputs a first snooze start signal to an audio selection counter as a step signal; and a switching mode signal generation circuit. a second snooze operation start detection circuit that outputs a start signal from the start signal generation circuit in response to the generation of the second snooze start signal; It consists of an interlace selection circuit that supplies a signal to a voice selection counter as an increment signal;

(Function) In the audio clock with snooze configured as above, if the switching mode signal is not output from the switching mode circuit,
The start signal generation circuit generates a start signal only when the alarm is turned on or when a count-up signal from the snooze counter is generated.

At this time, the audio selection counter also outputs an increment signal output from the first snooze operation start detection circuit in response to the first snooze start signal, and an output from the jump selection circuit when the second snooze start signal is generated. advances its count in response to an increment signal.

That is, when the switching mode signal is not generated, the sound is generated only when the alarm is on and when the snooze pause ends, and the switching of the sound is advanced by two when the snooze switch is operated, and as a result, the sound is heard as the snooze pause confirmation sound. On the other hand, if the switching mode signal is output from the switching mode circuit, the start signal generating circuit will not only output the sound in the above case but also when the second snooze start signal is generated. The start signal is also output in response to the signal output from the snooze operation start detection circuit No. 2.

Additionally, the audio selection counter advances its count only in response to the first snooze start signal.

As a result, when the switching mode signal is generated, a sound is generated not only when the alarm is turned on and when the snooze pause ends, but also when the snooze switch is operated.The switching of the sound is advanced by 1 for each snooze switch operation, and the snooze pause operation is confirmed. Sound is output.

The sound notified by the above operation is, for example, as shown in Table 3.

Table (1) That is, when the switching mode signal is not generated, no sound is generated to confirm the snooze pause operation, but when the switching mode signal is generated, different sounds are generated when the snooze switch is operated.

(Example) The present invention will be described in detail below based on the drawings.

FIG. 1 is a block diagram showing a circuit configuration of a main part of an audio clock with snooze according to an embodiment of the present invention, and FIG. 2 is a diagram showing a schematic configuration of an audio clock with snooze according to this embodiment.

In FIG. 2, 2 is a clock section, which includes a clock IC 6 that generates a reference signal using a crystal oscillator 4, synthesizes 17 motor drive signals from this reference signal, and a motor 8 that is driven by the motor drive signal. It has a train 10 driven by a motor 8, and a display section 12 that displays the time using a hand driven by the train 10.

Note that the clock section 2 in this embodiment includes a frequency divider 14 that divides the frequency of 17 pulse signals for driving the motor into 1/2.

16 is a notification control IC which is a main part of the present invention;
D. A power supply for the VSS input, an RC oscillation circuit 18 for manual power from 08C1 to oS03, and a reference switch 20 for the ALII input that turns on when the time of the clock section 2 reaches a set value. S
The NZ input has a snooze switch 22, the ALI2 manual input has a ring stop switch 24, the MODI and MOD2 manual input have a mode changeover switch 26, 28, 0.5 for switching between generation and non-generation of the snooze pause confirmation sound. Clock sections 2 are connected to each.

In addition, the PoW○ output of this notification control IC 16 outputs an operation signal for activating the notification circuit, which will be described later, and the IO~2 output outputs a signal for selecting and instructing the audio signal to be output from the audio circuit, which will be described later. is output, and stop and start signals for stopping or starting the output of the audio signal are output from the 5TOP and LOAD outputs, respectively.

Reference numeral 30 denotes an audio circuit, which includes an audio signal synthesis IC 32.

A crystal oscillator 34 for obtaining a reference signal is connected to this audio signal synthesis IC 32, and
o-I 2 manual, RESET and ST large input notification control I
The lo-I2 output, 5TOP, and LOAD output of C16 are connected to each other, and the power supply is connected to the voo and vss inputs.

Also, an audio signal is output from the AVO output of this audio signal synthesis IC 32, and a display output signal indicating that an audio signal is being output is output from the BUSY output, and is applied to the BUSY input of the notification control IC 16. Ru.

This audio signal synthesis IC 32 stores alarm notification audio data of a plurality of voices A1 to D1, A2 to E2, and A3 to H3 shown in Table (1) in advance, and inputs the signals to IO to (2) human power. An audio signal is synthesized and output based on the corresponding audio data.

36 is a notification circuit, which includes a notification IC 38 that inputs the audio signal from the AV○ output of the audio signal synthesis IC to the INA input and drives the speaker 4o connected to the 0UTA and ○UTB outputs; A power-on circuit 42 is provided between the VDD input of the IC 16 and the power supply, and is made up of a transistor whose conduction or non-conduction is determined by a power-on signal from the POW○ output of the notification control IC 16.

Next, an outline of the operation of the audio clock with snooze configured as described above will be explained.

In this embodiment, two mode changeover switches 26.
28 is provided, and depending on its on/off state, Ml
, M2. It is configured so that M3 mode can be selected. In this Ml, 82 mode, the snooze pause operation confirmation sound is not generated, but is set to be generated only in the M3 mode.

For example, in the M1 mode, when the reference switch 20 is turned on while the alarm stop switch 24 is in the alarm on state, an operation signal is output from the LOAD output of the notification control IC 16, and at the same time, an operation signal is output from the LOAD output of the notification control IC 16. A code signal corresponding to voice A1 shown in Table I is output from the second output.

Moreover, the audio signal synthesis IC 32 outputs an audio signal representing the audio A1 from the AVO output in response to the signal inputted to the ST power input 0 to 2 manual power.

The notification IC 38 that inputs this audio signal to the INA input inputs the audio signal because the power-on circuit 42 is brought into conduction by the operation signal output from the powo output of the notification control IC 16 at the start of notification, and is connected to the power source. The speaker 40 is driven based on the audio signal to generate audio A1.

When the voice A1 is generated in this way, the notification control IC1
A stop signal is output from the 5TOP output of No. 6, and the audio signal synthesis IC 32 which inputs this to the RESET input is reset and stops outputting the audio signal.

Further, following this voice A1, voice A1 is generated again in the same manner as the above operation, and this is repeated until the snooze switch 22 is turned on. When the snooze switch 22 is turned on, the voice notification is temporarily stopped. . The subsequent operations are similar to the above operations, and the order in which the sounds are generated is shown in the table below. As shown.

In the case of the M2 mode, the operation is almost the same as that described above, but the only difference is that the voice to be notified consists of different types of voices as shown in Table 2, and these are alternately notified.

In this way, in the Ml and M2 modes, the snooze pause operation confirmation sound is not notified, but in the M3 mode, even when the snooze switch 22 is operated, an operation signal is output from the powo output of the notification control IC 16, and at this time, the IO A code signal instructing a sound as a snooze pause operation confirmation sound is outputted from the output of the second output, and as a result, a sound is also notified when the snooze switch 22 is operated.

Next, the detailed circuit configuration of the notification control IC 16 shown in FIG. 2 will be explained using FIG. 1.

50 is an oscillation circuit connected to the RC oscillation circuit 18 via 03CI-O8C3, and outputs a reference signal.

A frequency dividing circuit 52 divides the frequency of the reference signal and outputs a clock signal φ2.

A mode switching circuit 53 outputs signals M1, M2, and M3 indicating the M1, M2, and M3 modes, respectively, in accordance with signals from the mode selector switches 26 and 28 that are inputted manually via MODI and MOD2.

Reference numeral 54 designates a first gate consisting of an AND gate which inverts and inputs the signals from the reference switch 20 and the ring stop switch 24 via the AL11 input and the ALI2 manual input, and outputs an alarm-on signal.

56 is a chattering prevention circuit that inputs the alarm-on signal from the first gate 54.

Reference numeral 58 denotes an operation signal generation circuit, which outputs an operation signal POW○ when the alarm-on signal A from the first gate 54 is inputted via the chattering prevention circuit 56.

60 is a chattering prevention circuit that inputs the signal from the snooze switch 22 via the SNZ input.

62 is a snooze start signal generation circuit, and when an alarm on signal is generated and the alarm is on,
Snooze switch 2 via chattering prevention circuit 60
When the signal B from 2 is input, the first and second snooze start signals 5NZI and 5N are activated at the timing of the tarok signal φ2.
This is to sequentially output Z2.

64 is a snooze counter, and a snooze switch 22
The first snooze start signal 5NZ generated when is operated.
In response to I, it counts 0.5 Hz signals input from 0.57 inputs, and outputs a count-up signal 4M after a certain period of time.

66 is a snooze mode signal generation circuit, which outputs snooze mode signals SN○ and SNO in response to the second snooze start signal 5NZ2 when the alarm is on, and stops outputting when the snooze counter 64 counts up. It is something.

While this snooze mode signal SNO is being generated, the operation signal generation circuit 58 is prevented from outputting the operation signal powo.

Reference numeral 68 is a start signal generation circuit, which is used to generate signals at the time of starting alarm notification, when resuming alarm notification after snooze, and the second signal generation circuit described later.
When the signals from the snooze operation start detection circuit and the repetition signal output circuit are input, the start signal LOA is output, respectively.
Output D.

7o is a second snooze operation start detection circuit, which outputs the start signal LOAD from the start signal generation circuit 68 in response to the second snooze start signal 5NZ2 generated when the snooze switch 22 is operated only in the M3 mode. This is what outputs it.

Reference numeral 72 denotes a repeating signal output circuit, which causes the repeating start signal generating circuit 68 to output a start signal in response to a signal BUS2 outputted from a sound stop detection circuit (to be described later) every time sound generation stops when the alarm is on. be.

74 is a voice selection counter, 76 is a first snooze operation start detection circuit, and 78 is an interlace selection circuit. In the Ml and M2 modes, the audio selection counter 74 is set to two in succession by the first and second snooze start signals 5NZI and 5NZ2 inputted via the first snooze operation start detection circuit 76 and the skip selection circuit 78. Advance the count step by step.

In the case of the M3 mode, the first snooze start signal 5NZI from the first snooze operation start detection circuit 76 and the signal 4M generated when the snooze counter 64 from the skip selection circuit 78 counts up increase the count to 1. You can proceed step by step.

80 is an audio stop detection circuit, which includes an audio signal synthesis IC3.
Based on the display output signal BU3 indicating the output state of the audio signal from the BUSY output of No. 2, it detects that the generation of audio has stopped and outputs the detection signal BUS2.

82 is a 1/2 frequency divider, which divides the signal BU3 indicating the output state of the audio signal output from the audio synthesis IC 32 by 1/2.
It divides the frequency and outputs a signal BU2 for distinguishing between the sounds A2 and A3 and the next sound generated in the M2 and M3 modes.

84 is a decoder, 86 is a single voice repetition circuit, and 88 is a multiple voice repetition circuit. The single voice repetition circuit 84 is
The signal from the voice selection counter 74 is applied to the decoder 84 when the signal M1 is generated, and the multiple voice repeat circuit 88 applies the signal from the voice selection counter 74 to the decoder 84 when the signal BU2 is generated while the signal M2 or M3 is generated. The signal from 74 is changed into a signal indicating a predetermined voice and is applied to decoder 84.

Next, an outline of the operation of the notification control IC 16 having the above configuration will be explained.

When the set alarm time comes and the reference switch 20 is turned on, the operation signal generation circuit 58 outputs a signal ALO and an operation signal POW○ indicating that the alarm is on.

Start signal generation circuit 68 outputs start signal LOAD in response to trigger signal R8T2 output from operation signal generation circuit 58 when signal ALO is generated.

As a result, signals are applied from the powo output and the LOAD output to the audio circuit 30 and the notification circuit 36, respectively, and audio notification starts.

When the M1 mode is selected, the signal output from the voice selection counter 74 is applied to the decoder via the single voice repetition circuit 86, and when the M2 and M3 modes are selected, the signal output from the voice selection counter 74 is applied to the decoder through the single voice repetition circuit 86. It is applied to the decoder via circuit 88.

In the Ml and M2 modes, the audio selection counter 74 outputs the first and second snooze start signals 5NZI and 5NZ2 output from the snooze start signal generation circuit 62 when the snooze switch 22 is operated to the snooze operation start detection circuit 7.
6 is input via the skip selection circuit 78, and the count value is incremented by two. As a result, the signal 2.4.6 for generating the snooze pause operation confirmation sound is skipped, and the snooze pause operation confirmation sound is not generated.

In addition, in the case of M3 mode, the signal 4M generated when the snooze counter 64 counts up instead of the second snooze start signal 5NZ2 is sent to the skip selection circuit 7.
8 to the audio selection counter 74, and as a result, the audio selection counter 74 is incremented by 1 when the snooze counter 64 counts up and when the snooze switch 22 is operated. For this reason, the signal 2.4 for generating the snooze pause operation confirmation sound.
6 is output when the snooze switch 22 is operated, so that this snooze pause operation confirmation sound is generated in the M3 mode.

On the other hand, when in Ml or M2 mode, the snooze switch 22
Even if the second snooze start signal 5NZ2 is operated, the second snooze start signal 5NZ2
Application to the start signal generation circuit 68 is blocked by the second snooze operation start detection circuit 70, but in the M3 mode, it is applied to the start signal generation circuit 68 via the second snooze operation start detection circuit 70. Therefore, only in the M3 mode, the start signal LOAD is generated even when the snooze switch 22 is operated.

Note that the audio signal synthesis IC 32 in this embodiment needs to be reset once after outputting an audio signal and before outputting the next audio signal. The stop signal 5TOP synthesized by the start signal generation circuit 62 is output, and the circuit is reset.

Furthermore, since it becomes necessary to apply the start signal LOAD every time each audio signal is output, this start signal LOAD is also generated every time each audio signal is output.

When the reference switch 20 or the ring stop switch 24 is turned off, the generation of the signal ALO indicating alarm on stops, the generation of the operation signal powo and the start signal LOAD also stops, and the notification ends.

Next, the detailed circuit configuration and operation of each of the above circuits will be explained.

FIG. 3 is a circuit diagram of the mode switching circuit 53 shown in FIG. 1, and FIG. 4 is a time chart thereof.

100 to 104 are Noah gates, each with MODI
, signals E and F from MOD2 manual input, signal E and signal F inverted by inverter 108, and signal E and signal F inverted by inverter 106 are input.

In this mode switching circuit 53, a signal M indicating the M1, M2, and M3 modes, respectively, depending on the states of the signals E and F.
1, M2, and M3 each go to H level, and a mode corresponding to the signal at I (level) is set.

FIG. 5 is a circuit diagram of the operation signal generation circuit 58 shown in FIG. 1, and FIGS. 6 and 7 are time charts in M1, M2 mode, and M3 mode.

110 and 112 are flip-flops (hereinafter abbreviated as "FF"), FFll0 inputs the alarm-on signal A to its input, and FF112 inputs the signal from the output Q of FFll0 to its input, and both clock signal φ
2 is input to the clock manual power φ.

114.116 is Noah Gate, Noah Gate 114
is the signal from the output Q of FFll0 and the output Q of FF112
The NOR gate 116 inputs the signal from FF1 and the clock signal φ2 and outputs the second trigger signal R8T3.
The signal from the output Q of l0, the signal from the output Q of FF112, and the clock signal φ2 are input to generate the first trigger signal R8.
Output T2.

118 is an OR gate, and the first and second trigger signals R
5T2. I am inputting R5T3.

Reference numeral 120 denotes a latch circuit composed of NOR gates 122 and 124 which input the second and first trigger signals R8T3 and R8T2, respectively.

128 is a Nant gate, into which the signal SNO from the snooze mode signal generation circuit 66 and the signal from the latch circuit 120 are inputted via the inverter 126.

130 is an AND gate which inputs the output signal of the Nandt gate 128 and the signal BU3 from the BUSY input and outputs the operation signal powo.

When the reference switch 22 is turned on and the alarm-on signal A becomes H level, the FFll0°112 sequentially switches its output state in response to the clock signal φ2, and during this time the NOR gate 116 pulses the first trigger signal R3T2. to occur.

In response to the pulse of the first trigger signal R8T2, the latch circuit 120 sets the signal ALO outputted via the inverter 126 to H level. This causes an alarm notification state as described above.

Furthermore, when this signal ALO goes to H level, the output of Nandt gate 128 goes to L level while signal SNO is at H level, so AND gate 130 becomes closed, and the operation signal PoWOfJ becomes less than L level and operates. become a state.

As shown in FIG. 6, in the M1 and M2 modes, the snooze state occurs, and when the signal SNO goes to the L level, the operation signal POW○ goes to the H level and the notification is temporarily stopped, and as shown in FIG. In mode, after signal SN○ goes to L level, snooze pause operation confirmation sound C3, E3,
The operation signal powo is kept at the L level until G3 is generated and the signal BU3 goes to the H level.

FIG. 8 is a circuit diagram of the snooze start signal generating circuit 62 shown in FIG. 1, and FIG. 9 is a time chart thereof.

132 to 136 are FFs, and FF 132 inputs signal B indicating the operating state of the snooze switch 22;
The other FFs 134 and 136 input the signal from the output Q of the previous stage. Further, a beam lock signal φ2 is applied to the clock input φ of the FFs 132 to 136.

138.140 is Noah Gate, Noah Gate 138
inputs each signal from the output Q of FF132 and the output Q of FF134 and the clock signal φ2, and outputs the first snooze start signal 5NZI, and the NOR gate 140 outputs the first snooze start signal 5NZI.
A second snooze start signal 5N is generated by inputting each signal from the output Q of FF 34 and the output Q of FF 136 and the clock signal φ2.
Output Z2.

As shown in FIG. 9, the FFs 132 to 136 sequentially switch their output states at the timing of the clock signal φ2 when the snooze switch 22 is operated and the signal B becomes H level.

As a result, a trigger pulse is generated in the first snooze start signal 5NZI, and with a slight delay, a trigger pulse is also generated in the second snooze start signal 5NZ2.

142 is an AND gate into which the signal ALO indicating the alarm-on state and the first snooze start signal are input.

144 is the output signal of the AND gate 142 and the signal ALO
This is a NOR gate that inputs the second trigger signal R3T3, which generates a pulse when it disappears, and outputs the signal 5TOI.

146 is an AND gate which inputs the signal 5TOI and the signal LOADI from the start signal generation circuit 68 and outputs the signal 5TOP.

Normally, the signal 5TOI output by the NOR gate 144 is at H level, so the AND gate 146 is in an open state, and the L level pulse generated in the signal LOADI is directly output from the AND gate 146 as shown in FIG. Generated at signal 5TOP.

The NOR gate 144 determines whether the snooze switch 22 is turned on when the signal ALO is at the H level and a pulse is generated in the first snooze start signal 5NZI (temporary stop due to snooze), or when the signal ALO goes to the L level and the second snooze switch 22 is turned on. When a pulse is generated in the trigger signal R8T3 (the reference switch 20 is turned off), a pulse is generated in the output signal 5TOI, and this pulse is generated in the output of the AND gate 146.

FIG. 10 is a circuit diagram of the snooze counter 64 shown in FIG. 1, and FIG. 11 is a time chart thereof.

Reference numeral 148 denotes a counter that inputs a 0.5 Hz signal to the clock input φ and sets the output Q to H level after counting 4 minutes.

150 is an AND gate into which the signal ALO and the snooze mode signal SNO are input, and 152 is an AND gate into which the output signal of the counter 148 and the output signal of the AND gate 150 are input.

154 and 156 are FFs, both of which input the clock signal φ to the clock input φ, FF154 inputs the output signal of the AND gate 152 to its input, and FF156 inputs the signal from the output Q of FF154. is being entered.

158 is a NOR gate which inputs the signal from the output Q of the FF 154 and the signal from the output Q of the FF 156 and outputs a count-up signal 4M.

A NOR gate 160 inputs the signal R8T2+RST3 and the first snooze start signal 5NZI and applies a signal to the reset input R of the counter 148.

The counter 148 starts counting when it is reset by a trigger pulse generated in the first snooze start signal 5NZI when the snooze switch 22 is turned on.

The H level signal that this counter 148 counts up and outputs is the signal ALO and the snooze mode signal SNO.
This occurs at the output of the AND gate 152, which is open when the signal is at H level.

When the output signal of this AND gate 152 becomes H level, the FFs 154 and 156 sequentially switch their output states at the timing of the clock signal φ1, and during this time, the NOR gate 158
A trigger pulse indicating that the count has increased is generated in the signal 4M outputted by the controller, and the alarm notification is restarted by this trigger pulse.

FIG. 12 shows the snooze mode signal generation circuit 6 shown in FIG.
6, and FIG. 13 is its time chart.

Reference numeral 162 denotes a Nante gate, into which the signal ALO and the second snooze start signal 5NZ2 are input.

Reference numeral 164 denotes an AND gate, which inputs the signal 4M, which generates a pulse when the snooze counter 64 counts up, and the signal R3T2+R8T3 via the inverter 166.

Reference numeral 168 denotes a latch circuit, which consists of Nant gates 170 and 172 into which signals from the Nant gate 162 and AND gate 164 are input.

176 and 178 are FFs, both of which input the clock signal φ2 to the clock input φ, and the FF176 inputs the clock signal φ2 to the inverter 17.
The signal from the latch circuit 168 is input to the FF 178 through the input terminal 4, and the FF 178 inputs the signal from the output Q of the FF 176 to the input terminal, and outputs the snooze mode signal 5NO1SNO from the outputs Q and Q, respectively.

When the alarm is on and the signal ALO is at H level, when the snooze switch 22 is operated and a pulse is generated in the second snooze start signal 5NZ2, this pulse is generated as an L level pulse at the output of the Nantes gate 162,
It is latched by a latch circuit 168.

The output signal of this latch circuit 168 is transmitted to the inverter 174.
is inverted and applied to FF176, and FF176.1
78 sequentially switches the output at the timing of the clock signal φ2, and the snooze mode signals SNO and SNO become H5L level.

In this way, when the snooze mode is entered, alarm notification is temporarily stopped.

After that, when the snooze counter 64 counts up and an L level trigger pulse is generated on the signal 4M, this trigger pulse is generated at the output of the AND gate 164, and in response, the latch circuit 168 changes the output signal to the H level. Make it.

As a result, the FFs 176 and 178 switch their output states, the snooze mode signals SNO and SNO become L and H levels, and alarm notification starts again.

FIG. 14 is a circuit diagram of the start signal generation circuit 68, second snooze operation start detection circuit 70, and repetition signal output circuit 72 shown in FIG.
, is a time chart in M2 mode and M3 mode.

The start signal generation circuit 68 generates a first trigger signal R8T.
2 and an inverter 18 that inverts the count-up signal 4M.
0,182, a Nant gate 184 which inputs its output signal and the signals from the second snooze operation start detection circuit 70 and the repetition signal output circuit 72, an inverter 186 which inverts its output signal, and its output signal LOADI. An FF188 is input to the set human power S, and the input terminal is grounded, and the clock signal φ2 is input to the clock human power φ, and the signal from its output Q is input to the input terminal, and the signal LOAD is input to the input terminal.
1 to the set input S and a clock signal φ2 to the clock input φ, and a Nant gate 192 to which the signal from the output Q of the FF 188 and the signal from the output Q of the FF 190 are input.

Further, the second snooze operation start detection circuit 70 and the repetition signal output circuit 72 are connected to the Nantes gate 194.1, respectively.
The Nantes gate 194 inputs the signal AL○, the signal M3 from the mode switching circuit 53, and the second snooze start signal 5Nz2, and the Nantes gate 196 inputs the signal AL○, the snooze mode signal SNO, and the audio stop signal. A signal BUS2 from the detection circuit 80 is input.

As shown in FIGS. 15 and 16, when the alarm is turned on, the signal ALO becomes H level.

A trigger pulse is generated in the first trigger signal R8T2.

This trigger pulse is generated as an L-level trigger pulse on signal LOAD1 via inverters 180, 186 and Nant gate 184.

The FFs 188 and 190 enter the set state in response to this trigger pulse, and then return to the original state by sequentially switching their output states in synchronization with the clock signal φ2.

During this time, the output of the Nant gate 192 becomes L level,
A pulse having a pulse width equivalent to one period of the clock signal φ2 is generated in the start signal LOAD.

Furthermore, when a pulse is generated in the signal BUS2, which generates a pulse when the generated audio stops, this pulse is generated in the signal LOADI via the Nant gates 196, 184 and the inverter 186, and in the same way as the above operation, is generated in the start signal LOAD. A pulse is also generated. As a result, the voice will be repeatedly announced.

Furthermore, when the snooze switch 22 is turned on, the second
A pulse is generated in the snooze start signal 5NZ2. This pulse is not generated at the output of the Nant gate 194 in the M1, M2 mode, that is, when the signal M3 is at the L level as shown in FIG. 15, and in the M3 mode, that is, as shown in FIG. 16. This occurs at the output of the Nant gate 194 only when the signal M3 is at H level. In this way, even when a pulse is generated in the output signal of the Nant gate 194, a pulse is generated in the start signal LOAD in the same manner as in the above operation. As a result, only in the M3 mode, when the snooze switch 22 is operated, a start signal is generated and audio is output.

Also, when a pulse is generated in the count up signal 4M, a pulse is generated in the signal LOADI, and the start signal L
A pulse is also generated in OAD.

FIG. 17 shows the audio selection counter 74, first snooze operation start detection circuit 76, and skip selection circuit 78 shown in FIG.
FIG. 18 and FIG. 19 are time charts in M1 mode, M2 mode, and M3 mode.

The audio selection counter 74 includes a Nantes gate 198 that inputs signals from the first snooze operation start detection circuit 76 and the skip selection circuit 78, and a shift register 202 that inputs its output to the clock input φ via an inverter 200.
and a latch circuit 2 consisting of NOR gates 208 and 210 which input the clock signal φ1 via the inverter 204 and also input the signal 8 from the final stage of the shift register 202.
06, and a NOR gate 214 which inputs its output signal via an inverter 212 and inputs signals R8T2+R8T3 to apply a signal to the reset manual R of the shift register 202.

The first snooze operation start detection circuit 76 is composed of a Nante gate 216 that receives the signal ALO and the first snooze start signal 5NZI.

The skip selection circuit 78 includes an OR gate 218 that inputs the signal M3 and the signal 4M inverted by the inverter 222;
It is composed of a Nantes gate 220 which inputs the signal ALO, the inverted signal M3, and the second snooze start signal 5NZ2.

In the Ml and M2 modes, as shown in Fig. 18,
The signal M3 is kept at the L level, and therefore the output of the OR gate 218 is kept at the aH level. Therefore, even if the snooze counter 64 counts up and a pulse is generated in the signal 4M, this pulse is not applied to the audio selection counter 74.

On the other hand, when the snooze switch 22 is operated in the M1 and M2 modes and the alarm is on, pulses are sequentially generated in the first and second snooze start signals 5NZI and 5NZ2. Both pulses are applied to the Nant gates 216, 2
20 and is applied to the shift register 202 via the Nant gate 198 and the inverter 200.

Therefore, the shift register 202 will continue to advance the count value by two, and the signal 2.4.6 for instructing generation of the snooze pause operation confirmation sound will be substantially skipped.

Therefore, the snooze pause operation confirmation sound is not generated in the M1 and M2 modes.

When the M3 mode is entered, the signal M3 is activated as shown in FIG.
becomes H level, and as a result, Nantes Gate 22
0 output is kept at H level.

Therefore, when the snooze switch 22 is operated, the first snooze start signal 5NZI is applied to the shift register 202 in the same manner as in the operation described above, but the second snooze start signal 5NZ2 is applied to the output of the Nantes gate 220. Therefore, when the snooze switch 22 is operated, the count value of the shift register 202 is advanced by one.

Further, the pulse generated in the signal 4M by counting up the snooze counter 64 is applied to the shift register 202 via the OR gate 218, the Nant gate 198, and the inverter 200.

In this way, when the M3 mode is entered, the shift register 202 is advanced by 1, and the snooze pause operation confirmation sound is also generated when the snooze switch 22 is operated.

Incidentally, when the signal 8 from the final stage of the shift register 202 becomes H level or a pulse is generated in the signal RS T 2 + RS T 3, a pulse is applied to the reset human power R of the shift register 202 via the NOR gate 214 to reset it. do.

When this signal 8 becomes H level, this signal 8 is converted by the latch circuit 206 into a signal 9 which becomes H level at the timing of the clock signal φ□, and is further generated as a signal R1.

FIG. 20 is a circuit diagram of the audio stop detection circuit 8° shown in FIG. 1, and FIG. 21 is a time chart thereof.

226 to 230 are FFs, the clock signal φ2 is applied to the clock input φ, the FF226 inputs the signal BU3 from the BUSY input via the inverter 224, and the FFs 228 and 230 are the FFs of the previous stage. The signal from the output Q of the is input to the input.

232 is an inverter that inverts the signal 9; 234 is an AND gate that inputs the output signal of the inverter 232 and the signal 5TOI and applies the output signal to the reset input R of the FFs 226 to 230;

236 is a NOR gate, which outputs Q and F of FF228.
It inputs each signal from the output Q of F230 and the clock signal φ2, and outputs the signal BUS2.

The FFs 226 to 230 sequentially switch their output states in response to a pulse generated in the signal BU3 indicating the generation state of the audio signal output by the audio signal synthesis device C32.

As a result, a pulse is generated in the output signal BUS2 of the NOR gate 236 when the output of each audio signal is stopped.

FIG. 22 is a circuit diagram of the 1/2 frequency divider 82 shown in FIG. 1, and FIGS. 23 and 24 are time charts in M1, M2 mode, and M3 mode.

238 is FF, and its clock power φ is BUSY.
A signal BU3 is input from the input, and a signal BU2 is output from the output Q.

240 is an AND gate, which inputs the signal 4M that generates a pulse when the snooze counter 64 counts up, and the signal R1 that generates a pulse when the audio generation ends, and
Apply a signal to the reset human power R of F238.

The FF 238 divides the frequency of the signal BU3 into 1/2 and outputs it, and is reset when the snooze counter 64 counts up.

In this embodiment, the voices generated in the M2 and M33 modes are two different types of voices, and the voices A2 and A3 are notified alternately so that they always come first. For this reason,
The signal BU2 is inverted every time a voice is generated, so that the voices A2 and A3 are generated when the signal BU2 is at L level.

FIG. 25 is a circuit diagram of the decoder 84, single voice repeat circuit 86, and multiple voice repeat circuit 88 shown in FIG. 1, and FIGS. 26 to 28 are time charts in M1, M2, and M3 modes, respectively. .

The single voice repeat circuit 86 is connected to the Nantes gates 242-24.
6, each of the Nant gates receives the signal M1, and the Nant gate 242 receives the signal 7, the Nant gate 2
44 is signal 3. The Nant gate 246 receives the signal 5.

The multiple voice repetition circuit 88 is connected to the Nantes gates 248 to 25.
Nandt gate 248 receives signal BU2, Nandt gate 250 receives signal M2 and signal 1, Nandt gate 252 receives signal M3 and signal 1, and Nandt gate 254 receives signal 3. The Nant gate 256 receives the signal 5.

The decoder 84 consists of Nante gates 264 to 268, and the Nante gate 264 is composed of Nante gates 242, 248 to 248.
The Nant gate 266 receives the signal from the Nant gate 242, 244, 248, 254 and the signal 2.6 via the inverter 260.260. is input, and Nantes Gate 268 is Nantes Gate 242.2.
46.248, 256 and inverter 258.
Signals 4 and 6 are input via 262.

The single voice repeat circuit 86 applies the signal 7.3.5 to the decoder only when the signal M1 is at H level, as shown in FIG.

Further, the multiple voice repetition circuit 88 is shown in FIGS. 27 and 28.
As shown in the figure, when the signal BU2 goes to the L level in the M2 and M3 modes, all the outputs of the Nantes gates 248 to 256 go to the H level, regardless of the signal from the audio selection counter 74.
Since the level is maintained, all output signals of the decoder 84 become L level.

A state is reached in which voices A2 and A3 are shown. Therefore, the voice specified by the voice selection counter 74, for example, voice D2.
, D3, etc. are generated, and two different types of voices (for example, A2 and D2, A3 and D3) are alternately and repeatedly generated.

(Effects of the Invention) According to the present invention, it is possible to provide two types of snooze clocks, one with and without a snooze pause operation confirmation sound, using one clock circuit by simply switching an external switch. The cost per IC can be reduced, and it is most suitable for the production of watches, which are becoming increasingly produced in high-mix, low-volume production.

Note that the external switch may be connected on the board at the manufacturing stage, and the same effect can be achieved in this case as well.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the circuit configuration of the main parts of an audio clock with snooze according to an embodiment of the present invention, FIG. 2 is a diagram showing a schematic configuration of the audio clock with snooze according to the embodiment, and FIG. 3 is a circuit diagram of the mode switching circuit shown in Fig. 1, Fig. 4 is a time chart of the signals in Fig. 3, and Fig. 5 is a circuit diagram of the mode switching circuit shown in Fig. 1.
6 and 7 are time charts of the signals in FIG. 5. FIG. 8 is a circuit diagram of the snooze start signal generation circuit shown in FIG. 1. A time chart of the signals in FIG. 8. FIG. 10 is a circuit diagram of the snooze counter shown in FIG. 1. FIG. 11 is a time chart of the signals in FIG. 10. Part 12 is the circuit diagram of the snooze mode signal generation circuit shown in Fig. 1, Fig. 13 is the time chart of the signal in Fig. 12, and Fig. 14 is the start signal generation circuit shown in Fig. 1, and the second snooze operation. A circuit diagram of a start detection circuit and a repetitive signal output circuit. FIGS. 15 and 16 are time charts of the signals in FIG. 14. FIG. 17 is a circuit diagram of the audio selection counter shown in FIG. 1 and the first snooze operation start detection circuit. , a circuit diagram of the skip selection circuit, FIGS. 18 and 19 are time charts of the signals in FIG. 17, FIG. 20 is a circuit diagram of the audio stop detection circuit shown in FIG. 1, and FIG. 21 is a circuit diagram of the audio stop detection circuit shown in FIG. Signal time chart. Figure 22 is a circuit diagram of the 1/2 frequency divider shown in Figure 1. Figure 23 is a circuit diagram of the 1/2 frequency divider shown in Figure 1.
24 and 24 are time charts of the signals in FIG. 22, FIG. 25 is a circuit diagram of the decoder, single voice repetition circuit, and multiple voice repetition circuit shown in FIG. 1, and FIGS. 26 to 28 are the time charts of the signals in FIG. 5 is a time chart of signals in the figure. 2...Clock part, 16...Notification control IC
120... Reference switch, 22... Snooze switch, 24... Ring stop switch, 26.28... Mode selection switch. 30...Audio circuit, 36...Notification circuit. 54... First gate, 58... Operation signal generation circuit, 62... Snooze start signal generation circuit, 64... Snooze counter. 66... Snooze mode signal generation circuit, 68... Start signal generation circuit, 70... Second snooze operation start detection circuit. 72... Repetition signal output circuit, 74... Audio selection counter, 76... First snooze operation start detection circuit, 78...
- Jump selection circuit, 80... Audio stop detection circuit, 82... 1/2 frequency divider, 84... Decoder, 86...
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Claims (1)

[Scope of Claims] A clock unit that generates a reference signal to measure and display the time, a reference switch that turns on and outputs an alarm-on signal when the time from the clock unit reaches a set time, and a ring stopper. a switch; a first gate that allows the alarm-on signal to pass when the ringing stop switch is in a non-sounding state; and an operation signal generation circuit that outputs an operation signal in response to the alarm-on signal from the first gate; a snooze switch; a snooze start signal generation circuit that outputs a first snooze start signal and subsequently a second snooze start signal in response to an on operation of the snooze switch only when the alarm on signal is generated; and the alarm on signal. a snooze counter that counts the reference signal from the clock unit in response to the generation of the first snooze start signal only when the first snooze start signal is generated, and outputs a count-up signal after a certain period of time; a snooze mode signal generation circuit that outputs a snooze mode signal that prevents generation of an operation signal from the operation signal generation circuit from the generation of a snooze start signal until the generation of a count-up signal from the snooze counter; and the alarm-on signal and the count-up signal. a start signal generation circuit that outputs a start signal in response to the generation of the up signal; an audio selection counter that counts up the count up signal from the snooze counter; and a plurality of types of alarm notification audio data stored and configured to generate the start signal. an audio circuit that outputs an audio signal corresponding to the count value of the audio selection counter in response to the above, and stops operation in response to generation of the snooze start signal and disappearance of the operation signal, and is operable only when the operation signal is generated. In the audio clock with snooze function, the alarm circuit includes: a notification circuit that receives an audio signal from the audio circuit and notifies the audio; a mode switching circuit that outputs a switching mode signal by external operation; a first snooze operation start detection circuit that outputs the first snooze start signal as an increment signal to the audio selection counter only when the switching mode signal and the alarm-on signal are generated; a second snooze operation start detection circuit that outputs a start signal to the start signal generation circuit in response to the occurrence of the snooze operation; A voice clock with a snooze function, comprising: an interlace selection circuit that supplies a snooze start signal to the voice selection counter as a step signal.