JPH0244286A - Sound time-piece with snooze - Google Patents

Abstract

PURPOSE:To lower the manufacturing cost of the title time-piece by a providing clock part for generating a reference signal to clock and display a time and an alarm switch turned ON when the time from the clock part becomes a set time to output an alarm ON signal. CONSTITUTION:When an alarm switch 22 becomes an ON state and an alarm ON signal A becomes an H-level, ETs 110, 112 respond to a clock signal phi2 to successively change over the output states thereof and, during this time, an NOR gate 116 responds to the pulse of the first trigger signal RST 2 and the signal ALO outputted through an inverter 126 is set to an H-level by a latch circuit 120. By this method, an alarm informing state is obtained. As mentioned above, two kinds of sound informing patterns can be changed over by one clock circuit only by changing over an external switch and cost per one IC is lowered to make it possible to lower the manufacturing cost of a time-piece.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to an improvement of a watch with a snooze function, and in particular, a watch with a snooze function that can be switched between watches with different notification sound repetition patterns using a single IC. Concerning what has been done.

(Prior Art) In recent years, watches that notify alarms by sound have been commercialized, and among them, a watch that changes the sound each time the snooze operation is performed, such as the clock disclosed in Japanese Patent Publication No. 718997/1983, has been proposed. There is.

(Problems to be Solved by the Invention) As in the conventional example above, there are various forms of notifying sound as a snooze sound, and various forms can be considered.For example, a form of repeatedly notifying only sound A, sound A, There are various forms such as repeating B and alternately notifying the user.

Conventionally, new ICs had to be designed separately for watches with different notification formats, and it is unnecessary to design watches with the same specifications but only different notification formats separately. The purpose of the present invention is to make it possible to switch between a notification format that repeats a single voice and a notification format that alternately repeats multiple voices, thereby standardizing the IC and reducing costs. There is a particular thing.

(Means for Solving the Problems) The audio clock with snooze of the present invention includes a clock section, a reference switch that outputs an alarm-on signal, a ringing stop switch, and a ringing stop switch that allows the alarm-on signal to pass when in a non-sounding state. a first gate, an operation signal generation circuit that outputs an operation signal in response to an alarm-on signal, a snooze switch, a snooze start signal generation circuit that outputs a snooze start signal in response to an on operation of the snooze switch, and a snooze start signal. a snooze counter that counts in response to a signal and outputs a count-up signal; a snooze mode signal generation circuit that outputs a snooze mode signal that prevents generation of an operation signal from the time the snooze signal is generated until the time the count-up signal is generated; and an alarm. A start signal generation circuit that outputs a start signal in response to the generation of an on signal and a count-up signal, an audio selection counter that counts the count-up signal, and a count value of the audio selection counter in response to the generation of the start signal. An audio circuit that outputs an audio signal and an output display signal indicating the audio signal output and stops operation when a snooze start signal is generated or when an operating signal disappears; a notification circuit that inputs an audio signal and notifies the audio; and one display output signal. A sound clock with snooze function, comprising: a sound stop detection circuit for detecting disappearance of the sound; and a repeat signal output circuit for causing a start signal generation circuit to output a start signal in response to the detection signal.

A mode switching circuit that outputs a first or second mode signal by external operation, and a 172 frequency divider that divides the output display signal by 172 and whose divided output is cleared every time a count-up signal is generated from the snooze counter. and.

A single voice repeating circuit outputs a voice selection signal corresponding to the count output signal only when the first mode signal is generated, and a single voice repeating circuit outputs the voice selection signal corresponding to the count output signal only when the second mode signal is generated. A plurality of voice repetition circuits that change a voice selection signal in response to a change in a frequency division output when a count output signal is generated.

It consists of

(Function) When the first mode signal is generated, the single voice repetition circuit outputs a voice selection signal corresponding to the signal from the voice selection counter.

Therefore, a single voice selection signal is output from the single voice repetition circuit until the voice selection counter is incremented.

On the other hand, when the second mode signal is generated, a voice selection signal corresponding to the output signal of the voice selection counter is output from the multiple voice repetition circuit in place of the single voice repetition circuit.

This voice selection signal also instructs a single voice until the voice selection counter is incremented, but when the signal from the 172 frequency divider disappears, the voice selection signal changes and instructs a different voice, When the signal from the 1/2 frequency divider is generated, it is returned to the original state again and this process is repeated.

The sounds notified by the above operation are as shown in Table 1, for example.

table ! That is, when the first mode signal is generated, a single voice, for example, voice A1, is repeatedly generated, and when the second mode signal is generated, a plurality of voices, for example, voices A2, 82 . Alternatively, sounds A3 and 83 are repeatedly generated alternately.

(Example) The present invention will be described in detail below based on the drawings.

FIG. 1 is a block diagram showing a circuit configuration of a main part of an audio clock with snooze according to an embodiment of the present invention, and FIG. 2 is a diagram showing a schematic configuration of an audio clock with snooze according to this embodiment.

In FIG. 2, 2 is a clock section, which includes a clock IC 6 that generates a reference signal using a crystal oscillator 4, synthesizes 17 motor drive signals from this reference signal, and a motor 8 that is driven by the motor drive signal. It has a wheel train 10 driven by a motor 8, and a display section 12 that displays the time using a pointer driven by the wheel train 10.

Note that the clock section 2 in this embodiment includes a frequency divider 14 that divides the frequency of one pulse signal for driving the motor by 172.

16 is an IC for notification control which is a main part of the present invention; iJ;
Power supply for VDD and VSS input, RC oscillation circuit 18 for oSC1 to ○SC3 manual power, and reference switch 20 for AL11 input that turns on when the time of clock section 2 reaches the set value.
, the SNZ input has a snooze switch 22. The ALI2 manual has a ring stop switch 24, and the MODI and MOD2 manual have a mode changeover switch 26.28, 0.51 for switching between generation and non-generation of the snooze pause confirmation sound (the clock part 2 is connected to the z input, respectively). ing.

Further, the powo output of this notification control IC 16 outputs an operation signal for activating the notification circuit, which will be described later, and the ■0 to ■2 outputs are signals for selecting and instructing the audio signal to be output from the audio circuit, which will be described later. is output, and stop and start signals for stopping or starting the output of the audio signal are output from the 5TOP and LOAD outputs, respectively.

Reference numeral 30 denotes an audio circuit, which includes an audio signal synthesis IC 32.

A crystal oscillator 34 for obtaining a reference signal is connected to the audio signal synthesis IC 32, and
o-12 Human power, RESET and shoulder input notification control IC
16 ■ 0 ~ engineering 2 output.

5TOP and LOAD outputs are connected respectively, and v
A power supply is connected to the oo and vss inputs.

Also, an audio signal is output from the AVO output of this audio signal synthesis IC 32, and a display output signal indicating that an audio signal is being output is output from the BUSY output, and is applied to the BUSY input of the notification control IC 16. Ru.

This audio signal synthesis IC 32 has a plurality of voices A1 to D1, A2 to E2, . Alarm notification audio data of A3 to H3 is stored, and an audio signal is synthesized and output based on the audio data corresponding to signals inputted by 10 to 12 human inputs.

36 is a notification circuit, which includes a notification IC 38 that inputs the audio signal from the AVO output of the audio signal synthesis IC to the INA input and drives the speaker 40 connected to the 0UTA and 0UTB outputs, and the VDD of this notification IC 38. It consists of a power-on circuit 42 which is provided between the input and the power source and is made up of a transistor whose conduction or non-conduction is determined by a power-on signal from the powo output of the notification control IC 16.

Next, an outline of the operation of the audio clock with snooze configured as described above will be explained.

In this embodiment, two mote selector switches 26.
28 is provided, and depending on its on/off state, Ml
, M2, and M3 modes can be selected.

For example, in the M1 mode, when the reference switch 20 is turned on while the ring stop switch 24 is in the alarm on state, an operation signal is output from the LOAD output of the notification control IC 16, and at the same time, the lo-I2 A code signal corresponding to voice A1 shown in Table I is output from the output.

Further, the audio signal synthesis C32 outputs an audio signal representing the audio A1 from the AVO output in response to the signals inputted to the ST input and the 0 to 12 manual inputs.

The notification equipment C38 that inputs this audio signal to the INA input inputs it because the power-on circuit 42 becomes conductive due to the operation signal output from the powo output of the notification control IC 16 at the time of starting notification, and is connected to the power source. The speaker 40 is driven based on the audio signal to generate audio A1.

When the voice A1 is generated in this way, the notification control IC1
A stop signal is output from the 5TOP output of No. 6, and the audio signal synthesis IC 32 which inputs this to the RESET input is reset and stops outputting the audio signal.

Further, following this voice A1, voice A1 is generated again in the same manner as the above operation, and this is repeated until the snooze switch 22 is turned on. When the snooze switch 22 is turned on, the voice notification is temporarily stopped. . The subsequent operations are similar to those described above, and the order of the sounds generated is as shown in Table I.

In the case of the M2 mode, the operation is almost the same as that described above, but the only difference is that the voice to be notified consists of different types of voices as shown in Table 2, and these are alternately notified.

Furthermore, in the case of the M3 mode, a plurality of different sounds are alternately and repeatedly announced as in the case of the M2 mode, and further, when the snooze switch 22 is operated, the snooze pause operation confirmation sound is notified.

Next, the detailed circuit configuration of the notification control IC 16 shown in FIG. 2 will be explained using FIG. 1.

50 is an oscillation circuit connected to the RC oscillation circuit 18 via 08CI to 05C3, and outputs a reference signal.

52 is a frequency dividing circuit which divides the frequency of the reference signal and outputs the clock signal φ1. Outputs φ2.

53 is a mode switching circuit which outputs signals M1, M2 . Output M3.

Reference numeral 54 designates a first gate consisting of an AND gate which inverts and inputs the signals from the reference switch 20 and the ring stop switch 24 through the ALII input and the ALI2 input, and outputs an alarm-on signal.

56 is a chattering prevention circuit that inputs the alarm-on signal from the first gate 54.

58 is an operation signal generation circuit, and when the alarm-on signal A from the first gate 54 is inputted via the chattering prevention circuit 56, the operation signal pow is generated.

Output.

60 is a chattering prevention circuit that inputs the signal from the snooze switch 22 via the SNZ input.

62 is a snooze start signal generation circuit, and when an alarm on signal is generated and the alarm is on,
Snooze switch 2 via chattering prevention circuit 60
When the signal B from 2 is input, the first and second snooze start signals 5NZI, 5N are activated at the timing of the clock signal φ2.
This is to apply 8 forces to Z2 in sequence.

64 is a snooze counter, and a snooze switch 22
The first snooze start signal 5NZ generated when is operated.
In response to I, the 0 and 5 electric signals input from the 0.5 Hz input are counted, and a count-up signal 4M is output after a certain period of time.

66 is a snooze mode signal generation circuit, which outputs a snooze mode signal 5NO1SNO in response to the second snooze start signal 5NZ2 when the alarm is on, and stops outputting when the snooze counter 64 counts up. .

While this snooze mode signal SNO is being generated, the operation signal generation circuit 58 is prevented from outputting the operation signal powo.

Reference numeral 68 is a start signal generation circuit, which is used to generate signals at the time of starting alarm notification, when resuming alarm notification after snooze, and the second signal generation circuit described later.
When the signals from the snooze operation start detection circuit and the repeat signal output circuit are input.

Each outputs a start signal LOAD.

70 is a second snooze operation start detection circuit, which generates a start signal LOAD from the start signal generation circuit 68 in response to the second snooze start signal 5NZ2 generated when the snooze switch 22 is operated only in the M3 mode. This is what outputs it.

Reference numeral 72 denotes a repeating signal output circuit, which causes the repeating start signal generating circuit 68 to output a start signal in response to a signal BUS2 outputted from a sound stop detection circuit (to be described later) every time sound generation stops when the alarm is on. be.

74 is a voice selection counter, 576 is a first snooze operation start detection circuit, and 78 is an interlace selection circuit. In the Ml and M2 modes, the audio selection counter 74 is set to two in succession by the first and second snooze start signals 5NZI and 5NZ2 inputted via the first snooze operation start detection circuit 76 and the skip selection circuit 78. Advance the count step by step.

In the case of the M3 mode, the first snooze start signal 5NZI from the first snooze operation start detection circuit 76 and the signal 4M generated when the snooze counter 64 from the skip selection circuit 78 counts up increase the count to 1. You can proceed step by step.

80 is an audio stop detection circuit, which includes an audio signal synthesis IC3.
Based on the display output signal BU3 indicating the output state of the audio signal from the BUSY output of No. 2, it detects that the generation of audio has stopped and outputs the detection signal BUS2.

82 is a 172 frequency divider, which divides the signal BU3 indicating the output state of the audio signal output from the audio synthesis IC 32 by 1/2.
Divide the frequency, M2. In the M3 mode, a signal BU2 is output for distinguishing the sounds A2 and A3 from the next sound.

84 is a decoder, 86 is a single voice repetition circuit, and 88 is a multiple voice repetition circuit. The single voice repetition circuit 84 is
The signal from the voice selection counter 74 is applied to the decoder 84 when the signal M1 is generated, and the multiple voice repeat circuit 88 applies the signal from the voice selection counter 74 to the decoder 84 when the signal BU2 is generated while the signal M2 or M3 is generated. The signal from 74 is changed into a signal indicating a predetermined voice and is applied to decoder 84.

Next, an outline of the operation of the notification control IC 16 having the above configuration will be explained.

When the set alarm time comes and the reference switch 20 is turned on, the operation signal generation circuit 58 outputs a signal ALO and an operation signal POW○ indicating that the alarm is on.

Start signal generation circuit 68 outputs start signal LOAD in response to trigger signal R5T2 output from operation signal generation circuit 58 when signal ALO is generated.

As a result, signals are applied from the powo output and the LOAD output to the audio circuit 3o and the notification circuit 36, respectively, and audio notification starts.

When the M1 mode is selected, the signal output by the voice selection counter 74 is applied to the decoder via the single voice repetition circuit 86, and when the M2 and M3 modes are selected, the signal output from the voice selection counter 74 is applied to the decoder through the single voice repetition circuit 86. It is applied to the decoder via circuit 88.

In the Ml and M2 modes, the audio selection counter 74 outputs the first and second snooze start signals 5NZI and 5NZ2 output from the snooze start signal generation circuit 62 when the snooze switch 22 is operated to the snooze operation start detection circuit 7.
6 is input via the skip selection circuit 78, and the count value is incremented by two. As a result, signals 2, 4 and 6 for generating the snooze pause operation confirmation sound are skipped, and the snooze pause operation confirmation sound is not generated.

In addition, in the case of M3 mode, instead of the second snooze start signal 5NZ2, the signal TV generated when the snooze counter 64 counts up is sent to the skip selection circuit 7.
8 to the audio selection counter 74, and as a result, the audio selection counter 74 is incremented by 1 when the snooze counter 64 counts up and when the snooze switch 22 is operated. For this reason, the signal 2.4 for generating the snooze pause operation confirmation sound.
6 is output when the snooze switch 22 is operated, so that this snooze pause operation confirmation sound is generated in the M3 mode.

On the other hand, when in Ml or M2 mode, the snooze switch 22
Even if the second snooze start signal 5NZ2 is operated, the second snooze start signal 5NZ2
Application to the start signal generation circuit 68 is blocked by the second snooze operation start detection circuit 70, but in the M3 mode, it is applied to the start signal generation circuit 68 via the second snooze operation start detection circuit 70. Therefore, only in the M3 mode, the start signal LOAD is generated even when the snooze switch 22 is operated.

Note that the audio signal synthesis IC 32 in this embodiment needs to be reset once after outputting the audio signal and before outputting the primary audio signal, so the snooze function is activated every time the audio signal corresponding to each audio is generated. The stop signal 5TOP synthesized by the start signal generation circuit 62 is output, and the circuit is reset.

Furthermore, since it becomes necessary to apply the start signal LOAD every time each audio signal is output, this start signal LOAD is also generated every time each audio signal is output.

When the reference switch 20 or the ring stop switch 24 is turned off, the generation of the signal ALO indicating alarm on stops, the generation of the operation signal powo and the start signal LOAD also stops, and the notification ends.

Next, the detailed circuit configuration and operation of each of the above circuits will be explained.

FIG. 3 is a circuit diagram of the mode switching circuit 53 shown in FIG. 1, and FIG. 4 is a time chart thereof.

100 to 104 are Noah gates, each with MODl
, signals E and F from MOD2 manual input, signal E and signal F inverted by inverter 108, and signal E and signal F inverted by inverter 106 are input.

In this mode switching circuit 53, the signal E.

Depending on the state of F, signals M1, M2, and M3 indicating Ml, M2, and M3 modes respectively go to H level, and
The mode corresponding to the signal at the level is set.

FIG. 5 is a circuit diagram of the operation signal generation circuit 58 shown in FIG. 1, and FIGS. 6 and 7 are time charts in M1, M2 mode, and M3 mode.

110 and 112 are flip-flops (hereinafter abbreviated as "FF"), FFll0 inputs the alarm-on signal A to its input, and FF112 inputs the signal from the output Q of FFll0 to its input.

Furthermore, the clock signal φ2 is inputted to the clock input φ.

114.116 is Noah Gate, Noah Gate 114
inputs the signal from the output Q of FF112, the signal from the output of FF112, and the clock signal φ2, and outputs the second trigger signal R8T3, and the NOR gate 116 outputs the second trigger signal R8T3.
The signal from the output Q of l0, the signal from the output Q of FF112, and the clock signal φ2 are input to generate the first trigger signal RS.
Output T2.

118 is an OR gate, and the first and second trigger signals R
ST2. I am inputting R3T3.

Reference numeral 120 denotes a latch circuit composed of NOR gates 122 and 124 which input the second and first trigger signals R8T3 and RST2, respectively.

128 is a Nant gate, into which the signal SNO from the snooze mode signal generation circuit 66 and the signal from the latch circuit 120 are inputted via the inverter 126.

130 is an AND gate which inputs the output signal of the Nandt gate 128 and the signal BU3 from the BUSY input and outputs the operation signal POW○.

When the reference switch 22 is turned on and the alarm-on signal A becomes H level, the FFll0°112 sequentially switches its output state in response to the clock signal φ2, and during this time the NOR gate 116 pulses the first trigger signal R5T2. to occur.

In response to the pulse of the first trigger signal R5T2, the latch circuit 120 sets the signal ALO outputted via the inverter 126 to H level. This causes an alarm notification state as described above.

Furthermore, when this signal ALO goes to H level, the output of Nant gate 128 goes to L level while signal SNO is at H level, so AND gate 130 becomes closed, and the operation signal powo goes to L level and operates. become a state.

As shown in FIG. 6, in the M1 and M2 modes, the snooze state occurs, and when the signal SN○ goes to the L level, the operation signal powo goes to the H level and the notification is temporarily stopped, and as shown in FIG. mode, the snooze pause operation confirmation sound C3, E3.
The operation signal powo is kept at the L level until G3 is generated and the signal BU3 goes to the H level.

FIG. 8 is a circuit diagram of the snooze start signal generating circuit 62 shown in FIG. 1, and FIG. 9 is a time chart thereof.

132 to 136 are FFs, and FF 132 inputs signal B indicating the operating state of the snooze switch 22;
The other FFs 134 and 136 input the signal from the output Q of the previous stage. Also, this FF132. ~136
A clock signal φ2 is applied to the clock input φ.

138.140 is Noah Gate, Noah Gate 138
inputs each signal from the output Q of FF132 and the output Q of FF134 and the clock signal φ2, and outputs the first snooze start signal 5NZI, and the NOR gate 140 outputs the first snooze start signal 5NZI.
A second snooze start signal 5N is generated by inputting each signal from the output Q of FF 34 and the output Q of FF 136 and the clock signal φ2.
Output Z2.

As shown in FIG. 9, the FFs 132 to 136 sequentially switch their output states at the timing of the clock signal φ2 when the snooze switch 22 is operated and the signal B becomes H level.

As a result, a trigger pulse is generated in the first snooze start signal 5NZI, and with a slight delay, a trigger pulse is also generated in the second snooze start signal 5NZ2.

Reference numeral 142 denotes an AND gate into which the signal AL○ indicating the alarm-on state and the first snooze start signal are input.

144 is the output signal of the AND gate 142 and the signal ΔLO
Second Trigger No. 3 R3T3 that generates a pulse when it disappears
This is a NOR gate that inputs the signal 5TOL and outputs the signal 5TOL.

146 is an AND gate which inputs the signal 5TOI and the signal LOAD1 from the start signal generation circuit 68 and outputs the signal 5TOP.

Normally, the signal 5TOI output by the NOR gate 144 is at H level, so the AND gate 146 is in an open state, and the L level pulse generated in the signal LOAD1 is directly output from the AND gate 146 as shown in FIG. Generated at signal 5TOP.

The NOR gate 144 determines whether the snooze switch 22 is turned on when the signal AL○ is at the H level and a pulse is generated in the first snooze start signal 5NZI (temporary stop due to snooze), or when the signal ALO is at the L level and the second snooze switch 22 is turned on. When a pulse occurs in the trigger signal RST3 (as a guideline switch 2
0 turns off), it generates a pulse on its output signal 5TOI, which pulse is generated at the output of AND gate 146.

FIG. 10 is a circuit diagram of the snooze counter 64 shown in FIG. 1, and FIG. 11 is a time chart thereof.

148 is a counter that inputs the signals of Q and 51 (z) to the clock input φ and sets the output Q to the H level after counting 4 minutes.

150 is an AND gate into which the signal ALO and the snooze mode signal SNO are input, and 152 is an AND gate into which the output signal of the counter 148 and the output signal of the AND gate 150 are input.

154 and 156 are FFs, both of which input the clock signal φ1 to the clock input φ, FF154 inputs the output signal of the AND gate 152 to its input, and FF156 inputs the signal from the output Q of FF154 to its input. I am typing.

158 is a NOR gate which inputs the signal from the output Q of the FF 154 and the signal from the output Q of the FF 156 and outputs a count-up signal 4M.

160 is a NOR gate which inputs the signal R8T2+RST3 and the first snooze start signal 5NZL and applies a signal to the reset input R of the counter 148.

The counter 148 starts counting when it is reset by a trigger pulse generated in the first snooze start signal 5NZI when the snooze switch 22 is turned on.

The H level signal that this counter 148 counts up and outputs is the signal 1 AL○ and the snooze mode signal SN.
AND gate 152 that is open when O is at H level
occurs in the output of

When the output signal of this AND gate 152 becomes H level, the FFs 154 and 156 sequentially switch their output states at the timing of the clock signal φ, and during this time, the NOR gate 158
A trigger pulse indicating that the count has increased is generated in the signal 4M output by 5, and the alarm notification is restarted by this trigger pulse.

FIG. 12 shows the snooze mode signal generation circuit 6 shown in FIG.
6, and FIG. 13 is its time chart.

Reference numeral 162 denotes a Nante gate, into which the signal ALO and the second snooze start signal 5NZ2 are input.

Reference numeral 164 denotes an AND gate, which inputs the signal 4M, which generates a pulse when the snooze counter 64 counts up, and the signal R3T2+R5T3 via the inverter 166.

Reference numeral 168 denotes a latch circuit, which consists of Nant gates 170 and 172 into which signals from the Nant gate 162 and AND gate 164 are input.

176 and 178 are FFs, both of which input the clock signal φ2 to the clock input φ, and the FF176 inputs the clock signal φ2 to the inverter 17.
The signal from the latch circuit 168 is inputted to the FF 178 via the input terminal 4, and the signal from the output Q of the FF 176 is inputted to the FF 178, and the snooze mode signal 5HO5SNO is outputted from the outputs Q and Q, respectively.

When the alarm is on and the snooze switch 22 is operated when the signal ALO is at H level, a pulse is generated in the second snooze start signal 5NZ2.

This pulse is used as an L level pulse at the Nant gate 16.
2 and is latched by the latch circuit 168.

The output signal of this latch circuit 168 is transmitted to the inverter 174.
is inverted and applied to FF176, and FF176.1
78 sequentially switches the output at the timing of the clock signal φ2, and the snooze mode signals SNO and SNO become H and L levels.

In this way, when the snooze mode is entered, alarm notification is temporarily stopped.

After that, when the snooze counter 64 counts up and a low-level trigger pulse is generated on the signal 〒V, this trigger pulse is generated at the output of the AND gate 164, and in response, the latch circuit 168 changes the output signal to high. level.

As a result, the FFs 176 and 178 switch their output states, the snooze mode signals SNO and SNO become L and H levels, and alarm notification starts again.

FIG. 14 is a circuit diagram of the start signal generation circuit 68, second snooze operation start detection circuit 70, and repetition signal output circuit 72 shown in FIG.
, is a time chart in M2 mode and M3 mode.

The start signal generation circuit 68 generates a first trigger signal R8T.
2 and an inverter 18 that inverts the count amplifier signal 4M.
0,182, a Nantes gate 184 which inputs its output signal and signals from the second snooze operation start detection circuit 70 and the repetitive signal output circuit 72, an inverter 186 which inverts its output signal, and its output signal LOADl. FF188 is input to the set input S, and the input terminal is grounded, and the clock signal φ2 is input to the clock input φ, and the signal from its output Q is input to the input terminal, and the signal LOAD is input to the input terminal.
It is composed of an FF 190 which inputs 1 to the set input S and a tarlock signal φ2 to the clock input φ, and a Nant gate 192 which inputs the signal from the output Q of the FF 188 and the signal from the output Q of the FF 190.

Further, the second snooze operation start detection circuit 70 and the repetition signal output circuit 72 are respectively connected to the Nante gate], 94.
196, the Nantes gate 194 inputs the signal ALO, the signal M3 from the mode switching circuit 53, and the second snooze start signal 5NZ2, and the Nantes gate 196
inputs the signal ALO, the snooze mode signal SNO, and the signal BUS2 from the audio stop detection circuit 80.

As shown in FIGS. 15 and 16, when the alarm is turned on, the signal ALO becomes H level.

A trigger pulse is generated in the first trigger signal R8T2.

This trigger pulse is generated as an L-level trigger pulse on signal LOADI via inverters 180, 186 and Nant gate 184.

The FFs 188 and 190 enter the set state 7S in response to this trigger pulse, and then sequentially switch their output states in synchronization with the clock signal φ2 to return to the original state by one.

During this time, the output of the Nant gate 192 becomes L level,
A pulse having a pulse width equivalent to one period of the clock signal φ2 is generated in the start signal LOAD.

Furthermore, when a pulse is generated in the signal BUS2, which generates a pulse when the generated audio stops, this pulse is generated in the signal LOADI via the Nant gates 196, 184 and the inverter 186, and in the same way as the above operation, is generated in the start signal LOAD. A pulse is also generated. As a result, the voice will be repeatedly announced.

Furthermore, when the snooze switch 22 is turned on, the second
A pulse is generated in the snooze start signal 5NZ2. This pulse is not generated at the output of the Nant gate 194 in the Ml1M2 mode, that is, when the signal M3 is at the L level as shown in FIG. This occurs at the output of the Nant gate 194 only when M3 is at H level. In this way, even when a pulse is generated in the output signal of the Nant gate 194, a pulse is generated in the start signal LOAD in the same manner as in the above operation. As a result, only in the M3 mode, when the snooze switch 22 is operated, a start signal is generated and audio is output.

Also, when a pulse is generated in the count up signal 4M, a pulse is generated in the signal LOAD1, and the start signal L
A pulse is also generated in OAD.

FIG. 17 shows the audio selection counter 74, first snooze operation start detection circuit 76, and skip selection circuit 78 shown in FIG.
FIG. 18 and FIG. 19 are time charts in M11M2 mode and M3 mode.

The audio selection counter 74 includes a Nantes gate 198 that inputs signals from the first snooze operation start detection circuit 76 and the skip selection circuit 78, and a shift register 202 that inputs its output to the clock input φ via an inverter 200.
and a clock signal φ through an inverter 204, and a latch circuit 2 consisting of NOR gates 208 and 210 which also inputs the signal 8 from the final stage of the shift register 202.
06, and a NOR gate 214 which inputs its output signal via an inverter 212 and inputs the signals RST 2 + R and S T 3 to apply a signal to the reset input R of the shift register 202.

The first snooze operation start detection circuit 76 is composed of a Nante gate 216 that receives the signal ALO and the first snooze start signal 5NZI.

The skip selection circuit 78 includes an OR gate 218 that inputs the signal M3 and the signal 4M inverted by the inverter 222;
It is composed of a Nantes gate 220 which inputs the signal ALO, the inverted signal M3, and the second snooze start signal 5NZ2.

In the Ml and M2 modes, as shown in Fig. 18,
Signal M3 is kept at L level, so the output of OR gate 218 is kept at H level. Therefore, even if the snooze counter 64 counts up and a pulse is generated in the signal 4M, this pulse is not applied to the audio selection counter 74.

On the other hand, when the snooze switch 22 is operated in this Ml1M2 mode and the alarm is on, pulses are generated in the first and second snooze start signals 5NZI and 5NZ2 in sequence. Both pulses are applied to the Nant gates 216, 2
20 and is applied to the shift register 202 via the Nant gate 198 and the inverter 200.

For this reason.

The shift register 202 will continue to advance the count value by two, and the signal 2.4.6 for instructing generation of the snooze pause operation confirmation sound will be substantially skipped.

Therefore, the snooze pause operation confirmation sound is not generated in the M1 and M2 modes.

When the M3 mode is entered, the signal M3 is activated as shown in FIG.
becomes H level, and as a result, Nantes Gate 22
0 output is kept at H level.

Therefore, when the snooze switch 22 is operated, the first snooze start signal 5NZI is applied to the shift register 202 in the same manner as in the operation described above, but the second snooze start signal 5NZ2 is applied to the output of the Nantes gate 220. Does not occur. Therefore, when the snooze switch 22 is operated, the count value of the shift register 202 is advanced by one.

Further, the pulse generated in the signal 4M by counting up the snooze counter 64 is applied to the shift register 202 via the OR gate 218, the Nant gate 198, and the inverter 200.

In this way, when the M3 mode is entered, the shift register 202 is advanced by l, and the snooze pause operation confirmation sound is also generated when the snooze switch 22 is operated.

Note that when the signal 8 from the final stage of the shift register 202 becomes H level or a pulse is generated in the signal RS T 2 + RS T 3, a pulse is applied to the reset input R of the shift register 202 via the NOR gate 214 to reset it. do.

When this signal 8 becomes H level, this signal 8 is converted by the launch circuit 206 into a signal 9 which becomes H level at the timing of clock signal φ1, and is further generated as signal R1.

FIG. 20 is a circuit diagram of the audio stop detection circuit 80 shown in FIG. 1, and FIG. 21 is a time chart thereof.

226 to 230 are FFs, the clock signal φ2 is applied to the clock input φ, the FF 226 inputs the signal BU3 from the BUSY input through the inverter 224, and the FFs 228 and 230 are the FFs in the previous stage. The signal from the output Q of the is input to the input.

232 is an inverter that inverts the signal 9; 234 is an AND gate that receives the output signal of the inverter 232 and the signal 5TOI and applies the output signal to the reset input R of the FFs 226 to 230;

236 is a NOR gate, which outputs Q and F of FF228.
It inputs each signal from the output Q of F230 and the clock signal φ2, and outputs the signal BUS2.

The FFs 226 to 230 sequentially switch their output states in response to a pulse generated in the signal BU3 indicating the generation state of the audio signal output by the audio signal synthesis IC 32.

As a result, the output signal of the NOR gate 236 +3LIS2
A pulse is generated when output of each audio signal is stopped.

FIG. 22 is a circuit diagram of the 1/2 frequency divider 82 shown in FIG. 1, and FIGS. 23 and 24 are time charts in M1, M2 mode, and M3 mode.

238 is FF, and its clock power φ is BUSY.
The signal BU3 from the input is input.

A signal BU2 is output from the output Q.

240 is an AND gate, which inputs the signal 4M that generates a pulse when the snooze counter 64 counts up, and the signal R1 that generates a pulse when the audio generation ends, and
Apply a signal to the reset human power R of F238.

The FF 238 divides the frequency of the signal BU3 into 1/2 and outputs it, and is reset when the snooze counter 64 counts up.

In this embodiment, the voices generated in the M2 and M33 modes are two different types of voices, and the voices A2 and A3 are notified alternately so that they always come first. For this reason,
The signal BU2 is inverted every time a voice is generated, so that the voices A2 and A3 are generated when the signal BU2 is at L level.

FIG. 25 shows the decoder 84, single voice repeat circuit 86, and the single voice repeat circuit 86 shown in FIG. 26 to 28 are circuit diagrams of the multiple voice repetition circuit 88, respectively.

M2. It is a time chart in M3 mode.

The single voice repeat circuit 86 is connected to the Nantes gates 242-24.
6, each of the Nant gates receives the signal M1, and the Nant gate 242 receives the signal 7, the Nant gate 2
44 inputs the signal 3, and the Nant gate 246 inputs the signal 5.

The multiple voice repetition circuit 88 is connected to the Nantes gates 248 to 25.
6, each of the Nant's gates receives the signal BU2, the Nant's gate 248 receives the signal 7, the Nant's gate 250 receives the signal M2 and the signal 1, and the Nant's gate 252 receives the signal M3 and the signal 1. Nantes gate 254 receives signal 3. The Nant gate 256 receives the signal 5.

The decoder 84 consists of Nante gates 264 to 268, and the Nante gate 264 is composed of Nante gates 242, 248 to 248.
The Nantes gate 266 inputs the signal from the Nantes gate 242, 244, 248, 254 and the signals 2, 2 through the inverter 258, 260, and the Nantes gate 266 inputs the signal from the Nantes gate 242, 244, 248, 254 and the signal 2, 6 through the inverter 260, 262. Nantes Gate 268 is Nantes Gate 242.2.
46.248, 256 and inverter 258.
Signals 4 and 6 are input via 262.

As shown in FIG. 26, the single voice repeat circuit 86 applies the signal 7°3.5 to the decoder only when the signal M1 is at H level.

Further, the multiple voice repetition circuit 88 is shown in FIGS. 27 and 28.
As shown in the figure, when the signal BU2 goes to the L level in the M2 and M3 modes, the outputs of the Nante gates 248 to 256 go to the H level regardless of the signal from the audio selection counter 74.
Since the level is maintained, all output signals of the decoder 84 become L level.

A state is reached in which voices A2 and A3 are shown. Therefore, the voice specified by the voice selection counter 74, for example, voice D2.
．． Voice A2, which is different from D3, etc. A3 is generated, and two different types of voices (eg, A2 and D2, A3 and D3) are alternately and repeatedly generated.

(Effects of the Invention) According to the present invention, it is possible to switch between two types of audio notification formats with one clock circuit by simply switching an external switch, and the cost per IC can be reduced.
It is most suitable for the production of watches, which is becoming a high-mix, low-volume production.

Note that the external switch may be connected on the board at the manufacturing stage, and the same effect can be achieved in this case as well.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the circuit configuration of the main parts of an audio clock with snooze according to an embodiment of the present invention, FIG. 2 is a diagram showing a schematic configuration of the audio clock with snooze according to the embodiment, and FIG. 3 1 is a circuit diagram of the mode switching circuit shown in FIG. 1, and FIG. 4 is a time chart of signals in FIG. 3. FIG. 5 is a circuit diagram of the operation signal generation circuit shown in FIG. 1. 6 and 7 are time charts of the signals in FIG. 5, FIG. 8 is a circuit diagram of the snooze start signal generation circuit shown in FIG. 1, FIG. 9 is a time chart of the signals in FIG. 8, and FIG.
Figure 11 is a circuit diagram of the snooze counter shown in Figure 1. Figure 11 is a time chart of the signal in Figure 10. Figure 12 is a circuit diagram of the snooze mode signal generation circuit shown in Figure 1. Signal time chart. Figure 14 shows the start signal generation circuit shown in Figure 1. A circuit diagram of a second snooze operation start detection circuit and a repetitive signal output circuit, and FIGS. 15 and 16 are time charts of signals in FIG. 14. Figure 17 is a circuit diagram of the audio selection counter, first snooze operation start detection circuit, and skip selection circuit shown in Figure 1@; Figures 18 and 19 are time charts of the signals in Figure 17; Figure 20 is A circuit diagram of the audio stop detection circuit shown in FIG. 1, FIG. 21 is a time chart of the signal in FIG. 20, FIG. 22 is a circuit diagram of the 172 frequency divider shown in FIG.
The figure and FIG. 24 are time charts of the signals in FIG. 22. FIG. 25 is a circuit diagram of the decoder, single voice repetition circuit, and multiple voice repetition circuit shown in FIG. 1, and FIGS. 26 to 28 are time charts of signals in FIG. 25. 2...Clock part, 16...Notification control plate C. 2o...Standard switch, 22...Snooze switch, 24...Sound stop switch, 26.28...Mode selection switch. 30...Audio circuit, 36...Notification circuit, 54...
...first gate, 58...operation signal generation circuit, 62
. . . Snooze start signal generation circuit, 64 . . . Snooze counter. 66... Snooze mode signal generation circuit, 68... Start signal generation circuit, 70... Second snooze operation start detection circuit, 72...
Repetitive signal output circuit, 74... Audio selection counter, 76... First snooze operation start detection circuit, 78...
- Jump selection circuit. 80...Audio stop detection circuit, 82...1/2 frequency divider, 84...Decoder, 86...
Single voice repetition circuit, 88...Multiple voice repetition circuit. The 9th ward has returned to death. Ml Shizuka M2 Sade No. 280 Shu Ako Eko M3 mode

Claims (1)

[Scope of Claims] A clock unit that generates a reference signal to measure and display the time, a reference switch that turns on and outputs an alarm-on signal when the time from the clock unit reaches a set time, and a ring stopper. a switch; a first gate that allows the alarm-on signal to pass when the ringing stop switch is in a non-sounding state; and an operation signal generation circuit that outputs an operation signal in response to the alarm-on signal from the first gate; a snooze switch; a snooze start signal generation circuit that outputs a snooze start signal in response to an on operation of the snooze switch only when the alarm on signal is generated; a snooze counter that counts a reference signal from the clock section and outputs a count-up signal after a certain period of time; a snooze mode signal generation circuit that outputs a snooze mode signal that prevents generation of an operation signal from the operation signal generation circuit; a start signal generation circuit that outputs a start signal in response to the generation of the alarm-on signal and the count-up signal; an audio selection counter that counts up the count-up signal from the snooze counter; and an audio selection counter that stores a plurality of types of alarm notification audio data and generates an audio signal and audio corresponding to the count value of the audio selection counter in response to generation of the start signal. an audio circuit that outputs an output display signal indicating a signal output and stops operating in response to generation of the snooze start signal and disappearance of the operation signal; and an audio circuit that is operable only when the operation signal is generated and that outputs the audio signal from the audio circuit. an annunciation circuit for notifying audio in response to a signal supplied from the audio circuit; an audio stop detection circuit for detecting disappearance of the output display signal from the audio circuit; and a sound stop detection circuit for generating a detection signal from the audio stop detection circuit only when the alarm-on signal is generated. A repeating signal output circuit that outputs a start signal to the start signal generation circuit in response; A mode switching circuit that outputs a first mode signal or a second mode signal by external operation in an audio clock with snooze; a 1/2 frequency divider that divides the output display signal from the audio circuit into 1/2 and whose frequency-divided output is cleared each time a count-up signal is generated from the snooze counter; and a count from the audio selection counter. The output signal and the first mode signal from the mode switching circuit are input, and the first mode signal is inputted.
a single voice repetition circuit that outputs a voice selection signal corresponding to the count output signal only when a mode signal is generated; and a count output signal from the voice selection counter and a second mode signal from the mode switching circuit, and A frequency divided output signal from a frequency divider by 2 is input, and an audio selection signal corresponding to the count output signal is output only when the second mode signal is generated, and a voice selection signal corresponding to the count output signal is output when the same count output signal is generated. A voice clock with snooze, comprising: a multiple voice repetition circuit that changes a voice selection signal in response to a change in a frequency division output;