JPH0438594U - - Google Patents

Info

Publication number
JPH0438594U
JPH0438594U JP8023690U JP8023690U JPH0438594U JP H0438594 U JPH0438594 U JP H0438594U JP 8023690 U JP8023690 U JP 8023690U JP 8023690 U JP8023690 U JP 8023690U JP H0438594 U JPH0438594 U JP H0438594U
Authority
JP
Japan
Prior art keywords
display means
storage device
time
counting circuit
decoder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8023690U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP8023690U priority Critical patent/JPH0438594U/ja
Publication of JPH0438594U publication Critical patent/JPH0438594U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案におけるデジタル時計の機能ブ
ロツク図、第2図は第1図のデジタル時計の回路
構成図、第3図は第1図のデジタル時計における
音発生器の回路図、第4図は第1図のデジタル時
計における時刻調整装置の回路図、第5図は本考
案における他の改良された具体例を示す回路図で
ある。 1……時刻計数回路、3……設定回路、4……
音発生器、5……駆動用インターフエース、6…
…切換え回路、7……記憶装置選択手段、11…
…発振器、12……第1の表示手段、13……第
2の表示手段、21……分デコーダ、22……時
デコーダ、23……記憶装置、34,35……制
御用スイツチ、101,102,103……時刻
設定用スイツチ、130……LED、131……
カウンタ、132……押釦スイツチ、302,3
03,304,305……フリツプフロツプ。
Fig. 1 is a functional block diagram of the digital clock of the present invention, Fig. 2 is a circuit diagram of the digital clock of Fig. 1, Fig. 3 is a circuit diagram of the sound generator in the digital clock of Fig. 1, and Fig. 4 is a functional block diagram of the digital clock of the present invention. 1 is a circuit diagram of the time adjustment device in the digital watch of FIG. 1, and FIG. 5 is a circuit diagram showing another improved example of the present invention. 1... Time counting circuit, 3... Setting circuit, 4...
Sound generator, 5... Drive interface, 6...
...Switching circuit, 7...Storage device selection means, 11...
...Oscillator, 12...First display means, 13...Second display means, 21...Minute decoder, 22...Hour decoder, 23...Storage device, 34, 35...Control switch, 101, 102, 103... Time setting switch, 130... LED, 131...
Counter, 132...Push button switch, 302,3
03,304,305...flipflop.

Claims (1)

【実用新案登録請求の範囲】 (1) 発振器と、前記発振器により駆動される時
刻計数回路と、前記時刻計数回路に接続され時、
分を表示する第1の表示手段及び曜日を表示する
第2の表示手段と、前記第1の表示手段に接続さ
れこの第1の表示手段からの信号をデジタル形式
に変換する時デコーダ及び分デコーダと、前記時
デコーダ及び分デコーダからの各信号を受け取り
複数の入・出力及び制御用ピンを有する記憶装置
と、前記記憶装置の入力に接続された複数のフリ
ツプフロツプ及び制御用スイツチからなり音報知
を行う時刻を予め設定する設定回路と、前記記憶
装置の各出力に接続されこの記憶装置により音報
知を行う音発生器及び駆動用インターフエースと
、前記第2の表示手段の出力及び前記記憶装置の
制御用ピンに接続され前記第2の表示手段に表示
された日に前記記憶装置の機能を抑止する切換え
回路と、前記時刻計数回路に接続され第1及び第
2の表示手段に表示された時刻の手動調整を行う
時刻設定用スイツチとからなることを特徴とする
設定時刻に音報知を行うデジタル時計。 (2) 前記第2の表示手段は前記時計計数回路の
出力に接続されたカウンタと、複数のLEDと、
前記第2の表示手段に表示された日を調整するた
めの押釦スイツチとからなることを特徴とする実
用新案登録請求の範囲第1項記載のデジタル時計
。 (3) 設定時刻に前記音発生器を介して報知を行
うための音楽用ソフトウエアをそれぞれ記憶した
記憶ブロツクを増やすため、前記記憶装置のアド
レスバスに接続して2個のスイツチを有する記憶
装置選択手段を備えたことを特徴とする実用新案
登録請求の範囲第1項記載のデジタル時計。
[Claims for Utility Model Registration] (1) An oscillator, a time counting circuit driven by the oscillator, and a time counting circuit connected to the time counting circuit;
a first display means for displaying the minutes, a second display means for displaying the day of the week, and an hour decoder and a minute decoder connected to the first display means and for converting signals from the first display means into digital format. and a storage device which receives each signal from the hour decoder and the minute decoder and has a plurality of input/output and control pins, and a plurality of flip-flops and control switches connected to the inputs of the storage device. a setting circuit that presets the time to perform the operation; a sound generator and drive interface that are connected to each output of the storage device and perform sound notification by the storage device; a switching circuit connected to the control pin and inhibiting the function of the storage device on the date displayed on the second display means; and a switching circuit connected to the time counting circuit and the time displayed on the first and second display means. A digital clock that makes an audible notification at a set time, comprising a time setting switch that performs manual adjustment. (2) The second display means includes a counter connected to the output of the clock counting circuit, a plurality of LEDs,
2. The digital timepiece according to claim 1, further comprising a push button switch for adjusting the date displayed on the second display means. (3) A storage device connected to the address bus of the storage device and having two switches in order to increase the number of storage blocks each storing music software for making a notification via the sound generator at a set time. A digital watch according to claim 1, characterized in that it is equipped with a selection means.
JP8023690U 1990-07-28 1990-07-28 Pending JPH0438594U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8023690U JPH0438594U (en) 1990-07-28 1990-07-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8023690U JPH0438594U (en) 1990-07-28 1990-07-28

Publications (1)

Publication Number Publication Date
JPH0438594U true JPH0438594U (en) 1992-03-31

Family

ID=31625113

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8023690U Pending JPH0438594U (en) 1990-07-28 1990-07-28

Country Status (1)

Country Link
JP (1) JPH0438594U (en)

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