JPS6216713Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a digital clock with an alarm.

Conventional digital clocks with alarms are manufactured using clock integrated circuits (hereinafter referred to as clock LSIs) that have alarm functions.
), the clock information of this clock LSI can be corrected or the display can be changed by turning on the time correction switch and display changeover switch, and also sounds an alarm when an alarm output signal is output from the clock LSI. The sound is stopped by turning on the stop switch.
However, in such digital watches, the various operation switches mentioned above are mounted relatively close to the watch case, so it is difficult to reliably operate the alarm silence switch when an alarm output signal is output. There was also the problem that the time could be adjusted by accidentally pressing a different time adjustment switch.

In order to solve this problem, we installed a logic circuit that makes it impossible for the time adjustment switch to perform corrective action while the alarm output signal is being output, and also makes it possible to stop the alarm from sounding.
It is being considered that the time adjustment switch also functions as an alarm silence switch. However, in such a watch, when the alarm is turned off by operating the switch, the output of the alarm output signal is immediately stopped, so the time can be adjusted by operating the switch. For this reason, when the switch is operated to silence the alarm, the time can be adjusted while the switch is still being pressed, resulting in the user inadvertently adjusting the time.

In order to eliminate these conventional drawbacks, the present invention aims to provide a digital clock in which the display of clock information does not change even if the switch is pressed for a certain period of time after the alarm is turned off by the switch. This is the purpose.

Hereinafter, the present invention will be explained in detail using the drawings.

The figure is a circuit diagram of essential parts showing an embodiment of a digital watch according to the present invention. In the figure, reference numeral 1 denotes an ordinary watch LSI having an alarm function, which has a time adjustment terminal 1a, a display switching terminal 1b, an alarm output terminal 1c, and an alarm silence terminal 1d. In this case, the time adjustment terminal 1a is connected to the clock when the input signal is at the V _SS level (hereinafter referred to as "L").
Enables time adjustment of LSI1, display switching terminal 1b
Similarly, "L" selects the display of clock, alarm, etc. Further, the alarm output terminal 1c outputs a V _DD level (hereinafter referred to as "H") as an alarm output signal when the time correction and alarm set time match. And alarm stop terminal 1
d turns off the alarm output signal when the input signal is "L". 2 is the time adjustment switch,
3 is a display changeover switch, one end of these switches 2 and 3 is commonly connected to the V _SS level line, each other end is pulled up to "H" (not shown), and the above-mentioned alarm is connected to one input terminal. The output signals are connected to the other input terminals of OR gates 4 and 5, respectively. Each output terminal of the OR gates 4 and 5 is connected to the other input terminal of the OR gates 6 and 7 to which the timer output signal of the 2-second timer 17 is input via the inverter 13 to one input terminal.
The output terminals of the clock LSI 1 are connected to the time adjustment terminal 1a and the display switching terminal 1b, respectively.
Note that each of the OR gates 4 to 7 constitutes a first gate circuit.

The other ends of the time adjustment switch 2 and display changeover switch 3 are connected to the other input terminals of OR gates 9 and 10, each of which has an output signal obtained by inverting the alarm output signal by an inverter 8. be done. The output terminals of the OR gates 9 and 10 are connected to each input terminal of the AND gate 11, and the output terminals are connected to the alarm stop terminal 1d of the clock LSI 1, and one input terminal of the OR gate 12 is connected via the inverter 18. connected to the terminal. The other input terminal of this OR gate 12 is connected via a capacitor 14 and a power switch 15 to the V _DD level line, and via a pull-down resistor 16 to the V _SS level line.
And the output terminal of OR gate 12 is 2 seconds timer 1
It is connected to the reset terminal (R) of 7. Incidentally, each of the OR gates 9 and 10 and the AND gate 11 constitute a second gate circuit.

Next, the operation of the above embodiment will be explained.

[] When the alarm output signal is not output from the clock LSI, the OR gate 12 is activated by turning on the power switch 15.
When an "H" pulse signal is input to the input terminal of the OR gate 12, an "H" pulse signal is output to the output terminal of the OR gate 12, and the 2-second timer 17 receives an "H" pulse signal to the reset terminal (R). is input. As a result, the timer 17 outputs an "H" signal from its output terminal after two seconds, and this "H" signal is input to the input terminals of the OR gates 6 and 7 via the inverter 13, and these input terminals becomes “L”. Further, since the clock LSI 1 is in a state where no alarm output signal is output, the alarm 1c is "L", and the input terminals of the OR gates 4 and 5 are both "L". When the time correction switch 2 is turned on, the input terminal of the OR gate 4 becomes "L", its output terminal also becomes "L", and the input terminal of the OR gate 6 also becomes "L". As a result, "L" is output to the output terminal of OR gate 6, and the clock
By inputting an "L" signal to the time adjustment terminal 1a of the LSI 1, the time adjustment switch 2 can adjust the time. Furthermore, when the display changeover switch 3 is turned on, the output terminals of the OR gates 5 and 7 become "L" in the same way as when the switch 2 is operated, and as a result, the display changeover terminal 1b of the watch LSI 1 becomes "L". Since the signal is input,
The display changeover switch 3 enables display changeover.

[] When an alarm output signal is output from the clock LSI When "H" is output from the alarm output terminal 1c, the input terminals of the OR gates 4 and 5 become "H". For this reason, the OR gate 4,
Each output terminal of 6 and 5, 7 is always “H”,
It becomes impossible to adjust the time or switch the display. On the other hand, the alarm output signal "H" is output to the inverter 8.
The inverted output signal "L" is input to the input terminals of OR gates 9 and 10. As a result, when the time correction switch 2 is turned on, the input signal of the OR gate 9 becomes "L", and when the display changeover switch 3 is turned on, the input terminal of the OR gate 10 becomes "L". Therefore, when any "L" signal is input to each input terminal of the AND gate 11, an "L" signal is output from the output terminal of the AND gate 11. Therefore, this "L" signal is input as an alarm stop signal to the alarm stop terminal 1d of the watch LSI 1, and the alarm can be stopped by the switch 2 or 3.

Then, when this sounding is stopped, at the same time, the input terminal of the OR gate 12 is inverted from the alarm sounding stopping terminal 1d to "H" by the inverter 18.
The "H" pulse signal output from the output terminal is input to the reset terminal of the two-second timer 17. Therefore, the 2-second timer 17 outputs an "L" signal for 2 seconds after the alarm stops sounding, and this output signal is inverted by the inverter 13, so even if the alarm stops sounding, the 2-second timer 17 outputs an "L" signal for 2 seconds after the alarm stops sounding. The outputs of the OR gates 6 and 7 become "H", and during this time, no time adjustment or display switching is performed even if the switches 2 and 3 are turned on. The output signal of the 2-second timer 17 becomes an "H" signal after 2 seconds have elapsed. This returns the power switch 15 to the on state described above, and by turning on the time adjustment switch 2 or the display changeover switch 3, it becomes possible to adjust the time or change the display.

Note that the present invention is not limited to the above-mentioned embodiments, and is applicable to all externally operated switches that change the clock information in addition to externally operated switches that modify the clock information of the clock LSI or change the display. It is also possible to add a function to silence the alarm.

In addition, the gate circuit that controls the operation signal of the external operation switch and outputs the alarm stop signal according to the alarm output signal output from the clock LSI is not limited to OR gates and AND gates, but may be replaced with other logic gates. You can also do it.

As explained above, with the digital clock of the present invention, even if the display change switch is also used as the alarm silence switch, there is no possibility that the display will be changed by mistake when operating the switch to silence the alarm. This has the effect of eliminating erroneous operations and improving operability.

[Brief explanation of the drawing]

The figure is a circuit diagram of essential parts showing an embodiment of a digital watch according to the present invention. 1... Clock integrated circuit (LSI), 1a... Time correction terminal, 1b... Display switching terminal, 1c... Alarm output terminal, 1d... Alarm stop terminal, 2
... Time correction switch, 3 ... Display changeover switch, 4 to 7, 9, 10, 12, ... OR gate,
8, 13...Inverter, 11...And gate, 17...2 second timer.

Claims (1)

[Claims for Utility Model Registration] A drive terminal that changes the clock information displayed when a signal is input, an alarm output terminal that outputs an alarm output signal when an alarm occurs, and an alarm that stops sounding when a signal is input. an integrated circuit for a watch having an alarm sounding terminal, an external operation switch for supplying an operating signal to the drive terminal, and a timer that outputs an output signal for a certain period of time when a signal is input to the alarm sounding terminal. , When the alarm output signal is not output, it is possible to input the operation signal from the external operation switch to the drive terminal, and when the alarm output signal is output, this input is disabled, and the output signal from the timer is output. A first gate circuit that disables input of the operation signal to the drive terminal regardless of the alarm output signal when the alarm output signal is output, and an external operation switch that stops the operation signal alarm from sounding when the alarm output signal is not output. a second gate circuit that disables input to the terminal and enables this input when an alarm output signal is output.