JPS625314B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic watch equipped with notification functions such as a timer, an alarm, and a time signal.

Recently, electronic watches have become more and more multi-functional.
Various products have been commercialized that have an alarm function that sets a time and sounds a sound at that time, a time signal function that sounds a sound every hour on the hour, etc.

However, some electronic watches with a notification function use a display in addition to sound as a means of notifying the notification time. The body lights up or flashes. but,
If the notification method is simply to turn on or blink the display, the visually appealing effect is low, and there is a risk that the display may be missed. Furthermore, optical display means constructed of liquid crystal or electrochromic elements have the disadvantage that the display becomes monotonous. Furthermore, although electronic clocks that can store a plurality of alarm times and notify each alarm time are known, it is not possible to know which alarm time the alarm time corresponds to when the notification is made.

This invention was made in view of the above circumstances, and its purpose is to make a notification using the entire time display in an electronic watch equipped with multiple notification functions, so that the notification time is reached. To provide an electronic timepiece which not only clearly informs the user that the notification time has arrived, but also informs which notification time the notification time has arrived.

Hereinafter, the present invention will be explained in detail based on an embodiment shown in the drawings. FIG. 1 is a circuit diagram of an electronic timepiece with an alarm function to which the present invention is applied.
In the figure, reference numeral 1 is an oscillation circuit that generates a reference frequency signal, and the reference frequency signal is applied to a frequency dividing circuit 2. This frequency dividing circuit 2 divides the frequency into a predetermined frequency signal and a signal with a period of 1 second based on the reference frequency signal, and the predetermined frequency signal is given to a timing generation circuit 3, and the signal with a period of 1 second is given to the sexagesimal seconds counting circuit 4. This second counting circuit 4 sends out a carry-up signal every minute and supplies it to a sexagesimal minute counting circuit 5. The minute counting information obtained by the minute counting circuit 5 is sent to the decoder 6
and 7, as well as matching circuits 8 and 9. Further, the minute counting circuit 5 sends out a carry-up signal every hour, and supplies it to the sexagesimal clock counting circuit 10. The clock information obtained by the clock circuit 10 is supplied to the decoder 7 as well as to the matching circuits 8 and 9. The decoder 6 decodes the minute counting information from the minute counting circuit 5 and outputs corresponding output information b ₀ to b ₅₉ to be supplied to the display control circuit 11 . The decoder 7 also includes a minute counting circuit 5.
The minute count information from the clock count circuit 10 and the clock count information from the clock count circuit 10 are decoded and the corresponding output information a ₀ ~
a ₅₉ is supplied to the sending display control circuit 11. The display control circuit 11 includes a timing signal generation circuit 3.
Three-phase timing signals f ₁ , f ₂ , f ₃ , which will be described later, are provided as display control signals.

On the other hand, the matching circuit 7 is supplied with output information from the minute storage section 12a and hour storage section 12b, which constitute the first alarm time setting circuit 12, respectively. The matching circuit 8 also includes a minute storage section 13a and a storage section 1 constituting the second alarm time setting circuit 13.
The output information of 3b is supplied respectively. and,
The matching circuit 8 includes the minute counting circuit 5 and the minute storage section 12a.
Output information and clock count circuit 10 and time storage unit 12
When the output information with b matches each other, the match signal c ₁
is sent out and given to the display control circuit 11. Note that the matching circuit 9 receives output information from the minute counting circuit 5 and the minute storage section 13a, and the output information from the clock counting circuit 10 and the hour storage section 13b.
When the output information matches, a match signal _c2 is sent out and given to the display control circuit 11. The above match signal
c ₁ and c ₂ are also given to the alarm control circuit 14. This alarm control circuit 14 sends out a drive signal to cause the buzzer device 15 to emit an alarm sound when either one of the coincidence signals c ₁ and c ₂ is applied.

On the other hand, the symbol S is an externally operated switch,
By operating this switch S, a one-shot pulse is output from the one-shot circuit 17, and the contents of a ternary counter (count values "0" to "2") for display mode switching are incremented. The count value "0" signal of the counter 18 is given to the display control circuit 11 as a normal time display designation signal, and the count value "1" and "2" signals are respectively given to the display control circuit 11 as demonstration display designation signals. A liquid crystal drive signal is sent from the display control circuit 11 and supplied to a liquid crystal time display section 19 that optically displays time information as a pointer.

FIG. 2 is a diagram showing the arrangement of liquid crystal electrodes constituting the time display section 19. That is, the liquid crystal electrodes are arranged radially around the circular center display body C and arranged at random intervals in a group of 60 rod-shaped inner display elements A ₀ -
A ₅₉ is arranged, and this inner display element group A ₀ ~
A group of 60 rod-shaped outer display elements B ₀ ~ on the extension line of A ₅₉
It consists of an array of B ₅₉ .

FIG. 3 shows an output waveform diagram of the timing signals f ₁ , f ₂ , f ₃ . These timing signals f ₁ , f ₂ , f ₃
is a signal with a duty of 1/2 and a period of 1 second, and
Timing signal f ₂ is 0.25 less than timing signal f ₁
The timing signal _f3 is outputted with a delay of 0.25 seconds than the timing signal _f2 .

FIG. 4 shows the display control circuit 11 and the time display section 1.
FIG. 9 is a circuit configuration diagram of No. 9. The count value "0" signal of the ternary counter 18 is applied to one input terminal of an AND circuit 20, and the output signal of the NAND circuit 21 is applied to the other input terminal of the AND circuit 20. Coincidence signals c ₁ and c ₂ are applied to the input terminals of this NAND circuit 21, respectively. Also,
The count value “1” signal of the ternary counter 18 is sent to three AND circuits 23, 24, 2 via an OR circuit 22.
5 as a gate control signal. The other input terminal of the AND circuit 23 receives the timing signal _f1 , and the AND circuit 2
The other input side terminal of 4 has a timing signal f ₃
However, the other input terminal of the AND circuit 25 is provided with a timing signal f ₂ . Further, the count value “2” signal of the ternary counter 18 is sent to three AND circuits 27, 2 via an OR circuit 26.
The gate control signal is inputted to one input side terminal of terminals 8 and 29 as a gate control signal. The other input terminal of the AND circuit 27 receives the timing signal f ₁ , the other input terminal of the AND circuit 28 receives the timing signal f ₂ , and the other input terminal of the AND circuit 29 receives the timing signal f 1 . , a timing signal _f3 is given as a gate control signal. On the other hand, the output information b ₀ to b ₅₉ from the decoder 6 is sent to the corresponding AND circuit AN ₀
~AN ₅₉ is given to one input side terminal, respectively.
When each of these AND circuits AN ₀ to _{AN 59} receives the output signal of the AND circuit 20 at one of its input terminals, the gate is released. Also, decoder 7
The output information a ₀ to _{a 59} is given to one input side terminal of the corresponding AND circuit AN' ₀ to AN' ₅₉ . Each of these AND circuits AN' ₀ to AN' ₅₉ is gated off when receiving the output signal of the AND circuit 20 at one of its input terminals. The output signals of the AND circuits AN ₀ to AN ₅₉ are applied to the input terminals of the corresponding OR circuits OR ₀ to OR ₅₉ , and the output signals of the AND circuits AN' ₀ to AN' _{59 are applied to the input terminals of the corresponding OR circuits OR 0 to OR 59} . It is applied to the input side terminals of OR circuits OR' ₀ to OR' ₅₉ . The output signal of the AND circuit 24 is applied to the input side terminal of each OR circuit OR ₀ to OR ₅₉ , and the output signal of the AND circuit 25 is applied to each OR circuit OR' ₀ to
These signals are applied to the input side terminals of OR′ ₅₉ , respectively. Further, the output signal of the AND circuit 27 is the OR circuit OR ₀ ~
Out of OR ₅₉ , OR circuit OR ₀ ~ OR ₄ , OR ₁₀ ~
OR ₁₄ , OR ₂₀ ~ OR ₂₄ , OR ₃₀ ~ OR ₃₄ , OR ₄₀ ~
It is given to the input side terminals of OR ₄₄ , OR ₅₀ to OR ₅₄ , and among the OR circuits OR' ₀ to OR' ₅₉ , OR' ₅ to
OR′ ₉ , OR′ ₁₅ 〜OR′ ₁₉ , OR′ ₂₅ 〜OR′ ₂₉ , OR′ ₃₅ 〜
It is given to the input side terminals of _OR'39 , _OR'45 to _OR'49 , and _OR'55 to _OR'59 . Further, the output signal of the AND circuit 29 is the OR circuit OR circuits OR ₅ to OR ₉ except those to which the output signal of the AND circuit 27 is applied.
………OR ₅₅ ~ OR ₅₉ and OR′ ₀ ~ OR′ ₄ ……………
It is given to the input side terminals of OR' ₅₀ to OR' ₅₄ . The output signals of the AND circuits 20, 23, and 28 are collectively applied to the input side terminal of the OR circuit OR'_' .
Liquid crystal drive circuits M _{0 -M 59} , M _{' 0} -M' ₅₉ , M'' corresponding to -OR ₅₉ , OR' ₀ -OR' ₅₉ , OR'' are provided. Each of these liquid crystal drive circuits M ₀ to M ₅₉ , M′ ₀ to
M′ ₅₉ , M″ send out a liquid crystal drive signal when receiving the output signal of the corresponding OR circuit. The liquid crystal drive signal sent from the liquid crystal drive circuits M ₀ to _{M 59} is as follows:
Outer display element group B ₀ to _{B 59} in time display section 19
The liquid crystal drive signals sent from the liquid crystal drive circuits M′ ₀ to M′ ₅₉ are applied to the inner display element groups A ₀ to
A ₅₉ and a liquid crystal driving signal sent from the liquid crystal driving circuit M'' are applied to the center display C.

Next, the operation of the electronic timepiece configured as described above will be explained with reference to the display states shown in FIGS. 5 to 7. First, when the content of the ternary counter 18 for display mode switching is "0" and both the coincidence signals c ₁ and c ₂ are not output, the AND circuit 20 changes the count value of the counter 18 to "0". `` signal and the output signal of NOR circuit 21 provide an output, which gates AND circuits AN ₀ -AN ₅₉ , AN' ₀ -AN' ₅₉ . As a result, output information b ₀ to b 59 from decoder 6 and output information a ₀ to b ₅₉ from decoder 7
_a59 is connected to the liquid crystal drive circuit _M0 to _M59 , _M'0 to M via AND circuits _AN0 to _AN59 , _AN'0 to _AN'59 and OR circuits _OR0 to _OR59 , _OR'0 to _OR59 . _'59 . For example, when a drive signal is output from the liquid crystal drive circuit M′ ₁₅ , Ma, M′ ₀ , the inner display element
A ₁₅ , A ₀ and the outer display element B ₀ are driven, and as shown in FIG. 5, for example, the current time "3:00" is optically displayed on the hand.

When the coincidence circuit 8 detects that the alarm time of the first alarm time setting circuit 12 has been reached, a coincidence signal _c1 is outputted and applied to the NOR circuit 21 of the display control circuit 11, and the OR circuit AND circuits 23, 24, 25 via 22
given to. As a result, AND circuit 20 is closed, and AND circuits 23, 24, and 25 are opened. Therefore, the AND circuit 23 outputs the timing signal f ₁ , the AND circuit 24 outputs the timing signal f ₂ , and the AND circuit 25 outputs the timing signal f ₃ . And, as shown in Figure 3,
During the first 0 to 0.25 seconds, only the timing signal _f1 is output, and is applied to the liquid crystal drive circuit M'' via the OR circuit OR''. Therefore, in the time display section 19, only the center display body C is driven,
The screen is displayed as shown in FIG. 6A. Next, from 0.25 seconds to 0.5 seconds, as shown in FIG. 3, a timing signal _f2 is output in addition to the timing signal _f1 . Therefore, the timing signal f ₁ is given to the liquid crystal drive circuit M'' in the same way as above, and the timing signal f ₂ is given to the liquid crystal drive circuit M' ₀ to M' ₅₉ via the OR circuits OR' ₀ to OR' ₅₉ . Therefore, in the time display section 19, in addition to the center display C,
The inner display element groups A ₀ to A ₅₉ are driven to display the image as shown in FIG. 6B. Next, from 0.5 seconds to 0.75 seconds, as shown in FIG. 3, a timing signal _f3 is output in addition to the timing signal _f2 .
Therefore, the timing signal f ₂ is given to the liquid crystal display circuits M' ₀ to M' ₅₉ in the same way as above, and the timing signal f ₃ is given to the liquid crystal display circuits M ₀ to M' 0 to M' ₅₉ through the OR circuits OR ₀ to OR 59. Given to M ₅₉ . Therefore, in the time display section 19, the inner display element group A ₀ -A ₅₉ and the outer display element group B ₀ -B ₅₉ are driven simultaneously, and the display is displayed as shown in FIG. 6C. Next, from 0.75 seconds to 1 second, only the timing signal _f2 is output. Therefore, in the time display section 19, the outer display element groups _B0 to _B59 are driven, and a display is displayed as shown in FIG. 6D. In this way, the display pattern that changes every 0.25 seconds is repeated every second, giving a dynamic impression similar to fireworks. This display makes it possible to visually indicate that the first alarm time has arrived. On the other hand, the match signal
In response to the output of _c1 , the sound control circuit 14 drives the buzzer device 15 to emit an alarm sound to audibly indicate that the alarm time has arrived.

Next, when the coincidence circuit 9 detects that the alarm time of the second alarm time setting circuit 13 has been reached, a coincidence signal c ₂ is outputted and given to the NOR circuit 21 of the display control circuit 11, and also AND circuit 27,2 via circuit 26
Given on 8,29. As a result, AND circuit 20 is closed, and AND circuits 27 and 2
8 and 29 are opened. Therefore, AND circuit 27
The AND circuit 28 outputs a timing signal f ₁ , the AND circuit 28 outputs a timing signal f ₂ , and the AND circuit 29 outputs a timing signal f ₃ . As shown in FIG. 3, from 0 seconds to 0.25 seconds, only the timing signal _f1 is output, and the liquid crystal drive circuits _M0 to _M4 ,
M ₁₀ ~ M ₁₄ ………………M ₅₀ ~ M ₅₄ and M′ ₅ ~ M′ ₉ ,
M′ ₁₅ to M′ ₁₉ ……………M′ ₅₅ to M′ ₅₉ are given. As a result, in the time display section 19, among the inner display element groups _A0 to _A59 , _A5 to _A9 , _A15 to _A19 ...
...... _A55 to _A59 are driven, and among the outer display element group _B0 to _B59 , _B0 to _B4 , _B10 to _B14 ......
. . . B ₅₀ to _{B 54} are driven and displayed as shown in FIG. 7A. Next, from 0.25 seconds to 0.5 seconds, in addition to the timing signal f ₁ , the timing signal f ₂
is output. This timing signal _f2 is an OR circuit
It is applied to the liquid crystal drive circuit M'' via OR'', and drives the center display C. As a result, as shown in FIG. 7B, the time display section 19 displays a pattern in which a display corresponding to the center display C is added to the display pattern shown in FIG. 7A. Next, from 0.5 seconds to 0.75 seconds, a timing signal _f3 is output in addition to the timing signal _f2 . This timing signal
_f3 is the liquid crystal drive circuit _M5 ~ _M9 , _M15 ~ _M19 …………
... _M55 to _M59 and _M'0 to _M'4 , _M'10 to _M'14 ......
......Given from M′ ₅₀ to M′ ₅₄ . As a result, in the time display section 19, the inner display element groups A ₀ to _{A 59}
Among them, A ⁰ ~ A ₄ , A ₁₀ ~ A ₁₄ ………………A ₅₀ ~
A ₅₄ is driven, and outer display element groups B ₅ to _{B 9} , B ₁₅
~B ₁₉ ......B ₅₅ ~ _{B 59} are driven, and a pattern as shown in FIG. 7C is displayed. Then 0.75~
During one second, only the timing signal _f3 is output. As a result, as shown in FIG. 7D, the time display section 19 displays a display pattern shown in FIG. 7C in which the display corresponding to the center display C is turned off. In this way, the display pattern that changes every 0.25 seconds is repeated every second, giving a dynamic impression as if it were continuously rotating. This display makes it possible to visually indicate that the second alarm time has arrived. On the other hand, due to the output of the coincidence signal _c2 , the alarm control circuit 14
drives the buzzer device 15 to emit an alarm sound to visually indicate that the alarm time has arrived.

In this way, when the first alarm time is reached, the display as shown in FIGS. 6A to 6D is performed,
Also, when the second alarm time is reached, the seventh
Since the display shown in Figures A to D is displayed, it is easy to identify whether the emitted alarm sound is aimed at the first alarm time or the second alarm time. I can do it.

Next, when the external operation switch S is operated to set the content of the ternary counter 18 for display mode switching to "1", the count value "1" signal of the counter 18 is sent to the OR circuit 22 in the display control circuit 11. The signal is applied to each AND circuit 23, 24, and 25 via the signal.
Therefore, as when the coincidence signal c ₁ is output, each AND circuit 23, 24, 25 is gated, respectively, and outputs the corresponding timing signal f ₁ , f ₂ , f ₃ . Therefore, the time display section 19 displays the patterns shown in FIGS. 6A to 6D.

Next, when the external operation switch S is operated to set the content of the ternary counter 18 to "2", in the display control circuit 11, the count value "2" signal of the counter 18 is transmitted to each AND circuit via the OR circuit 23. 24, 25, 26. Therefore, the coincidence signal _c2 is de-gated and the corresponding timing signals _f1 , _f2 , _f3 are output. Therefore,
In the time display section 19, patterns shown in FIGS. 7A to 7D are displayed.

By operating the external operation switch S in this way, all the display elements in the time display section 19 can be
A ₀ ~A ₅₉ , B ₀ ~ _{B 59} , and C are driven, and A ~
Since it can display patterns such as those shown in D and FIGS. 7A to 7D, it can also be used as an accessory.

In the above embodiment, the time information is displayed in hours and minutes, but it may also be displayed in seconds. In addition, for example, using a multilayer liquid crystal cell, one layer is provided with an analog display section that optically displays time information, and the other layer is provided with a digital display section that displays alarm time, date, etc. in numerical values. It's okay.

Further, although the above embodiment is applied to an electronic watch equipped with two alarm functions, a pattern may be displayed when notifying a time signal function, a timer function, etc. instead of an alarm function, or a pattern may be displayed when notifying a time signal function, a timer function, etc. If the system is equipped with functions, it is possible to know which function the notification is aimed at by displaying a unique display corresponding to each function.

Further, in the above embodiment, a liquid crystal was used as the optical display means, but an electromics element may also be used, and color display may also be performed. In addition, the display pattern is not limited to the above embodiment, and even more varied patterns can be displayed.

Further, although the above embodiment is applied to an electronic watch, the present invention can also be applied to an electronic watch with a calculation function that incorporates a calculator.

As described in detail above, the present invention is an apparatus for displaying time information with a hand by selectively driving a plurality of optical display elements constituting a time display section, which is provided with a plurality of alarm time storage means. When each alarm time is reached, notifications are displayed in different display formats, so it is possible to clearly notify that a predetermined notification time has arrived among multiple notification times, and the display can be There is no risk of missing or mistaking it.

[Brief explanation of the drawing]

The drawings show one embodiment of the invention.
Figure 1 is a circuit diagram of an electronic watch with an alarm function.
FIG. 2 is a diagram showing the arrangement of liquid crystal display electrodes constituting the time display section 19, and FIG. 3 is a diagram showing timing signals.
Output waveform diagram of f ₁ , f ₂ , f ₃ , Figure 4 is the display control circuit, circuit diagram of the time display section, Figures 5 and 6 ,
FIG. 7 is a diagram showing the display state. 5... Minute counting circuit, 8, 9... Matching circuit, 10
... Clock number circuit, 11 ... Display control circuit, 12,
13... Alarm time setting circuit, 19... Liquid crystal time display section, _A0 to _A59 , _B0 to _B59 , C... Display body.

Claims (1)

[Claims] 1. A first display element group consisting of a plurality of display elements arranged in a ring, and a second display element group consisting of a plurality of display elements arranged in a ring outside the first display element group.
an optical display device having a group of display elements, a time counting means for counting reference signals to obtain time information consisting of hour information and minute information, and displaying the time information obtained by the time counting means on the first display. Pointer time display control for driving at least one display element of the element group to display the minute information and driving at least one of each of the first display element group and the second display element group to display the minute information; means, first and second
alarm time storage means for storing an alarm time; and when the time information obtained by the time counting means coincides with each of the first and second alarm times, each of the optical display devices displays an alarm coincidence display. and an alarm coincidence display control means for dividing the frequency of the reference signal to output a plurality of timing signals; The timing for displaying all of the first and second display element groups by the timing signal when the time information displayed coincides with the first alarm time; A first method for repeatedly displaying a timing for displaying all of the display element groups and a timing for displaying neither of the first and second display element groups;
alarm display control means, and when the time information obtained by the time counting means coincides with the second alarm time, the timing signal causes the first
and a second alarm display control means that divides the display elements of each of the second display element groups into a plurality of groups and alternately displays each of the divided groups at predetermined timings. An electronic clock featuring