JPH0237594A - Static ram accessing circuit - Google Patents

Abstract

PURPOSE:To prevent a delay quantity from changing due to the change of environment by setting delayed signals by inputting an address signal, a data signal, a read instruction signal, and a write instruction signal to an FF which outputs data in synchronism with a clock generated at a 3-frequency division circuit. CONSTITUTION:The address signal, the data signal, and the read signal with width of one cycle of the clock of the 3-frequency division circuit 4 are inputted to the FFs 11-13 which output the data in synchronism with the clock in which the ratio of a level '1' to a level '0' generated at the 3-frequency division circuit 3 is set at 1:2, and they are delayed a little, then, are inputted to a RAM 2 as the address signal, the data signal, and the read signal. Also, the write instruction signal with the width of one cycle of the clock of the 3-frequency division circuit 4 is inputted to the FF 14, and it is delayed a little, then, is inputted to a logic gate 15. By taking the OR of the clock with the ratio of 1:2 and the FF 14 by inputting also the clock generated at the 3-frequency division circuit 4 to the logic gate 15, a write signal in which a delay component whose 2/3 of one cycle of the clock being a write cycle is the pulse of '0' level, and the delay quantity by the operations of the FFs 11 and 12 becomes a data write holding time is outputted.

Description

[Detailed Description of the Invention] [Summary] Regarding a static RAM access circuit that accesses static RAM using a dedicated chip that performs predetermined operations, the present invention relates to a static RAM access circuit that accesses static RAM using a dedicated chip that performs predetermined operations. For the purpose of providing a RAM access circuit, the 1:2 clock generated by the frequency divider circuit is used as the clock for the dedicated chip, and a first flip-flop inputs an address, a second flip-flop inputs data, The clock terminals of the third flip-flop to which the read instruction signal is input and the fourth flip-flop to which the write instruction signal is input are input to the logic gate, and the output of the fourth flip-flop is also input to the logic gate. Then, the output of the first flip-flop is used as an address, the output of the second flip-flop is used as data, and the output of the third flip-flop is used as a read signal, and the logic gate inputs the 1: 2 and the output of the fourth flip-flop both have the same sign level, and a signal having a width of 273 of the clock period is output as a write signal.

[Industrial application field]

The present invention relates to a static RAM access circuit that accesses static RAM using a dedicated chip that performs predetermined operations according to instructions from a processor.

In recent years, as systems have become faster and more diverse, it has become impossible to satisfy system specifications using only microprocessors (hereinafter referred to as MPUs).

Therefore, we have installed a dedicated chip that can handle some of the specific tasks that used to be handled by MI'U software by simply providing data and instructions.

The block diagram in this case is shown in Figure 4, and M
Data and instructions are given from the PUI, and in order for the dedicated chip 3 to perform a specific work, various data are sent to the static RA.
This is done by writing to and reading data from M (hereinafter referred to as RAM) 2.

To access this RAM 2, it is necessary to write and read at a speed as close as possible to the access speed guaranteed to the RAM.

-M-wise, the guaranteed timing conditions for RAM access are as shown in FIG.
For the write cycle tWe that sends the address shown in A), the write signal pulse width t, must satisfy a minimum of t, , = 0.6t, c as shown in (B), and the data is (C ), a short data write hold time tDH is required after data set up, so the write signal pulse is
It is necessary to become a rubel before H.

In addition, as a read signal, as shown in (D), the minimum tRP
It is necessary to satisfy =Q, 3t, and C.

Therefore, in order to access RAM2 from the dedicated chimp 3, a circuit that satisfies the above conditions is required, but this circuit is easy to design and is free from power supply fluctuations.

It is desirable that the conditions can be satisfied even if there are environmental changes such as voltage fluctuations.

[Conventional technology]

A conventional example will be explained below using figures.

FIG. 6 is a block diagram of a conventional RAM access circuit, and FIG. 7 is a time chart of each signal in FIG.
F) corresponds to points a-f in FIG.

In FIG. 6, the address output section 20.1 is synchronized with the system clock shown in FIG. The data output section 21 outputs addresses and data with a width of one system clock cycle as shown in FIG. 7(B), and rise and fall delay circuits 24.2 each consisting of a semiconductor gate circuit.
5, and after being delayed, the address and data at the timing shown in (C) are output.

In addition, in synchronization with the system clock, the write instruction section 23 outputs a pulse instructing a write with a width of one system clock period as shown in (D), and the write instruction section 23 outputs a pulse with a width of one system clock cycle, as shown in FIG.

The signal is delayed by the falling delay circuit 27 as shown in (E) and input to the OR circuit 29.

Further, as shown in (F), the system clock is delayed by a rise delay circuit 28, which is constituted by a gate circuit made of semiconductor, and then inputted to an OR circuit 29.

The OR circuit 29 takes the logical sum of these two inputs (F
), but in this case L
The width of the level needs to be at least 0.6 times the system clock cycle, and the data write hold time is also needed, so rise and fall delay circuits 24, 25° 27, The amount of delay of the rise delay circuit 28 must be set.

In addition, in synchronization with the system clock, the read instruction signal section 22 outputs a pulse instructing a read as shown in (H) in one cycle of the system clock, and a falling delay circuit is configured with a gate circuit made of semiconductor. At 26, the delay is delayed as shown in (D), and the minimum period is 0.26, which is one cycle width of the system clock.
Output as a read signal wider than 8 times.

That is, what is output in synchronization with the system clock is made to satisfy the RAM access conditions by various delay circuits constituted by gate circuits made of semiconductors.

[Problem to be solved by the invention]

However, in conventional RAM access circuits, the amount of delay of each delay circuit must be set to satisfy the RAM access conditions, which takes time and effort in designing the amount of delay, and each delay circuit is made of a semiconductor. Since it is configured with a gate circuit, the amount of delay changes due to environmental changes such as temperature changes and power supply fluctuations, and there is a problem that the RAM access conditions may not be satisfied.

An object of the present invention is to provide a static RAM access circuit that satisfies RAM access conditions even when the environment changes and is easy to design.

[Means to solve the problem]

FIG. 1 is a block diagram of the principle of the present invention.

As shown in FIG. 1, the 1:2 clock generated by the frequency divider circuit 4 is used as the clock for the dedicated chip 3, and the first flip-flop 11 inputs an address and the second flip-flop inputs data. 12. The clock terminals of the third flip-flop 13 to which the read instruction signal is input, the fourth flip-flop 14 to which the write instruction signal is input, and the logic gate 15, and the output of the fourth flip-flop 14. is also input to the logic gate 15.

Then, the output of the first flip-flop 11 is used as an address, the output of the second flip-flop 12 is used as data, the output of the third flip-flop 13 is used as a read signal, and in the logic gate 15, The input 1:2 clock and the output of the fourth flip-flop 14 both have the same sign level, and a signal having a width of 2/3 of the clock cycle is output as a write signal.

[For production]

According to the present invention, the level and O generated in the frequency divider circuit 4 are
The first one outputs data in synchronization with a clock whose level is 1:2. Second. Third flip-flop 11, 12
．． 13, addresses and data of one period width of the clock of the frequency divider circuit 4.

A read instruction signal is input, and after being slightly delayed, it is input to the RAM 2 as an address, data, and read signal, so that the pulse widths are equal and completely synchronized.

A write instruction signal having a width of one cycle of the clock of the frequency divider circuit 4 is inputted to the flip-flop 14 of the writer 4, and inputted to the logic gate 15 after being slightly delayed.

Further, a clock generated in the frequency divider circuit 4 with a ratio of, for example, level and O level of 1:2 is also input to the logic gate 15, and a clock of one period width of the clock inputted from the fourth flip-flop 14, for example, of the O level, is input to the logic gate 15. When logically summed with the signal, a pulse is generated in which 2/3 of one cycle width of the clock, which is a write cycle, is at O level.

Also, the end point of this 2/3 O level pulse is a minute before the end point of the output of the fourth flip-flop 14 is delayed by the fourth flip-flop 14, and the output of the logic gate 15 has a hazard (logic whiskers) are not output.

The RAM access circuit described above is a synchronous circuit using flip-flops, and the logic gate 15 has two
Just by taking the logic of the input, 2/3 of the width of one clock cycle
is the write signal, and the second flip-flop 1
Since the delay due to 1.12 is used as the data write hold time, the design is easy, and even if there is a change in the environment, there will be no timing difference, and the RAM access conditions will not be satisfied.

〔Example〕

An embodiment of the present invention will be described below with reference to the accompanying drawings.

FIG. 2 is a block diagram of a RAM access circuit according to an embodiment of the present invention, and FIG. 3 is a time chart of each signal in FIG.
A) to (F) correspond to points a%f in FIG.

In FIG. 2, the frequency of the crystal oscillator 5 is set to three times the operating cycle of the dedicated chip 3, and the clock of the MPU 1 is divided into n by an n frequency divider 6.

The output of this crystal oscillator 5 is input to the frequency divider circuit 4, which outputs a clock with a level of 1:2 as shown in FIG. 3(B). It is input to the clock terminals of pins 11, 12 and 13, 14 and the OR circuit 15.

Also, addresses and data with a width of one clock cycle.

The write instruction signal and the read instruction signal are also input to the flip-flops 11.12 and 14.13, respectively, and when they are clocked and output, the address and data are sent to (B) for the operation of the flip-flops, as shown in (E). ) is output at the LT@period width of the clock, which is slightly delayed from the clock shown in (F), and the read signal is also output with the clock shown in (F), which is slightly delayed from the clock shown in (B) due to the operation of the flip-flop. It is output with one cycle width.

Furthermore, due to the activation power of the flip-flop 14, as shown in (C), due to the operation of the flip-flop, a 0-level pulse with a one-period width slightly delayed from the clock shown in (B) is output, and is input to the OR circuit 15. do.

Furthermore, when the clock shown in (B) is also input to the OR circuit 15 and a logical sum is taken, the pulse width shown in (D) is 1 of the clock.
With a pulse of 2/3 of the period, the flip-flop 11.12
A write signal whose data write hold time corresponds to the delay due to the operation is output.

That is, this RAM access circuit has flip-flop 1
This is a synchronous circuit using 1 to 14, and the OR circuit 15 takes the logical sum of the two inputs, uses 273 of one cycle of the clock as a write signal, and uses the operation delay due to flip-flops 111 and 12 as the data write hold time. Therefore, the design is easy, and there is no timing difference between them due to changes in environmental conditions, and the RAM access conditions are not satisfied (
It won't happen.

Of course, a NAND circuit may be used in place of the OR circuit 15, and the circuit will operate in the same way if the output level of the frequency divider circuit 4 and the output level of the flip-flop 14 are inverted.

〔Effect of the invention〕

As described in detail above, according to the present invention, it is possible to obtain a RAM access circuit that is easy to design and that does not fail to satisfy RAM access conditions due to changes in environmental conditions.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of a RAM access circuit according to an embodiment of the invention, Fig. 3 is a time chart of each signal in Fig. 2, and Fig. 4 is a 1
FIG. 5 is a time chart showing the timing conditions for RAM access in one example. FIG. 6 is a block diagram of a conventional RAM access circuit. 2 is a time chart of each signal. In the figure, 1 is a processor, a microprocessor, and 2 is a RAM. 5 is a crystal oscillator, 6 is an n frequency divider, 11 to 14 are flip-flops, 15 is a logic gate OR circuit, 22 is a read instruction signal section, 23 is a write instruction signal section, 24.25.27 is a rising edge. 2 is a rising delay circuit, 24- is a falling delay circuit, a falling delay circuit, (B) (C) Eka of FF/4 (Vn Sugi 12-'s hayoshi time + Yatoki) 3 Figure

Claims (1)

[Claims] When the static RAM (2) is accessed by the dedicated chip (3) that performs a predetermined operation according to instructions from the processor (1), the 1:2 frequency ratio generated in the 3 frequency divider circuit (4) a first flip-flop (11) which uses the clock of the dedicated chip (3) as the clock of the dedicated chip (3) and inputs the address;
A second flip-flop (12) inputs data, and a third flip-flop (13) inputs a read instruction signal.
), the write instruction signal is input to each clock terminal of the fourth flip-flop (14), and the logic gate (15), and the output of the fourth flip-flop (14) is also input to the logic gate (15). , the output of the first flip-flop (11) is used as an address, the output of the second flip-flop (12) is used as data, the output of the third flip-flop (13) is used as a read signal, and The logic gate (15) generates a signal with a width of 2/3 of the clock period so that the input 1:2 clock and the output of the fourth flip-flop (14) both have the same sign level. A static RAM access circuit characterized in that it is output as a write signal.