KR910006685Y1 - Arbitration circuit for implementing multiprocessor using shared system bus - Google Patents

Abstract

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Description

Arbitration circuit for implementing a multiprocessor using a common system bus

1 is a multiprocessor system diagram using a common system bus according to the present invention.

2 is a block diagram of a system interface according to the present invention.

3 is a parallel priority selection scheme according to the present invention.

4 is a serial priority selection scheme according to the present invention.

5 is a detailed circuit diagram of the arbitration circuit 23 according to the present invention.

6 is a partial waveform diagram according to the present invention.

* Explanation of symbols for main parts of the drawings

20: address buffer 21: transceiver

22: control buffer 23: arbitration circuit

The present invention relates to a multiprocessing computer and a system using multiple processors, and more particularly to an arbitration circuit for implementing a multiprocessor system using a common system bus (BOS). .

Generally, microprocessors are cheaper, so multiprocessor systems that use multiple processors are better in price or functionality. Thus, there is a problem in that there is no arbitration circuit for implementing a common system bus for each communication in a conventional multiprocessor system.

Accordingly, an object of the present invention is to provide an arbitration circuit for implementing a common system bus method for communication between processors in a system using multiple microprocessors.

Hereinafter, the present invention will be described in detail with reference to the drawings.

1 is a multiprocessor system diagram using a common system bus according to the present invention.

2 is a configuration diagram of a system bus interface according to the present invention. The transceiver 21 selects the direction selection terminal S / R of the data transceiver by the address buffer 20 and the read / write signals R / W. ), A control buffer 22, and an arbitration circuit 23 for determining which processor is to use the system bus SB.

3 is a parallel priority selection scheme according to the present invention.

5 is a detailed circuit diagram of the arbitration circuit 23 according to the present invention.

4 is a serial priority selection method according to the present invention.

6 is a partial waveform diagram according to the present invention.

Based on the above-described configuration will be described in detail the present invention with reference to the drawings.

First of all, the common bus system uses processor A, B, C… as shown in FIG. The ROM, RAM, and input / output units of each N are connected to the local bus LB, and are connected to the system bus SB through the system bus interfaces 10, 11, and 12, respectively. The system bus SB is shared by each of the processors A, B, C ... N, and a global RAM and a global input / output unit are connected to the system bus SB for communication between the processors. have.

Since the system bus SB can only be used by one processor at a time, an arbitration circuit is needed to determine which processor will use this system boss SB. The system bus interface has an output enable terminal for the address buffer 20 and the control buffer 22 connected to the dress bus AB and the control bus CB as shown in FIG. Is the bus grant signal of the arbitration circuit 23 Enabled by In addition, the direction selection terminal S / of the data transceiver 21 connected to the data bus DB. ) Is the lead / light signal (R / Will be determined by Here, the arbitration circuit 23 may implement both the parallel priority selection method of FIG. 3 and the serial priority selection method of FIG. 4. First, the parallel priority selection method may be implemented using an encoder and a decoder. Can be.

In Figure 3, the required terminal of the arbitration circuit Input terminal of encoder To the decoder, and the output terminal of the decoder Enable input terminal of each intermediate circuit When connected to, each master is prioritized. Master 1 and Master 2 of the masters If the signal goes low, the output terminal is activated by the encoder operation. The input terminal of the decoder Enter The decoder decodes the output terminal. Becomes low and enables input terminal of master1 This master 1 can use the system bus (SB). Therefore, the priority is the highest of master 1 and the lowest of master N.

On the other hand, the serial priority selection scheme of FIG. The terminal is always enabled low, so it has the highest priority and the MasterN has the lowest priority.

Here, the difference between the parallel priority selection method and the serial priority selection method will be described. Even if you send a signal, priority is determined by the order in which it is connected to the encoder. The latter are daisy chained together from the higher priority master It is selected when there is no signal. Arbitration circuit 23 for implementing the common bus system by applying the parallel and serial priority selection scheme is shown in FIG. First bus request terminal A terminal is a terminal for enabling each processor to use a low state when using the system bus (SB), the waveform of Figure 6 (b). The terminal is a terminal that indicates to which processor the system bus (SB) is allocated. It is the same as the waveform of FIG. 6 (f), The terminal is an input terminal for enabling the arbitration circuit 23, as shown in FIG. 6 (d) waveform. Abitation clock terminal Is a clock that synchronizes each arbitration circuit with the same waveform as (a) in FIG. Is an output stage that enables an arbitration circuit in close proximity in the serial priority selection scheme. The terminals of the processor The output terminal that receives the signal and informs each arbitration circuit is the same as the waveform (c) of FIG. 6, and the clear terminal CLEAR is the terminal that makes the mediation circuit 23 initial. The terminal indicates that the processor is currently using the system bus (SB) and is the same as the waveform (e) of FIG. Looking at the operation of the arbitration circuit 23, the bus request terminal for the processor to use the system bus (SB) Set the signal to low. The low signal is input low to the input terminal J2 of the fifth flip flop 6, and the high signal, which is a signal inverted by the inverter 2, is input to the input terminal K2. Therefore, the output of the flip-flop 6 is next through the output terminal (Q2) Goes low at the falling edge of Output to the terminal. At this time Is high, the output of the AND gate 1 becomes low when the high signal becomes the low signal to the inverter 4, and the flip-flop (0, 0 becomes 0, 0 at the input terminals J1, K1 of the flip-flop 2). The output of 2) does not change. On the contrary If the terminal is low, this low signal becomes an inverted high signal through the inverter 4 and is input to the second input terminal of the AND gate 1. Also The high signal applied from the terminal is input to the first input terminal of the AND gate 1, and the inverted output terminal of the flip-flop 6 is input. The high signal output from is inputted to the third input terminal of the AND gate (1). Accordingly, the three signals inputted by the AND gate 1 are logically multiplied so that the resulting high signal is input to the input terminal J1 of the flip-flop 2.

Then, the input terminals J1 and K1 of the flip-flop 2 become 1,0, and the next High is output to the output terminal Q1 at the falling edge of the Outputs low. Since the output signal of the flip-flop 2 becomes a low signal through the inverter 3, The low signal is output to the terminal. In addition, the inverted output signal of the flip-flop 2 It is applied as a terminal and a low signal is applied to this terminal. In the above state While the signal is low, the processor can use the system bus (SB).

In the serial priority selection method of FIG. 4, the master 1 having the highest priority Since the signal is always low, If the signal is not enabled low, the signal applied to the flip-flop (6) input terminals (J2, K2) becomes 1,0 and the inverted output terminal Low is output. The low signal The low signal output by NAND gating the signal through the NAND gate 7 is Output to the terminal. The low signal By inputting to the terminal, if the higher priority master does not require the system bus, the next priority master can use the system bus (SB).

However, in the parallel priority selection method of FIG. When the signal is sent out, the decoder's output is routed to the Is applied to the terminal. This enables the master's arbitration circuitry so that the highest priority master can use the system bus (SB). When the processor currently occupying the system bus (SB) is finished When the signal is output high, the input terminal J2 of the flip-flop 6 goes high and the input terminal K2 goes low. The flip-flop 6 is applied to the clock terminal CLK. At the polling edge of the signal Since the signal is also high and the input terminals J1, K1 of the flip-flop 2 are 1, 1 On the falling edge of the signal, the output terminal (Q1, ) Is toggled. In other words The signal goes high The signal goes high so that the system bus SB can be used by the master of the next priority.

As described above, since an arbitration circuit for implementing a common system bus method is used for communication between processors in a system using a multiprocessor, there is an advantage of increasing multiprocessor performance at a low price.

Claims (2)

In a multiprocessor system using a shared system bus having an address buffer 20, a transceiver 21, and a control buffer 22 connected between a local bus and a system bus, in order to communicate between the processors in the multiprocessor. In order to implement a multiprocessor using a common system bus, characterized in that it consists of an arbitration circuit 23 that applies a parallel priority selection method or a serial priority selection method to determine which processor uses a system bus. Arbitration Circuit. The first flip-flop means according to claim 1, wherein the arbitration circuit (23) informs which processor a system bus is allocated to the processor according to an input signal synchronized by an ablation signal, or whether the system bus is used. A second flip-flop means for inputting a bus request signal to each arbitrator circuit while enabling a low state when each processor uses a system bus from the microprocessor in synchronization with the microprocessor; and the first and second flip-flops Arbitration circuit for implementing a multiprocessor using a common system bus, characterized in that the gate means for controlling the input signal of the means.