JPH0236540A - Mis transistor and manufacture of mis transistor - Google Patents

Abstract

PURPOSE:To prevent a reduction in a drive current by a method wherein a first conductivity type impurity region is provided in at least one of contact windows to a source region to form a wiring part at the source region and the electrical coupling of the source region with a first conductivity type region is performed. CONSTITUTION:First conductivity type impurity regions 21, which are used as, so to speak, contact parts to a first conductivity type semiconductor region 1, are provided in a contact holes 7 to a source region 3, in short, at a position where is surrounded with the region 3 and a contact to the region 1 under the region 3, that is, a substrate region is made through a wiring part 5 in this source region. That is, the contact regions 21 to the region 1 and the pattern of the wiring part 5 to these regions 21 are coincidentally formed and the interval X1 between the regions 21 and a gate part can be chosen in a large distance, that is, as X1>X0 because the consideration of the alignment of a contact region 9 with a contact hole 10 to the region 9 does not become necessary. Accordingly, the operation of a source can be performed effectively over the whole width of this region 3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a MIS type transistor, that is, an insulated gate type transistor, particularly a C type transistor in which a p-channel MIS type transistor and an n-channel MIS type transistor are formed on a common semiconductor substrate. - Concerning an MIS type transistor suitable for MIS and a method for manufacturing the MIS type transistor.

[Summary of the invention]

The present invention provides an impurity region of a first conductivity type within a source region of a second conductivity type provided in a semiconductor region of a first conductivity type, a so-called substraight region, at a position surrounded by this region when viewed in plan. A structure is adopted in which the source region is brought into contact with this first conductivity type semiconductor region by wiring to simplify manufacturing, improve reliability, and further reduce the occupied area.

(Prior Art) In a typical usage of a MIS type transistor, its source and a so-called substrate region of a channel forming portion are electrically contacted with each other and used at the same potential.

On the other hand, when it comes to semiconductor integrated circuits MIS-IC and C-MIS having ordinary MIS type transistors,
If each wiring or electrode needs to be led out from the same main surface of the conductive substrate, that is, from the upper surface side, the connection between the substrate region and the source region can also be made from the main surface of the semiconductor substrate where the gate electrode and the source and drain regions are arranged and formed. It becomes necessary to make contact with the connection wiring on the same side as the . As an example of a conventional MIS type transistor in this building, as shown in an enlarged plan view in FIG. A gate electrode (2) is formed on the substrate region with a gate insulating layer interposed therebetween, and on both sides thereof, a source region (3) and a drain region (4) of a second conductivity type, for example, an n-type, are formed with ions. It is formed by an injection method or the like. (5) and (6) are electrodes or wirings (hereinafter referred to as wirings) that are in contact with the source and drain regions (3) and (4), respectively.
These wirings (5) and (6) are formed by forming, for example, a plurality of contact holes (7) in the insulating layer formed to cover the source and drain regions (3) and (4), respectively. and (8) through each area (3) and (4)
It is made to contact ohmicly.

On the other hand, the source region (3) of the first conductivity type semiconductor region (1)
), a first conductivity type, that is, p-type, highly doped contact region (9) is formed by selective diffusion or the like in a position other than, for example, juxtaposed with this, and a similar contact hole (9) is formed in this by selective diffusion or the like.
1O) is opened and the wiring (5) is ohmically contacted to the contact region (9) through this contact hole (10) to connect the first conductivity type semiconductor region (1), that is, the substrate region and the source region (3). Electrical connections are made.

However, in the MIS transistor with such a configuration, the contact region (9) is located in the source region <
3), the overall occupied area becomes large, and there is a problem in that it impedes miniaturization of circuit elements in semiconductor integrated circuits (ICs) with high density.

[Problem to be solved by the invention]

The present invention aims to solve the above-described problem of increasing the occupied area due to electrical contact between the first conductivity type semiconductor region, that is, the substrate region and the source region.

For example, as shown in FIG. type semiconductor region +1), that is, a contact region (9) for the substrate m region
It is conceivable to take a structure in which the source region (3) is arranged when viewed in plan. In FIG. 4, the portion t3B corresponding to that in FIG. Referring to FIG. 6, the manufacturing method of this MIS type transistor will be explained by referring to FIG. 6. First, as shown in FIG. is formed by selective impurity doping, and the semiconductor substrate (11) constituting the first conductor region (11) of the first conductivity type is used up by this well region.

This semiconductor substrate (11) has a thick field insulation # (12) formed by thermal oxidation, for example, in the so-called field area other than the area where circuit elements such as MIS transistors are formed, and similarly, for example, in the element formation area. : A gate insulating layer (13) made of a thin oxide film made of # is formed, and a gate electrode (2) made of, for example, low resistivity polycrystalline silicon is formed on this.
) are formed in the desired pattern. Then, a first ion implantation mask II (15t) is formed partially over the element formation region surrounded by the field insulating layer (12) by, for example, coating a photoresist layer, pattern exposure, and development. Using this field insulating layer (12), the first ion implantation mask layer (151), and the gate electrode (2) as ion implantation masks, impurities of the second conductivity type (in this example, n-type) are ion-implanted to form the gate electrode. (2
) sandwiching the drain region (4) and the fourth region on the opposite side.
As shown in the figure, a partially cut out source region (3) is formed due to the presence of the first ion implantation mask layer (151).

As shown in FIG. 6B, the first ion implantation mask layer (1
5r) in the circuit element formation region, that is, the MIS transistor formation region in FIG. 6A.
A second ion implantation mask layer (152) is formed in the region where 5r) was not formed by, for example, coating a photoresist layer, pattern exposure, and development. That is, the source region (3) and drain region (4) explained in FIG.
) is formed using a second ion implantation mask Iti.
Covered by (152). Then, using the second ion implantation mask layer (152), the field insulating layer (12), etc. as a mask, impurities of the first conductivity type, for example, p type, are ion implanted to form a contact region (9).

As shown in FIG. 6C, the second ion implantation mask layer (1
52) and, for example, 5if2 was formed by the CV l) method (chemical vapor deposition method).
Then, as shown in FIG. 5, contact holes (7), (8), and (10) are formed on the source region (3), drain region (4), and contact region (9), respectively. Then, the wiring (5) is ohm-contacted across the contact holes (7) and (lO) to make contact or electrical connection between the source and the substrate, that is, the semiconductor region (1) of the first conductivity type; Further, ohmic contact of the wiring (6) is made to the drain region (4) through the contact hole (8).

These interconnections (5) and (6) can be formed simultaneously by, for example, full-surface vapor deposition and patterning by selective etching. Further, at the same time as forming these wirings (5) and (6), for example, an interlayer insulating layer (1
The gate wiring (16) can be formed together with each wiring (5) and (6) through the contact hole (15) drilled at the same time as the contact hole (7) +8> and (10) in 4). .

However, in the case of such a structure, the formation of a contact region (9) for the first conductivity type semiconductor region (11) and the drilling of a contact hole (10) for this contact region (9) are required. Considering positional deviation, it is necessary to form the contact region (9) in a relatively large area, and as shown in FIG. 5, the distance between the contact region (9) and the gate part is
Therefore, despite the existence of the source region (3) in this part, it does not substantially function as a source, and this reduces the effective gate width. As a result, a problem arises in that the current drive capability decreases.

The present invention also aims to solve the problem of narrowing the gate width, ie, the resulting reduction in current drive capability.

[Means to solve the problem]

In the present invention, as shown in FIG. 1 as an enlarged cross-sectional view, and as shown in FIG. area (i.e. substrate area) (1
), a first conductivity type impurity region (21) surrounded by this source region (3) is formed in a source region (3) formed of a second conductivity type impurity region provided in Conductivity type impurity 14! A structure is adopted in which the wiring (5) connected to the j region (21) makes contact with the first conductivity type semiconductor region +1) of the source region (3).

Further, in the present invention, as shown in the cross-sectional view of FIG.
jl (22), and the wiring (
5) may have a structure in which a first conductivity type impurity region (21) is provided in ohmic contact.

Further, in the present invention, the source region (3) is electrically connected to the wiring (5) in the above-described configuration.

In addition, in the manufacturing method of the present invention, impurities of the first conductivity type are introduced into at least one of the contact holes (7) provided on the source region (3), as shown in the second diagram. A type impurity region je2 (21) is formed in contact with the source region (3).

In addition, in the manufacturing method of the present invention, as shown in FIG. 3A, a contact hole (7) is etched to a position penetrating the source region (3) to form a groove (22), and a groove (22) is formed in this by etching the first conductivity type. An impurity region (21) of a first conductivity type is formed by introducing an impurity.

[Effect]

According to the present invention, the first contact hole (7) for the source region (3), that is, at the position surrounded by the source region (3), serves as a so-called contact portion for the semiconductor region (1) of the first conductivity type. Conductivity type impurity region (
21) to make contact with the semiconductor region (11, that is, the substrate region) of the source region (3), so to speak, it is a contact with the 14th electric type semiconductor region (1). ff
By forming the I region (2I) and the pattern of the wiring (5) corresponding thereto to match, the distance x1 between the region (2I) and the gate portion as shown in FIG. 1 is as shown in FIG. Since there is no need to consider the alignment between the contact region (9) and the contact hole (10) as described above, a large distance can be selected, that is, Xi >
This allows the source operation to be performed effectively over the entire width of the source area (3
Even though the contact portion to the first conductivity type semiconductor region (1), that is, the substrate region is provided in ), the effective source operation width is reduced, and therefore a reduction in drive current can be avoided. .

〔Example〕

A MISI transistor according to the invention and also a method of manufacturing a MES transistor according to the invention will now be described with reference to FIG.

As shown in FIG. 2A, the semiconductor region (substrate region) (1) itself is of a first conductivity type, for example, p-type, or
Alternatively, a semiconductor substrate (11) is provided which is selectively doped with impurities and has a semiconductor region (1) formed by a well region. This semiconductor substrate (11) has a field insulation JiJ (12) formed by selective thermal oxidation, for example, a thick oxide film, in the field area other than the J-route element formation area, that is, at least the MIS type transistor formation area. Then, on the area where the field insulating layer (12) is not formed, that is, on the area where the MIS transistor is formed, a thin gate insulating layer (13) of 5i (h insulating Il) is formed, for example, by thermal oxidation, and on top of this, for example, A gate electrode (2) made of low resistivity polycrystalline silicon or the like is formed in a band shape.

And field insulation! (12), gate electrode (2)
using the thin gate insulator as an ion implantation mask (13)
A source region (3) and a drain region (4) are formed by ion-implanting an impurity of a second conductivity type, for example, an n-type, into the portion where only the second conductivity type is formed.

As shown in FIG. 2H, for example, j-
An interlayer insulating layer (14) is deposited over the entire surface by CVD or the like, and source and drain regions (3) and (4) are formed on this layer.
Contact holes (7) and (8) are selectively formed on the top.

As shown in FIG. 2C, an ion implantation mask layer (24) is formed to open the contact hole (7) on the source region (3) and close the contact hole (8) on the drain region (4). For example, it is formed by photoresist coating, pattern exposure, and J3J image processing.

As shown in the second diagram, impurities of the first conductivity type, that is, p-type, are ion-implanted at a high concentration through the contact hole (7) using the ion implantation mask layer (24) as a mask, and the impurity region of the first conductivity type ( 21) is formed.

As shown in FIG. 2E, the ion implantation mask 1m described above is
(24) and each contact hole (7) and field)
For example, 8! is ohmic to the region (21) and the drain region (4) through each. Wirings (5) and (6) made of an AI gold monolayer formed by vapor deposition and patterning.
Form the adhesion. In this case, the wiring (5) passes through the first conductivity type impurity region (21) to the first conductivity type semiconductor region (
1) That is, it is electrically connected to the substrate region. In this case, the impurity vA region 21) of the first conductivity type and the source region (3) are each formed by a highly doped region, and the withstand voltage of the p-n junction between them is made sufficiently low, so that Specifically, the source region (3) is brought into contact with the wiring (5) through the impurity region (21) of the first conductivity type. That is, the source electrode for this source region (3) is shared by the wiring (5).

Another example of the manufacturing method of the present invention will be described with reference to FIG. 3. In this example as well, the contact hole (7) was opened by following the same steps as explained in FIGS. 2A to 2C. After forming the ion implantation mask IN (24), etching is performed across the source region (3) in the semiconductor substrate (11) through the contact hole (7) to form a trench (22). Then, through the contact hole (7), this groove (
22) by performing ion implantation into the bottom of the first impurity region (
21) is formed.

Next, as shown in FIG. 3B, wirings (5) and (6) are formed in the same manner as explained in FIG. is in ohmic contact with both the source region (3) and the impurity region (21) of the first conductivity type through the conductive layer to connect the first conductivity type region (1) and the source region (3) to each other and to connect the source region (3) with the source region (21). The bridge is derived.

In addition, in the illustrated example, the n-type source and drain regions <3)
An example of an n-channel MIS transistor in which
- In the transistor, the conductivity types of each part shown in FIGS. 1 to 3 are selected to be opposite conductivity types.

In addition, in the illustrated example, one MIS is provided on the semiconductor substrate (11).
In this case, a plurality of p-channel and n-channel MIS type transistors, for example, can be formed, and in this case, one of the transistors is doped with an impurity of a conductivity type different from that of the semiconductor substrate (11). A MISI-transistor of one conductivity type may be formed in a semiconductor region (1) consisting of a so-called well region into which is selectively introduced.

In addition, in the example shown in FIG.
) and for each contact hole (7) a first
A 4-electrode type impurity region (21) is provided and a wiring (5) is connected to these.
), but in some cases, one contact hole (7) may be provided, or at least one contact hole (7) may be formed in a plurality of contact holes (7). ), a first conductivity type impurity region (21) is formed in the other part, and a first conductivity type impurity If! The source region (31) is directly exposed through the contact rule (7) without providing the J region (21), and the wiring (5) is formed across each contact hole (7). You can also.

〔Effect of the invention〕

As described above, according to the present invention, the impurity region (21) of the first conductivity type is provided in at least one of the contact windows (7) for the source region (23), and the wiring (5) is formed there. As a result, the source region (3) and the first conductivity type region (0) are electrically connected, so as explained in FIG. In this case, the area occupied by the contact region (91) does not increase as in the case where the contact region (91) is provided, and the contact region (9) can be cut out as a part of the source region (3) as explained in FIG. As in the case where the contact region (9) and the gate electrode (2) are formed as shown in FIG. Such inconveniences can be avoided, and a MIS transistor that can be driven with a large current, is highly reliable, occupies a small area, and has a high integration density can be formed.

[Brief explanation of the drawing]

FIG. 1 is an enlarged plan view of an example of a MIS transistor according to the present invention, FIG. Another enlarged cross-sectional view of each step of the manufacturing method of the present invention, FIG. 4 is an enlarged plan view of a conventional MIS transistor, and FIG. The enlarged plan view and FIGS. 6A to 6C are respectively enlarged cross-sectional views along lines of each step of the manufacturing method of the example. (1) is a semiconductor region of the first conductivity type, (2) is a gate electrode, (3) is a source region, (4) is a drain region, (7)
, (8) is a contact hole, (11) is a semiconductor substrate, (21) is an impurity region of the first conductivity type, (13) is a gate insulation), and (22) is a groove. Agent Ito Sadado Matsukuma Hidemori 2γ-to-den a minute put-den I&un#d 1 Kuyurimi σ〕I charge = no ifhu) nxalf
3 Fig. 3 Process 10 of the manufacturing method of the present invention Fig. 2 Plane 1a of the enviable M15 7

Claims (1)

[Claims] 1. In a source region formed by a second conductivity type impurity region provided in a first conductivity type semiconductor region, a first conductivity type impurity region surrounded by the source region. formed,
A MIS type transistor in which a contact between the source region and the semiconductor region of the first conductivity type is formed by a wiring connected to the impurity region of the first conductivity type. 2. The MIS transistor according to claim 1, wherein the impurity region of the first conductivity type is formed at the bottom of a trench penetrating the source region. 3. The MIS type transistor according to claim 1, wherein the wiring and the source electrode are electrically connected. 4. Injecting an impurity of the first conductivity type into at least one of the contact holes formed on the source region in the source region formed of the impurity region of the second conductivity type provided in the semiconductor region of the first conductivity type. M characterized by having a step of introducing
Manufacturing method of IS type transistor. 5. forming an etching groove reaching the semiconductor region in at least one of the contact holes formed on the source region formed of the second conductivity type impurity region provided in the first conductivity type semiconductor region; A method for manufacturing an MIS transistor characterized by introducing an impurity of a first conductivity type.