JPH0235820A - Static complementary type semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To minimize the dislocation of the logical gate circuit change voltage of a static complementary semiconductor integrated circuit and to reduce an area by setting the gate width of the (n) pcs. of serial transistors from a conventional (n)-fold to n/2-fold or below. CONSTITUTION:In the circuit of 4 input NAND gates, the gate width of a P channel transistor 1 of an inverter circuit (a) is WP, the gate width of an N channel transistor 2 is made into WN and the 1/2 of a change voltage supply voltage is obtained, N channel transistors 7-10 go to 4WN/2.2, the WN goes to 4 pieces serially and goes to 4XWN/2 or below. Since P channel transistors 3-6 cannot be serial, the WP is obtained. The change voltage goes to approximately 1/2 as much as the supply voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a static complementary semiconductor integrated circuit.

2. Description of the Related Art Conventional static complementary semiconductor integrated circuits are based on the gate widths of N-channel and P-channel transistors whose transition voltage is 1/2 of the power supply voltage in an inverter circuit. The gate width of n N-channel transistors connected in series between the output and the ground potential in the logic gate circuit is n times that of the n-channel transistor in the inverter circuit.

Similarly, the gate width of n P-channel transistors connected in series between the output and the power supply potential is set to P of the inverter circuit.
It was set to be n times as large as the channel transistor.

FIG. 8 is a circuit diagram of an inverter circuit and an input NAND gate, in which a P-channel transistor 81. Since n N-channel transistors are connected in series in the n-input NAND gate in (b) with respect to the gate width W, , WN of the N-channel transistor 82, the gate width WN of the N-channel transistor 2 in the inverter circuit in (a) is It is n times larger than

Problems to be Solved by the Invention However, the above configuration is effective when the gate length is 2 μm or more (which can be approximated by a simple model using conventional gate-to-substrate capacitance). Due to the miniaturization of transistors, the gate length has become shorter, and the electric field generated by the voltage between the drain and source has become stronger. As a result, the mobility is saturated due to the electrons flowing under the gate, and the gate voltage and drain-source current also have square-law characteristics. It is close to a first-order characteristic. As a result, the conventional model can no longer approximate it, and when transistors are connected in series, the voltage between the drain and source of each transistor is divided and the current decreases due to the voltage drop between the drain and source of each transistor. It has become a little.

As a result, in conventional logic gate circuits, the transition voltage is shifted to the ground potential side when N-channel transistors are connected in series, as the drive capability of the N-channel transistor increases, and to the power supply potential side, when P-channel transistors are connected in series, as the drive capability of the N-channel transistor decreases. This had the problem of misalignment.

Furthermore, each input of a logic gate circuit rarely changes at the same timing, and each input is input with a delay. As a result, other inputs are determined at the timing when the last signal change is input. As a result, in a NAND gate or a NOR gate, when the output changes, all transistors except the transistor to which the last signal is input are in the on state. As a result, compared to the case where the inputs change simultaneously, the current value at the gate potential of about 1/2 of the power supply voltage, which affects the transition voltage, increases, so the transition voltage also shifts.

Figure 9 is a circuit diagram of a 4-person NAND gate, and Figure 10 is a circuit diagram of a 4-person NAND gate.
This figure shows the shift in transition voltage of a human-powered NAND gate. It can be seen that the transition voltage is about 1.5V. Figure 11 is a circuit diagram of a 4-person powered NOR gate, and Figure 12 shows the shift in transition voltage of a 4-person powered NOR gate.
．． It is about 2V. FIG. 13 is a comparison diagram of current when one N-channel transistor is used, when two N-channel transistors are connected in series, and when both are changed simultaneously.

SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide a static complementary semiconductor integrated circuit in which the shift in transition voltage of a logic gate circuit is reduced.

Means for Solving the Problems The present invention is designed to be smaller than n/2 times the size of the inverter circuit based on the gate width of n transistors connected in series in order to reduce the shift in the transition voltage of the logic gate circuit. It is a static complementary semiconductor integrated circuit.

The present invention uses the above-described design method to reduce the gate width of n transistors connected in series from n times to n/2 times the conventional width, thereby reducing the transition voltage r error and further reducing the gate area. It is something to do.

Embodiment FIG. 1 is a circuit diagram of a four-man power NAND gate, which is the first embodiment of the present invention. WN, and the transition voltage is 1/1 of the power supply voltage.
When set to 2, N-channel transistor, 7 to 10 is 4W
N/2.2, so 4 WNs are connected in series, but 4×W
It is less than N/2. P-channel transistor 3~
6 cannot be connected in series, so it becomes W.

FIG. 2 shows the result of DC analysis of the circuit shown in FIG. 1, and the transition voltage is approximately 1/2 of the power supply voltage.

FIG. 3 is a detailed explanatory diagram of the present invention. Solid line 1 shows the transition voltage 1/2 of the power supply voltage when a signal is applied to the input of each transistor connected in series according to actual measurement simulation.
This is a plot of the optimum gate width that minimizes the maximum delay time of each input and reduces the deviation from the value of . Solid line 2 plots the gate width of a transistor according to the prior art. Solid line 3 is a plot of the gate width that is N/2, which is the upper limit of the gate width according to the present invention, and the deviation from the optimal gate width is smaller than that of the conventional one. Also, the area of the logic gate circuit is The gate capacitance of the transistor is also reduced to about 70% of that of the conventional one, resulting in a high-speed logic gate circuit.

Power consumption is also reduced.

FIG. 4 is a circuit diagram of a four-power NOR gate which is an embodiment of the present invention shown in FIG.
Using the above W, the gate width of is 4W xi/2=2W
,,N channel transistors 45 to 48 are not connected in series, so they become WN.

FIG. 5 shows the results of DC analysis of a four-man power NOR gate according to the second example of the present invention, and it can be seen that the transition voltage is approximately 1/2 of the power supply voltage. Also, the gate area is smaller than that of the conventional 56
%.

FIG. 6 shows a three-man-powered 0RN in the embodiment of FIG. 3 of the present invention.
It is an AND gate. P-channel transistor 61.6
2 has two side rows, so the gate width is 2/2xW,
=W, and since the P-channel transistor 63 is not connected in series, the gate width is W. The N-channel transistors 64 and 66 are arrayed on two sides, and the gate width is 2/2.
2×WN=WN. Also, N-channel transistor 6
5.66 are also arranged on two sides, and the gate width is 2/
2XW,=W. FIG. 7 shows the results of DC analysis of the three-manpower 0RNAAND gate according to the third embodiment of the present invention, and it can be seen that the transition voltage is approximately 1/2 of the power supply voltage. Furthermore, the area can be reduced to about 58% of the conventional size.

As described in detail, according to the present invention, it is possible to reduce the shift in logic gate circuit transition voltage of a static complementary semiconductor integrated circuit compared to conventional designs, and also to reduce the area. It is effective in realizing integration, integration, and creation of multi-input gates, and its practical effects are great.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of a four-man powered NOR gate, which is the first embodiment of the present invention, and Figure 5 is a circuit diagram of a four-man powered NOR gate, which is the second embodiment of the present invention. The output characteristic curve diagram, FIG.
The circuit diagram of the RNAAND gate, Figure 7 is the same three-man-powered 0RNA
Input/output characteristics characteristic diagram of DC analysis of ND gate, Figure 8 is a circuit diagram of a conventional n-input NAND gate, Figure 9 is a 4-manpower NAND gate.
The circuit diagram of the AND gate, Fig. 10 is the input/output characteristic curve diagram of the DC analysis of the same 4-man-power NAND gate, Fig. 11 is the circuit diagram of the 4-man-power NOR gate, and Fig. 12 is the DC analysis of the 4-man power NOR gate. Figure 13 is an input/output characteristic diagram for the case of one N-channel transistor and for the case of two side arrays. 1...P channel transistor, 2...
- N channel transistor, 3 to 6...P channel transistor, 7 to 10...N channel transistor. Name of agent: Patent attorney Shigetaka Awano and 1 other person t, S~6
-P+Yanel transistor (f-to-to-w) Figure 2. Number of transistors in the Iji column 4I-sonP-)? Figure 61 - Otsu 3 64 - Otsu 6 --- P+Yanel transistor (Tate width Wp) N+Y Nel transistor (Tate width WN) [V] ? 8~9H-P+Renel transistor? 72~? IE-N 4- t-Half-transistor voltage [V] Output voltage [V] Cause Figure 11 JIB~llll- 1172~1II5 P+v low-level transistor Janel transistor

Claims (1)

[Claims] Based on the gate width of N-channel transistors and P-channel transistors in an inverter circuit with a standard transition voltage, the gate width of N-channel transistors in a logic gate circuit in which n transistors are connected in series between the output and the ground potential. The gate width of n P-channel transistors connected in series between the output and the power supply potential should be n/2 times or less than the N-channel transistor of the inverter circuit. A static complementary semiconductor integrated circuit comprising a logic gate circuit.