JPH07101843B2 - Static complementary semiconductor integrated circuit - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a static complementary semiconductor integrated circuit.

2. Description of the Related Art Conventional static complementary semiconductor integrated circuits are based on the gate widths of N-channel and P-channel transistors whose transition voltage is half the power supply voltage in an inverter circuit.
In the logic gate circuit, the gate width of n N-channel transistors connected in series between the output and the ground potential is n times the n-channel transistor of the inverter circuit. Similarly, the gate width of n P-channel transistors connected in series between the output and the power supply potential is n times the P-channel transistor of the inverter circuit.

FIG. 8 is a circuit diagram of the inverter circuit and the input NAND gate. The transition voltage of the inverter in (a) is 1/2 of the power supply voltage.
_N- input NAN of (b) with respect to the gate widths W _P and W _N of the P-channel transistor 81 and N-channel transistor 82 such that
In the D gate, since N N-channel transistors are connected in series, the gate width W _N of the N-channel transistor 82 of the inverter circuit of FIG.

However, the above-mentioned configuration is effective when the gate length is as long as 2 μm or more and can be approximated by a simple model based on the conventional gate-substrate capacitance. The miniaturization of the transistor shortens the cage length, and the electric field generated by the voltage between the drain and source becomes stronger.As a result, electrons flowing under the gate saturate the mobility and the gate voltage and drain source current are squared. The characteristics are close to the primary characteristics. As a result, the model cannot be approximated by the conventional model, and when the transistors are connected in series, the current between the drain and source of each transistor is reduced due to the voltage drop between the drain and source as in the past. It's getting less.

As a result, in the conventional logic gate circuit, the transition voltage is shifted to the ground potential side when the N-channel transistor is in series and the driving capability of the N-channel transistor is large, and to the power supply potential side when the P-channel transistor is in series, the driving capability of the P-channel transistor is large. Had the problem.

Further, each input of the logic gate circuit rarely changes at the same timing, and each input is input with a delay. As a result, at the timing when the last signal change is input, other inputs are fixed. This results in NAND gates and NO
In the R gate, when the output changes, all the transistors are turned on except the transistor to which the last signal is input. As a result, as compared with the case where the inputs change at the same time, the transition voltage deviates because the current value at the gate potential which is about half the power supply voltage that affects the transition voltage increases.

Figure 9 is a circuit diagram of a 4-input NAND gate, and Figure 10 is a 4-input NA.
It shows the shift of the transition voltage of the ND gate. It can be seen that the transition voltage is about 1.5V. Fig. 11 shows the circuit diagram of the 4-input NOR gate, and Fig. 12 shows the shift of the transition voltage of the 4-input NOR gate, which is about 3.2V. Thirteenth
The drawing is a comparison diagram of currents when one N-channel transistor and two N-channel transistors are connected in series and one input change and two changes simultaneously.

In view of the above point, the present invention has an object to provide a static complementary semiconductor integrated circuit in which the shift of the transition voltage of the logic gate circuit is reduced.

Means for Solving the Problems According to the present invention, in order to reduce the shift of the transition voltage of a logic gate circuit, the gate width of n transistors in series is 1 times or more and n / 2 times or less that of a reference inverter circuit. It is a static complementary semiconductor integrated circuit designed in size.

Action The present invention uses the above-described design method to reduce the gate width of n transistors in series from n times as much as the conventional gate width to n / 2 or more.
By making it less than or equal to twice, the shift of the transition voltage is reduced,
Furthermore, the gate area is reduced.

Practical Example The static complementary semiconductor integrated circuit of this embodiment is based on the gate widths of N-channel and P-channel transistors whose transition voltage is half the power supply voltage in the inverter circuit.

Figure 1 is a first embodiment is a circuit diagram of a 4-input NAND gate as an example an inverter circuit of a P gate width of the channel transistor 1 W _P of (a), the gate width of N-channel transistor 2 W of the present invention _{If N} and the transition voltage is 1/2 of the power supply voltage, four N-channel transistors 7-10 are connected in series, so the gate width of each transistor 7-10 that minimizes the transition voltage shift is measured. From 4W _N /2.2 to 4 × W
_N / 2 or less. P-channel transistors 3-6
Is not in series, so it becomes W _P.

FIG. 2 shows the result of the DC analysis in the circuit shown in FIG. 1, and the transition voltage is almost half of the power supply voltage.

FIG. 3 is an explanatory diagram of the basis of the present invention. The solid line 1 indicates the power supply voltage of the transition voltage when a signal is applied to the input of each transistor in series by actual measurement and simulation.
This is a plot obtained by finding an optimum gate width that minimizes the maximum delay time of each input with a smaller deviation from the value of 1/2. The transistor indicated by the solid line 1 has a gate length in which the mobility of electrons is saturated by the high electric field between the drain and the source, and the gate voltage and the drain-source current are close to the first-order characteristic due to the squared characteristic. The solid line 2 is a plot of the gate width of a conventional transistor. The solid line 3 is a plot of the gate width that is N / 2, which is the upper limit of the gate width according to the present invention, and the deviation from the optimum gate width is smaller than that of the conventional one. Further, the lower limit of the gate width according to the present invention is at least 1 time that of the reference inverter circuit. The rationale for this one-fold or more is explained below. As shown in FIG. 13, the current value of the transistors connected in series is closer to the transition voltage but is not larger than that of a single transistor having the same gate width. Therefore, the gate width that minimizes the shift of the transition voltage does not become smaller than the gate width of the reference transistor that constitutes the inverter. Therefore, the lower limit of the gate width is the minimum gate width of the reference transistor.
As described above, the gate width of the present invention is set to 1 time or more and n / 2 times or less that of the reference inverter circuit. If the solid line 3 is used for designing, the area of the logic gate circuit can be reduced to about 70% of that of the conventional one, and the gate capacitance of the transistor can be reduced, resulting in a high-speed logic gate circuit. In addition, power consumption is also reduced.

FIG. 4 is a circuit diagram of the 4-input NOR gate according to the embodiment of FIG. 2 of the present invention. The gate width of the P-channel transistors 41 to 44 is 4W _P × 1/2 = 2W _P when the above W _P is used, Since the N-channel transistors 45 to 48 are not in series, they become W _N.

FIG. 5 shows the result of DC analysis of the 4-input NOR gate according to the second case of the present invention, and it can be seen that the transition voltage is almost 1/2 of the current voltage. Also, the gate area can be reduced to about 56% of the conventional level.

FIG. 6 is a 3-input ORNAND in the embodiment of FIG. 3 of the present invention.
It is a gate. Since the two P-channel transistors 61 and 62 are in series, the gate width is 2/2 × W _P = W _P , and P
Since the channel transistor 63 is not in series, the gate width is
It becomes W _P. Two N-channel transistors 64 and 66 are connected in series, and the gate width is 2/2 × W _N = W _N. Two N-channel transistors 65 and 66 are also in series with each other, and the gate width is 2/2 × W _P = W _P. FIG. 7 shows the result of DC analysis of the 3-input ORNAND gate according to the third embodiment of the present invention, and it can be seen that the transition voltage is almost half the power supply voltage. Also, the area can be reduced to about 58% of the conventional size.

As described above, according to the present invention, the shift of the logic gate circuit transition voltage of the static complementary semiconductor integrated circuit can be made smaller and the area can be made smaller than that of the conventional design. It has the effect of realizing miniaturization, integration, and creation of multiple input gates, and its practical application effect is large.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a 4-input NAND gate according to the first embodiment of the present invention, FIG. 2 is an input / output characteristic curve diagram of DC analysis of a 4-input NAND according to the same embodiment, and FIG. FIG. 4 is a circuit diagram of a 4-input NOR gate according to the second embodiment of the present invention, and FIG. 5 is a DC input / output characteristic curve diagram of the 4-input NOR gate.
FIG. 6 is a circuit diagram of a 3-input ORNAND gate according to a third embodiment of the present invention, FIG. 7 is a characteristic diagram of input / output characteristics of DC analysis of the 3-input ORNAND gate, and FIG. 8 is a conventional n-input NAND gate. Circuit diagram of Fig. 9, Fig. 9 is a circuit diagram of 4-input NAND gate, Fig. 10
The figure is the input / output characteristic curve diagram of DC analysis of the same 4-input NAND gate, Fig. 11 is the circuit diagram of 4-input NOR gate, and Fig. 12 is the same figure.
FIG. 13 is an input / output characteristic curve diagram of direct current analysis of the input NOR gate, and FIG. 13 is an input / output characteristic diagram of one N-channel transistor and two N-channel transistors connected in series. 1 ... P-channel transistor, 2 ... N-channel transistor, 3-6 ... P-channel transistor, 7-10
... N-channel transistor.

Claims (1)

[Claims] 1. A gate width of an N-channel transistor and a P-channel transistor which is composed of a transistor having a gate length in which electron mobility is saturated by a high electric field between a drain and a source and which constitutes an inverter circuit having a standard transition voltage. , The gate width of the n-channel N-channel transistors connected in series between the output and the ground potential in the logic gate circuit is 1 times or more and n / 2 times or less that of the N-channel transistor of the inverter circuit. age,
The logic gate circuit is configured such that the gate width of n P-channel transistors connected in series between the output and the power supply potential is at least 1 time and not more than n / 2 times that of the P-channel transistor of the inverter circuit. Static complementary semiconductor integrated circuit.