JPH0235584U - - Google Patents

Description

[Brief explanation of drawings]

Figure 1 is a signal transmission system diagram showing the basic configuration of the device of the present invention, Figure 2 is a connection diagram showing the configuration of an example of the modulation section in the invention, and Figure 3 is a diagram showing the configuration of an example of the demodulation section in the invention. A connection diagram, FIG. 4 is a time chart for explaining the operation of the present device, and FIG. 5 is a signal transmission system diagram showing an example of the conventional device. DESCRIPTION OF SYMBOLS 1... Video signal generation section, 3... Video signal display section, 4... Modulation section, 5... Transmission path, 6... Demodulation section, 7... Double dot clock signal generation section, 8...
...Dot clock signal conversion unit, 9...Exclusive OR unit, 10...Delay unit, 11...Current differential type driver, 12...Current differential receiver, 13...First sampling unit, 14... Conversion section, 15, 16
...Second and third sampling section, 17...Exclusive OR section, 18...Fourth sampling section, 19...
...Double dot clock signal generator.

Claims (1)

[Scope of utility model registration request] A video signal generator 1 inputs and modulates the video signal output from the generator 1, and outputs it to the transmission line 5. A modulator 4 inputs the signal transmitted from the transmission line 5 and demodulates it. It consists of a demodulation section 6 and a video signal display section 3 which inputs the signal demodulated by the demodulation section 6 and displays a video signal. a double dot clock signal generator 7 that generates a certain double dot clock signal;
A dot clock signal converter 8 converts the output signal of the generator 7 into a dot clock signal of 1/2 the frequency, and exclusive logic inputs the output signal of the converter 8 and the video signal and modulates the video signal with the dot clock signal. The output signal of the logical sum section 9 and the output signal of the double dot clock signal generation section 7 are inputted to the sum section 9, and the output signal of the logical sum section 9 is sampled with the double dot clock signal and delayed by the double dot clock. section 10, and a current differential type driver 11 which inputs the output of this delay section 10 as a signal and outputs a current differential signal, and the demodulator 6 inputs the current differential signal and outputs a current differential signal. a current differential receiver 12 that outputs a signal with the same phase as the output signal of 9; a double dot clock signal generator 19 that generates a double dot clock signal; and an output signal of the receiver 12 and an output signal of this generator 19. is input and the output signal of the receiver 12 is generated by the generator 19.
a first sampling section 13 that samples the output signal of the dot clock signal, a converting section 14 that inputs the output signal of the double dot clock signal generation section 19 and converts it into a dot clock signal of half the frequency, and a receiver 12.
a second sampling section 15 that receives the output signal of the converter 14 and the output signal of the converter 14 and samples the output signal of the receiver 12 with the output signal of the converter 14;
a third sampling section 16 that samples the output signal of the receiver 12 with a signal of opposite polarity to that of the second sampling section 15; and second and third sampling sections 1
Exclusive OR unit 1 inputting output signals of 5 and 16
7, the output signal of the first sampling section 13 and the output signal of this OR section 17 are input, and the output signal of the first sampling section 13 is sampled with the output signal of this OR section 17, and the video signal of the modulation section 4 is inputted. A video signal transmission device comprising a fourth sampling section 18 that outputs a video signal similar to the video signal.