JPH0235576A - Detection of pattern fault - Google Patents

Abstract

PURPOSE:To high speedily inspect a fault with high reliability without receiving the influence of some fluctuation of an object pattern by detecting the pattern under a non-contact state using an optical means and examining the connecting relation between pads. CONSTITUTION:The optical image of the pattern to be inspected is converted into an electric signal in an image pickup device 21, the output of the device 21 is inputted through a binarizing device 22 to a connectivity processor 23, and connection data are created. In order to know a pad number when connectivity processing is to be executed, the corresponding relation between a pad position and the pad number is previously created from design information and stored in a pad position data memory 27. The created connection data are stored in a connection data memory 24. On the other hand, design data are previously created from the design information of a circuit pattern and stored in a design data memory 26. After the connection data of all the circuit patterns are created, fault detecting algorithm is executed by a processor 25.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method for inspecting patterns such as printed circuit patterns, and in particular to pattern defect detection suitable for non-contact and high-speed detection of defects related to electrical continuity. Regarding the method.

[Background of the invention]

Conventionally, the method of testing the electrical continuity of a printed circuit pattern is to memorize specific pad positions in advance, bring contact bottles into contact with them, apply a voltage between the two contact bottles, and check the presence or absence of current flowing, its size. There were devices that could detect continuity/disconnection and separation/short circuit. In this method, the contact bottle is brought into direct contact with the circuit pattern, so inspection reliability is low due to fluctuations in contact resistance.If the contact bottle becomes worn or damaged, it must be replaced, and the circuit pattern may be damaged by contact. In the worst case, the pattern may be damaged.In addition, if the circuit pattern is partially thin or the adjacent circuit pattern is closer than the specified value, the current It is conceivable that concentration of electric fields, etc., may have an adverse effect on circuit operation or long-term circuit reliability, but it is extremely difficult to detect these defects using this method.

Another conventional method for inspecting printed circuit patterns is to detect an optical image of the pattern in a non-contact manner.

This method includes methods that directly compare an inspection pattern with a design pattern, methods that directly compare two test patterns, and methods that detect the presence or absence of a pattern in a particularly important specific part of a pattern obtained from design information. There is. In these methods, the defect judgment criterion is whether there is a pattern with the correct size at a predetermined position, and in many printed circuit patterns where only conduction relationships and large pattern size differences are considered defects. There is a possibility of incorrectly determining a defect as a defect, which poses a major problem in terms of inspection efficiency.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art and to provide a method for detecting pattern defects such as disconnections, short circuits, small pattern widths, and small pattern intervals in printed circuit patterns in a non-contact and high-speed manner.

[Summary of the invention]

In order to achieve the above object, a pattern defect detection method according to the present invention converts an optical image of a pattern into an electrical signal, binarizes the electrical signal, and then converts an optical image of a pattern into an electrical signal, binarizes the electrical signal, and Examine the connection relationship, generate connection data that represents the connection relationship as a pair of numbers assigned to those points, create it from that connection data and design information, and cycle through the numbers assigned to the points in the connection relationship. In an advantageous embodiment of the present invention, the gist of which is to determine and detect pattern defects by comparing design data generated in a list structure, electrical signal binarization processing and connection data generation processing are performed. During this process, reduction processing and/or enlargement processing of the binarized pattern is added, and pattern defect judgment/detection is performed from the judgment results obtained through these processes, or from the judgment results obtained through these processes. The judgment results obtained without going through the process are also taken into consideration.

In order to detect the electrical continuity of a circuit pattern without contact, considering that the pattern exists on a plane, it is possible to detect the optical image of the pattern and separate and extract only the conductor part as a binary pattern. Apply connectivity processing to
This can be achieved by examining the connection relationship on the binary pattern between the two pawls and nodes, and by comparing this with the correct connection relationship obtained from the design information, it becomes possible to inspect for disconnections and short circuits.

In addition, when a pattern P exists as shown in Fig. 1, the pattern width and the pattern interval are reduced by reducing the binary pattern (Fig. 2) and enlarging it (Fig. 3), respectively. If there is a disconnection or short circuit, these can be detected and inspected. In FIG. 1, a indicates a location where the pattern width is small, and b indicates a location where the pattern spacing is small. These locations appear as disconnections in FIG. 2, which shows the pattern that has undergone the reduction process, and as short circuits in FIG. 3, which shows the pattern that has undergone the enlargement process.

The present invention uses output data of connectivity processing as a pair of a pad of interest and a pad connected to it, and also uses connection relationship data from design information as a circular list structure (hereinafter in this specification, the former is referred to as connection data). , the latter is called design data.) This is a method of checking by extracting pair data one by one from the connection data and checking whether each pad exists on the circular list of design data. This makes it possible to significantly reduce the amount of data and amount of processing.

First, connection data will be explained in more detail. Fourth
The diagram shows connection data. As shown in the figure, the data is a pair of a pad number of interest and a parent pad number in a connected relationship. The pad number is a number assigned to a pad on a circuit pattern whose conductivity, etc., needs to be tested according to a specific rule.

For example, as shown in FIG. 5, the numbers are sequentially numbered from top to bottom and from left to right, starting from 1. Out of the pad
A pad is a specific pad representing a connected individual circuit pattern. The method for determining the parent pad is, for example,
A specific criterion may be set, such as the one located at the upper leftmost position on the circuit pattern. Table 1 shows connection data using the pattern of FIG. 6 as an example. In the figure, the parent pads are pad numbers 1 and 4, and as shown in Table 1, the storage order (address) of the pad number pairs is arbitrary.

Table 1 Next, the design data will be explained in more detail. The design data is a data structure expressed as a circular list consisting of an address, that is, a pad number, and the first pad number that appears when the number representing that number is changed in a circular manner. have.

Each circular list shows the connection relationships of all pad numbers on one connected circuit pattern.

Here, the connection relationship means only a connection relationship between pads, and does not indicate a geometric positional relationship.
The order of ranking will be from the youngest number to the oldest number.

Table 2 shows design data using the pattern shown in FIG. 6 as an example.

Table 2 A method for detecting defects by comparing the connection data explained above with design data will be described. In order to store intermediate data of processing, 2-bit attribute data is added to each pad number (address) of the design data. The algorithm for this is shown below.

defective algorithm Stage 1. Clear all attribute data to 0.

Stage 2. Compare all connection data with design data using the following procedure and store the results in attribute data. If the left and right pad numbers of the connection data are the same, attribute data = 1
, If not, it goes through the circular list on the design data and checks whether the right pad number (parent pad number) of the connection data is on the design data. If there is, attribute data 2
, otherwise, attribute data=3, stage 3. The attribute data of each circular list of the design data is examined, and defects are determined according to the following criteria.

If there is one or more case 1.0 → The pad is defective (no pad) If there is one case 2.1 and all others are 2 → If there are two or more normal cases 3.1 → Disconnection Case 4. If there is one short-circuit staircase 4. Outputs the defect determination results for each circular list (connected circuit patterns).

Hereinafter, the present invention will be explained in more detail using examples with reference to the drawings, but these are merely illustrative and it is understood that various modifications and improvements may be made without going beyond the scope of the present invention. Of course.

[Embodiments of the invention]

First, the most basic embodiment of the present invention will be described.

FIG. 7 shows the configuration of a device that specifically executes this embodiment. As shown in the figure, first, an optical image of a pattern to be inspected is converted into an electrical signal by the imaging device 21. The image capturing device 21 may be a two-dimensional image capturing device such as a TV camera, or may be an image capturing device using a combination of a linear sensor and a unidirectional drive mechanism. It is converted into a binary signal (binary pattern).

As the binarization method, a fixed darkness value method may be used, or in order to obtain a stable pattern, a floating darkness value method or a shading correction means may be used. The binary signal is input to the connectivity processing device 23 to create the connection data shown in FIG. To know the pad number during connectivity processing,
A correspondence relationship between pad positions and pad numbers is created in advance from design information and stored in the pad position data memory 27. The connectivity processing device is more specifically the device described in the application specification entitled "Image Processing Apparatus and Method" previously filed by the applicant. The created connection data is stored in the connection data memory 24. is stored in On the other hand, design data is created in advance from circuit pattern design information and stored in the design data memory 26. After connection data for all circuit patterns is created (after all circuit patterns are imaged by the imaging device), the processing device 25 executes the defect detection algorithm described above and stores the attribute data in the attribute data memory 28. Performs output and defect determination.

The actual defect detection process is shown using the pattern to be inspected shown in FIG. 8 as an example. Table 3 shows the contents of the connection data stored in the connection data memory 24 after the binarization process and the connectivity process. . On the other hand, Table 4 shows the design data when the normal pattern is the pattern shown in Figure 9. The left column of Table 4 is the address, and the center column is the pad number (pointer).
, the right column shows attribute data, which is initialized to 0. First, when the data at the beginning of the connection data memory 24 is checked, both the left and right pad numbers are 1, so the attribute data of the address 1 of the design data is set to 1. Since the next connection data and the left and right pad numbers are in Table 3, Table 4, and Table 2, the attribute data of address 2 of the design data is set to 1. The next connection data has a left pad number of 3 and a parent band number of 2. First, when the data (pointer) at address 3 of the design data is checked, it is 1, which does not match the parent band number 2. Therefore, next, the data at the address l pointed to by the pointer is examined. Since the data is 2 and matches the parent pad number, the attribute data of address 3 is set to 2.

The left pad number of the next connection data is parent pad number 2. When we check the data at address 4 in the design data, it is 5, and the parent pad number does not match 2.So when we check the data at address 5, it is 4, which not only does not match the parent pad number 2, but also the data is different from the connection data. This matches pad number 4 on the left, which means that the parent pad could not be found even after going through the circular list. Therefore, the attribute data of address 4 is set to 3. Regarding the next connection data, the parent pad cannot be found even after going through the circular list, so the attribute data of address 5 is set to 3. Since the next connection data is the left pad number 6 and the parent pad number 6, the attribute data of address 6 is set to 1. In the next connection data, the left pad number is 8, the parent band number is 6, and when you check the data at address 8 in the design data, it is 6, so address 8
The attribute data of is set to 2. This completes the search for all connection data in this case and creates attribute data. Therefore, this time, the attribute data is examined for each circular list and defects are determined. First, pad numbers 1, 2.
Since the pattern consisting of 3 has two 1's in the attribute data, it is determined to be a disconnection.

Next, the pattern consisting of pad number 4.5 has all attribute data of 3, so it is determined to be a short circuit. Furthermore, since the pattern consisting of pad numbers 6, 7.8 has O in the attribute data, there is a no-pad defect (band number 7). In this way, the determination results correctly point out defects on the pattern.

However, one of the shorted patterns does not appear in the determination result, but this cannot be a serious drawback.

In this way, according to this embodiment, short circuits and disconnections in patterns can be detected in a non-contact manner with a relatively simple configuration.

Next, a second embodiment of the present invention will be described. FIG. 10 shows the configuration of an apparatus specifically implementing this embodiment. The difference from the embodiment shown earlier (FIG. 7) is that the binarization device 2
The difference is that a reduction processing device 29 is inserted between the connection processing device 2 and the connectivity processing device 23, and the other configurations are exactly the same. An embodiment of the reduction processing device 29 is shown in FIG. The device has 31 (mz 1) registers and ml of n-pinto.
It consists of two 32m bit shift registers. These shift registers are driven by the same sampling clock. n is made to match the number of sampling points of the I-imaging device 21 in the horizontal direction. Further, m, , mz are determined by the sampling time interval, the vertical resolution of the imaging device, and the size of the defect to be detected. For example, if the sampling time interval and vertical resolution are each equivalent to 10μ, and the size of the defect is 30μ-square, m I = m
Let t = 3. (Figure 11), and m.

The output of the shift register 32 of Xm is guided to the AND circuit 33 and output to the connectivity processing device 23. Although the outputs of all shift registers are extracted in FIG. 11, they may be selectively extracted depending on the shape of the defect to be detected.Results of reduction processing of the binary pattern shown in FIG. 12 by the apparatus of FIG. 11 is shown in FIG. A square whose side is the shortest line segment represents one pixel. The pattern after reduction processing of the inspected pattern shown in Fig. 14 is shown in Fig. 15, and the connection data generated by connectivity processing is shown in Table 5. Design data is shown in Table 6. Furthermore, the attribute data and defect determination results generated in the same manner as in the first embodiment described above are shown in the right column of Table 6.

Table 5 Table 6 As is clear from the results, the specified value (in this example 30
It is possible to detect a pattern width smaller than (μm) as a disconnection. However, it is not possible to distinguish between a disconnection and a small pattern width, and there is a possibility that a minute short circuit may be overlooked.

As described above, according to this embodiment, a pattern defect detection device can be realized with a relatively simple configuration when it is sufficient to detect wire breaks and small pattern widths without distinction.

Next, a third embodiment will be explained. FIG. 16 shows the configuration of an apparatus that specifically executes this embodiment.

As is clear from the figure, this embodiment is a combination of the first embodiment and the second embodiment. Attribute data and defect determination results detected from the pattern to be inspected shown in FIG. 14 are shown in Table 7 together with the data.

The apparatus shown in Figure 16 of the Table is a combination of the apparatus shown in Figure 7 and the apparatus shown in Figure 10, and reference numbers common to those figures refer to the same parts as in those figures.
The a attached to the reference number indicates that the reference number belongs to the series that processes the original pattern, and the letter b indicates that the reference number belongs to the series that processes the reduced pattern. The processing in each series is exactly the same as in the previous two columns, and finally, processing is added to comprehensively judge the judgment results obtained from the original pattern and the judgment results obtained from the reduced pattern. That is, as shown in Table 7, based on the two determination results, it is possible to distinguish between wire breaks and small pattern widths, and it is also possible to avoid overlooking minute short circuits. In this manner, according to the present embodiment, wire breakage and small pattern width can be detected separately.

Next, a fourth embodiment of the present invention will be described.

FIG. 17 shows the configuration of a device that specifically executes this embodiment. The difference from the first embodiment (Fig. 7) is that the binarization device 2
The only difference is that an enlargement processing device 30 is included between 2 and the connectivity processing device 23, and the other configurations are exactly the same. An embodiment of the enlargement processing device 30 is shown in FIG. 18. The device consists of 3 Hmz1) n-bit shift registers and 32 mz m1-bit shift registers. These shift registers are driven by the same sampling clock. n is made to match the number of sampling points in the horizontal direction of the imager. In addition, ml and m are determined by the sampling time interval, the vertical resolution of the imaging device 21, and the size of the defect to be detected. For example, the sampling time interval and the vertical resolution each correspond to 10 μm, and the size of the defect If the length is 30μ steel angle, m+=mz=3 (
Figure 18). Then, shift register 3 of m, Xm,
The output of 2 is led to the OR circuit 34 and output to the connectivity processing device 23. In FIG. 18, the outputs of all the shift registers 32 are led to the OR circuit 34, but they may be selectively taken out depending on the type of defect to be detected. FIG. 19 shows the result of enlarging the binary pattern shown in FIG. 12 using the apparatus shown in FIG. 18. Further, the pattern after the enlargement process of the pattern to be inspected shown in FIG. 14 is shown in FIG. 20, and the connection data generated by the connectivity process is shown in Table 8. Furthermore, attribute data and defect determination results generated in the same manner as in the first embodiment are shown in Table 9 together with design data.

Table 8 Table 9 As is clear from the results, the specified value (in this example 30
A pattern interval smaller than (μm) can be detected as a shortening. However, it is not possible to distinguish between shortened patterns with small widths, and there is a possibility that minute breaks may be overlooked.

As described above, according to this embodiment, a pattern defect detection device can be realized with a relatively simple configuration when it is sufficient to detect short circuits and small pattern intervals without distinction.

Next, a fifth embodiment will be explained. FIG. 21 shows the configuration of a device that specifically executes this embodiment.

As is clear from the figure, this embodiment is a combination of the first embodiment and the fourth embodiment. Table 10 shows the attribute data and defect determination results detected from the pattern to be inspected shown in FIG. The apparatus shown in Figure 21 is adapted from the apparatus shown in Figures 7 and 17, and reference numbers common to those figures refer to the same parts as in those figures. As in FIG. 16, the ``a'' appended to ``a'' indicates that the pattern belongs to the series that processes the original pattern, and the letter ``C'' indicates that the pattern belongs to the series that processes the enlarged pattern. The processing in each series is exactly the same as in the first and fourth examples, but finally, in the third
Similar to the example above, a process is added to comprehensively judge the judgment results obtained from the enlarged pattern of the judgment results obtained from the original pattern.

That is, as shown in Table 1O, the two determination results make it possible to distinguish between small short-circuit pattern intervals and eliminate the possibility of overlooking minute disconnections. In this way, according to this embodiment, short circuits and small pattern intervals can be detected separately.

Table 10 Next, a sixth embodiment of the present invention will be described. FIG. 22 shows the configuration of a device that specifically executes this embodiment. As is clear from the figure, this embodiment is a combination of the second embodiment and the fourth embodiment.

Attribute data and defect determination results detected from the pattern to be inspected shown in FIG. 14 are shown in Table 11 together with the design data. The process leading up to this point is the second step. This is exactly the same as the fourth example. However, at the end, processing is added to comprehensively judge the judgment results obtained from the reduced pattern and the judgment results obtained from the enlarged pattern.

In other words, as shown in Table 12, from the two judgment results, it is not possible to distinguish between a small pattern interval and a minute short circuit, and between a small pattern width and a minute disconnection, but it is possible to completely distinguish and detect the others. It's there, and you can't miss it. As described above, according to this embodiment, it is possible to distinguish and detect complete short circuits, complete wire breaks, small pattern spacing or fine short circuits, and small pattern widths or fine wire breaks.

The process leading up to this point is as follows. Second. This is exactly the same as the fourth example. However, at the end, a process is added to comprehensively judge the judgment results obtained from the reduced pattern, the judgment results obtained from the enlarged pattern, and the judgment results obtained from the original pattern.

That is, as shown in Table 14, from the three judgment results, complete disconnection, complete short circuit, minute disconnection, minute short circuit,
In this way, according to this embodiment, it is possible to completely distinguish between small pattern width and small pattern interval and detect defects without missing anything.In this way, according to this embodiment, it is possible to completely distinguish between defect types.

Table 14 Next, a seventh embodiment of the present invention will be explained. The configuration of an apparatus for specifically carrying out this embodiment is shown in FIG. 23. As is clear from the figure, this embodiment 1. Second.
This is a composite of the fourth embodiment.

Attribute data and defect determination results detected from the pattern to be inspected shown in FIG. 14 are shown in Table 13 together with the design data.

Table 13 Next, the memory capacity and processing time required for the seven embodiments described above will be considered.

Assuming that there are 256 x 256 pads on one board,
First, the memory capacity is calculated. In this case, the pad number can be expressed in 16 bits (2 bytes). Assuming that all pads are detected in the connectivity process, the generated connection data is (16bit+16bit)X256”=2.097
,152bit= 262.144kbyte Also, the design data is 16bit x256”=1,048.576b;t=
131.072kbytes Attribute data is 4b when expressed in 4bits including spare data.
it X256”=262,144bit=32.76
It will be 8kbytes. The total memory capacity is calculated for each of the first to seventh embodiments.

1st example 425.984 kbyte 2nd
〃425.984 kbyte 3rd 〃72
0.896 kbyte 4th 〃425.984
kbyte 5th 〃720.896 kbyte 6th s 720.896 kbyte 7th
s 1,015.808 kbytes. Using 64kbytes of RAM, these
Although 52 to 124 RAMs are required, this is a sufficiently achievable capacity and will not pose any problem when considering future increases in RAM capacity. For example, a 150s square substrate is 5μm thick.
Original image information when detected with resolution 'iJ1900M
bit (=112.5 Mbyte), these can be said to be very compact.

Furthermore, processing time is evaluated based on the number of times design data is referenced. If the average number of pads on one connected pattern is n, then the average number of references required to find a parent pad when generating attribute data is 256 x 256 pads, assuming that all patterns are free of defects. In the case of , it becomes.

Now, if 1% of all pads have a defect in which the parent pad cannot be found, this will serve as a reference in this case. Assuming n=4, there are 165,478.4 references to design data in generating attribute data. In addition, for defect determination processing, all the design data needs to be referenced once, so 256" = 65,536 references are required. From the imaging device 21 to connection data generation by the connectivity processing device 23. can be processed in real time. Therefore, a 150-square board can be processed in real time using a device that assumes that the imaging signal sampling frequency is 5 MHz, the processing device is a microcomputer, and that it takes 100 μs to refer to design data once. Assuming that the inspection is performed with a resolution of 5 μm, the overall inspection processing time for the first to seventh embodiments is: 203.1 seconds 2nd 4203.1 seconds 3 4226.2 seconds in the first embodiment 4th 4203.1 seconds 5th 4226.2 seconds 6th 4226.2 seconds 7th 249.3 seconds.

〔Effect of the invention〕

As explained above, according to the present invention, the pattern is detected non-contact using optical means, and the connection relationship between pads is determined by image processing, so it is not affected by slight variations in the target pattern. , and allows for high-speed defect inspection without damaging the pattern (with high reliability).

In particular, since a list structure is used for design data representing connection relationships, for example, in the case of 256" x 256 butts, 256" x 256
2#2.56x to9bit to 1.05X 10'
Data compression into bits can be realized, and processing time can also be significantly reduced.

[Brief explanation of the drawing]

Fig. 1 is a plan view of an example of the original pattern, Fig. 2 is a plan view of a pattern obtained by applying reduction processing to the pattern shown in Fig. 1, and Fig. 3 is a plan view of the pattern shown in Fig. 1. FIG. 4 is a diagram showing the structure of connection data; FIGS. 5 and 6 are plan views showing two different examples of circuit patterns; FIG. 8 is a block diagram showing the configuration of an apparatus for carrying out the method according to the first embodiment of the present invention, FIG. 8 is a plan view of an example of a pattern to be inspected, and FIG. 9 is the same as that shown in FIG. A plan view of a normal pattern corresponding to the pattern to be inspected, FIG. 10 is a block diagram showing the configuration of an apparatus for carrying out the method according to the second embodiment of the present invention, and FIG. 11 is a configuration of a reduction processing apparatus. FIG. 12 is a block diagram showing an example of a binary pattern, FIG. 13 is a pattern diagram obtained by applying reduction processing to the pattern shown in FIG. 12, and FIG. FIG. 15 is a plan view of a pattern obtained by applying reduction processing to the pattern shown in FIG. 14, and FIG. 16 is a plan view of an example of the third embodiment of the present invention. Block diagram showing the configuration of an apparatus for carrying out the method by Mr. g, No. 17
FIG. 18 is a block diagram showing the configuration of an apparatus for carrying out the method according to the fourth embodiment of the present invention, FIG. 18 is a block diagram showing the configuration of an enlargement processing device, and FIG. FIG. 20 is a plan view of the pattern obtained by enlarging the pattern shown in FIG. 14, FIGS. 21, 22, and 23. 5. of the present invention, respectively. 6th. and FIG. 10 is a block diagram showing the configuration of an apparatus for carrying out the method by Mr. B of the seventh embodiment. 21... Imaging device, 22-... Value conversion device, 23.23
a, 23b. 23 c = connectivity processor, 24.24a, 24b
, 24cm" connection data memory, 25...processing device, 26...design data memory, 27...bad position data memory, 28...attribute data memory,
29... Reduction processing device, 30... Enlargement processing device, 3
1.32...Shift register, 33...AND circuit, 34...OR circuit. Agent Tadashi Akimoto Figure 1 Figure 4 Figure 5 Figure 2 Figure 6 Figure 3 Figure 7 Cause 8 Figure 9 Figure 12 Figure 13 Figure 10 Figure 11 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 21 Binding Figure 22 Figure 19 Figure 20 Figure 23

Claims (7)

[Claims] 1. Convert the optical image of the pattern into an electrical signal, binarize the electrical signal, examine the connection relationship between two selected points on the binarized pattern, and calculate the connection relationship by the numbers assigned to those points. By generating connection data expressed in pairs and comparing the connection data with design data created from design information and expressing numbers assigned to connected points in a circular list structure, defects in patterns can be detected. A pattern defect detection method characterized by determining and detecting. 2. 2. The pattern defect detection method according to claim 1, wherein a reduction process of the binarized pattern is added between the binarization process of the electrical signal and the connection data generation process. 3. 2. The pattern defect detection method according to claim 1, further comprising enlarging the binarized pattern between the electrical signal binarization process and the connection data generation process. 4. Pattern defect detection according to claim 2, characterized in that pattern defects are finally judged and detected from the judgment results obtained through the reduction process and the judgment results obtained without the reduction process. Method. 5. Pattern defect detection according to claim 3, characterized in that a pattern defect is finally judged and detected from the judgment result obtained through the enlargement process and the judgment result obtained without the enlargement process. Method. 6. Between the electrical signal binarization process and the connection data generation process, reduction and enlargement processes of the binarized pattern are added, and the judgment results obtained through the reduction process and the judgment obtained through the enlargement process are 2. The pattern defect detection method according to claim 1, wherein a pattern defect is finally determined and detected from the results. 7. A pattern defect is finally determined and detected from the determination result obtained through reduction processing, the determination result obtained through enlargement processing, and the determination result obtained without undergoing reduction processing or enlargement processing. , a pattern defect detection method according to claim 1.