JPH0231864B2 - - Google Patents
Info
- Publication number
- JPH0231864B2 JPH0231864B2 JP59190327A JP19032784A JPH0231864B2 JP H0231864 B2 JPH0231864 B2 JP H0231864B2 JP 59190327 A JP59190327 A JP 59190327A JP 19032784 A JP19032784 A JP 19032784A JP H0231864 B2 JPH0231864 B2 JP H0231864B2
- Authority
- JP
- Japan
- Prior art keywords
- ceramic
- ceramic substrate
- resin material
- ceramic plate
- semiconductor pellet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000919 ceramic Substances 0.000 claims description 89
- 239000000758 substrate Substances 0.000 claims description 53
- 239000004065 semiconductor Substances 0.000 claims description 41
- 229920005989 resin Polymers 0.000 claims description 33
- 239000011347 resin Substances 0.000 claims description 33
- 239000000463 material Substances 0.000 claims description 31
- 239000008188 pellet Substances 0.000 claims description 27
- 238000000034 method Methods 0.000 description 5
- 238000007789 sealing Methods 0.000 description 5
- 238000013459 approach Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000004382 potting Methods 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明は、例えば印刷積層型のセラミツク基板
を用いたチツプキヤリアIC等の半導体装置に関
する。DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a semiconductor device such as a chip carrier IC using a printed laminated ceramic substrate.
〈従来の技術〉
一般に、この種の半導体装置としては、例えば
セラミツク基板を備え、このセラミツク基板上に
チツプ型トランジスタやチツプ型半導体集積回路
等の半導体ペレツトを載置固定し、この半導体ペ
レツトとセラミツク基板に配線されたリード部と
をワイヤボンデイングしたものが知られている。<Prior Art> In general, this type of semiconductor device includes, for example, a ceramic substrate, and a semiconductor pellet such as a chip type transistor or a chip type semiconductor integrated circuit is placed and fixed on the ceramic substrate, and the semiconductor pellet and the ceramic are placed and fixed on the ceramic substrate. A device in which wire bonding is performed to a lead portion wired on a substrate is known.
〈発明が解決しようとする問題点〉
ところで、この半導体ペレツトは外部の影響を
受けないようにするために、封止手段を用いて保
護する必要がある。<Problems to be Solved by the Invention> Incidentally, in order to prevent the semiconductor pellet from being affected by external influences, it is necessary to protect it using a sealing means.
第３図は従来の封止手段の一例を示し、この図
に示されるものでは、矩形状の箱形に形成された
セラミツクキヤツプ９を用意し、このセラミツク
キヤツプ９をセラミツク基板２上に取り付けられ
た半導体ペレツト３に被せ付けたのち、該セラミ
ツクキヤツプ９とセラミツク基板２とをガラスグ
レーズや樹脂接着剤で接合することにより、半導
体ペレツト３をセラミツクキヤツプ９内に密封す
るようにしている。 FIG. 3 shows an example of a conventional sealing means. In the one shown in this figure, a ceramic cap 9 formed in a rectangular box shape is prepared, and this ceramic cap 9 is mounted on a ceramic substrate 2. After the ceramic cap 9 and the ceramic substrate 2 are bonded with glass glaze or resin adhesive, the semiconductor pellet 3 is sealed inside the ceramic cap 9.
ところが、このような封止方式の場合、半導体
ペレツト３はセラミツクキヤツプ９により確実に
保護されるが、このセラミツクキヤツプ９が相当
高価につくため製造コストが嵩み、実用に際し問
題がある。 However, in the case of such a sealing method, although the semiconductor pellet 3 is reliably protected by the ceramic cap 9, the ceramic cap 9 is quite expensive, which increases the manufacturing cost and poses a problem in practical use.
また、第４図は他の従来例を示し、これではセ
ラミツク基板２上の半導体ペレツト３を樹脂材５
で被覆することにより、この樹脂材５で該半導体
ペレツト３を封止している。 Further, FIG. 4 shows another conventional example, in which semiconductor pellets 3 on a ceramic substrate 2 are made of a resin material 5.
By covering the semiconductor pellet 3 with the resin material 5, the semiconductor pellet 3 is sealed.
しかしながら、この場合においては、安価に製
造し得る反面、樹脂材５とセラミツク基板２の線
膨張係数に大差があるため、第５図イに示すよう
に、ゲル化状態の樹脂材５が硬化する際に収縮す
ることにより、セラミツク基板２に引張力が加わ
り、該セラミツク基板２に反りが生じたり、ある
いはセラミツク基板２または樹脂材５に割れが発
生する場合がある。また、このほか、第５図ロに
示すように、サーマルシヨツクが付与されると、
樹脂材５の両端がセラミツク基板２から剥離し
て、該セラミツク基板２と樹脂材５とが分離して
しまう場合もあり、これらの点が製造上あるいは
使用上の問題となつている。 However, in this case, although it can be manufactured at a low cost, there is a large difference in linear expansion coefficient between the resin material 5 and the ceramic substrate 2, so that the resin material 5 in a gelled state hardens, as shown in FIG. 5A. Due to the shrinkage, a tensile force is applied to the ceramic substrate 2, which may cause the ceramic substrate 2 to warp or cause cracks to occur in the ceramic substrate 2 or the resin material 5. In addition, as shown in Figure 5B, if a thermal shock is applied,
In some cases, both ends of the resin material 5 are peeled off from the ceramic substrate 2, and the ceramic substrate 2 and the resin material 5 are separated, which poses a problem in manufacturing or use.
そこで、これの改善策として、例えば第６図に
示すように、セラミツク基板２上に取り付けられ
た半導体ペレツト３に前記他の従来例のように樹
脂材５を被覆し、この樹脂材５をセラミツク基板
２とこのセラミツク基板２の上方に配置した方形
のセラミツク板１０とで挟着し、該樹脂材５がゲ
ル化状態において生じる表面張力により、この樹
脂材５と前記セラミツク基板２並びにセラミツク
板１０とを接合固着することにより、該樹脂材５
の硬化時における収縮による内部応力を分散させ
るようにしたものが提案されている。 Therefore, as a solution to this problem, for example, as shown in FIG. 6, a semiconductor pellet 3 mounted on a ceramic substrate 2 is coated with a resin material 5 as in the other conventional example, and this resin material 5 is coated with a ceramic material. The substrate 2 is sandwiched between the ceramic substrate 2 and a rectangular ceramic plate 10 placed above the ceramic substrate 2, and the resin material 5, the ceramic substrate 2, and the ceramic plate 10 are bonded together by the surface tension generated when the resin material 5 is in a gel state. By joining and fixing the resin material 5
A method has been proposed in which the internal stress caused by shrinkage during curing is dispersed.
しかし、このような従来の改善例の場合、新た
に次のような問題点が生じる。すなわち、前述の
樹脂硬化時における収縮などによつて、前記セラ
ミツク板１０が第６図の想像線で示すように、セ
ラミツク基板２に対して傾いたり、樹脂材５の量
が流れ方によつて、セラミツク板１０とセラミツ
ク基板２との間隔、すなわち半導体装置自体の厚
み寸法にはりつきを生じたりするため、極端な場
合、セラミツク板１０が半導体ペレツト３から引
き出されたボンデイングワイヤ４…に当接して、
このボンデイングワイヤ４…を倒して断線させる
こともある。 However, in the case of such a conventional improvement example, the following new problems arise. That is, due to shrinkage during the resin curing mentioned above, the ceramic plate 10 may be tilted with respect to the ceramic substrate 2, as shown by the imaginary line in FIG. , the gap between the ceramic plate 10 and the ceramic substrate 2, that is, the thickness of the semiconductor device itself, may cause sticking. ,
This bonding wire 4 may be knocked down and broken.
本発明はかかる従来の問題点に鑑み、セラミツ
ク板の傾きおよび半導体装置自体の厚み寸法のば
らつきをなくして、寸法および機能の安定化を図
ることを目的とする。 In view of these conventional problems, it is an object of the present invention to eliminate the inclination of the ceramic plate and the variations in the thickness of the semiconductor device itself, thereby stabilizing the dimensions and functions.
〈問題点を解決するための手段〉
本発明ではこのような目的を達成するために、
セラミツク基板の上面に取り付けた半導体ペレツ
トを樹脂材で被覆するとともに、この樹脂材を介
して前記セラミツク基板とその上方に配置された
矩形のセラミツク板とを接合してなる半導体装置
において、前記セラミツク板の外側に位置する４
隅部それぞれに相等しい長さの脚部を突出形成
し、かつ、接合した状態では前記脚部が前記半導
体ペレツトを跨ぐとともに、各脚部の先端が前記
セラミツク基板の上面に当接する点に特徴を有し
ている。<Means for solving the problems> In order to achieve such an object, the present invention has the following features:
In a semiconductor device formed by coating a semiconductor pellet attached to the upper surface of a ceramic substrate with a resin material, and bonding the ceramic substrate to a rectangular ceramic plate disposed above the ceramic substrate via the resin material, the ceramic plate 4 located outside of
Legs of equal length are formed protrudingly at each corner, and in the joined state, the legs straddle the semiconductor pellet, and the tips of each leg abut the top surface of the ceramic substrate. have.
〈作 用〉
すなわち、上記構成の半導体装置は、セラミツ
ク基板とセラミツク板とが半導体ペレツトを被覆
する樹脂材のゲル化状態における表面張力によつ
て近接させられたのち、この樹脂材が硬化するこ
とによつてセラミツク基板とセラミツク板とが接
合されることにより一体化される。そこで、セラ
ミツク基板にセラミツク板が近接した際には、こ
のセラミツク板の４隅部それぞれから突出形成さ
れた相等しい長さの脚部が半導体ペレツトを跨い
だ状態で配置されることになり、各脚部の先端が
セラミツク基板の上面に当接することによつてセ
ラミツク板の位置決めが行われることになる。し
たがつて、このセラミツク板はセラミツク基板に
対して脚部の長さに応じた所定間隔だけ離間した
平行状態で配置されることになる。<Function> In other words, in the semiconductor device having the above structure, the ceramic substrate and the ceramic plate are brought close to each other by the surface tension in the gelled state of the resin material covering the semiconductor pellet, and then the resin material is cured. The ceramic substrate and the ceramic plate are bonded and integrated by the method. Therefore, when the ceramic plate approaches the ceramic substrate, the legs of equal length protruding from each of the four corners of the ceramic plate are arranged so as to straddle the semiconductor pellet. The ceramic plate is positioned by the tips of the legs coming into contact with the upper surface of the ceramic substrate. Therefore, this ceramic plate is arranged in parallel with the ceramic substrate at a predetermined interval corresponding to the length of the leg.
〈実施例〉
以下、本発明を図面に示す実施例に基づき詳細
に説明する。<Example> Hereinafter, the present invention will be described in detail based on an example shown in the drawings.
第１図はこの実施例の半導体装置の要部を示す
縦断側面図である。この図において、この半導体
装置は例えば一面にリード部１…を印刷配線して
なる矩形のセラミツク基板２を備え、このセラミ
ツク基板２の一面にチツプ型トランジスタやチツ
プ型半導体集積回路等の半導体ペレツト３を取り
付け、該半導体ペレツト３の電極（図示せず）と
前記リード部１…とを複数のボンデイングワイヤ
４…で接続してなる、いわゆるセラミツクキヤリ
アICである。前記半導体ペレツト３は前述のよ
うにワイヤボンデイングされたのち、エポキシ樹
脂等の樹脂材５で被覆されることにより封止され
る。なお、この樹脂材５を半導体ペレツト３上に
付与するについては、ドロツピングあるいはポツ
テイング等の手法が採用される。半導体ペレツト
３上に付与された樹脂材５の上面にはセラミツク
板６が配置される。 FIG. 1 is a longitudinal sectional side view showing the main parts of the semiconductor device of this embodiment. In this figure, this semiconductor device includes a rectangular ceramic substrate 2 having, for example, printed wiring leads 1 on one side, and a semiconductor pellet 3 such as a chip type transistor or a chip type semiconductor integrated circuit on one side of the ceramic substrate 2. This is a so-called ceramic carrier IC in which the electrodes (not shown) of the semiconductor pellet 3 and the lead portions 1 are connected by a plurality of bonding wires 4. After the semiconductor pellet 3 is wire bonded as described above, it is sealed by being covered with a resin material 5 such as epoxy resin. Incidentally, in order to apply the resin material 5 onto the semiconductor pellet 3, a method such as dropping or potting is adopted. A ceramic plate 6 is placed on the upper surface of the resin material 5 applied on the semiconductor pellet 3.
第２図はセラミツク板６の斜視図である。この
図において、このセラミツク板６は前記セラミツ
ク基板２とほぼ同形状の矩形板部７と、該矩形板
の外側に位置する４隅部から同方向に突出形成さ
れた４本の脚部８…とで構成される。各脚部８…
はそれぞれ等しい長さ寸法を有し、その長さ寸法
は半導体ペレツト３に接続されたボンデイングワ
イヤ４…の上端からセラミツク基板２の一面まで
の距離より大きく設定されている。 FIG. 2 is a perspective view of the ceramic plate 6. In this figure, this ceramic plate 6 includes a rectangular plate portion 7 having approximately the same shape as the ceramic substrate 2, and four legs 8 formed protruding in the same direction from four corners located on the outside of the rectangular plate. It consists of Each leg 8...
have the same length, and the length is set larger than the distance from the upper end of the bonding wires 4 connected to the semiconductor pellet 3 to one surface of the ceramic substrate 2.
このセラミツク板６とセラミツク基板２との間
に挟み込まれた樹脂材５は、例えばセラミツク基
板２を熱板（図示せず）により加熱することによ
り熱硬化処理されるが、この樹脂材５が硬化する
までのゲル化状態において生じる表面張力によ
り、この樹脂材５の下側に位置するセラミツク基
板２、並びに上側に位置するセラミツク板６とが
互いに引き合う方向に近接して接合固着される。
そして、この両者２，６が近接する過程におい
て、前記各脚部８…はその先端がそれぞれセラミ
ツク基板２の面上に当接し、これにより前記セラ
ミツク基板２、半導体ペレツト３、樹脂材５およ
びセラミツク板６が所定の配置位置を保持した状
態で互いに組み付け固定される。 The resin material 5 sandwiched between the ceramic plate 6 and the ceramic substrate 2 is thermally cured, for example, by heating the ceramic substrate 2 with a hot plate (not shown). Due to the surface tension generated in the gelling state, the ceramic substrate 2 located below the resin material 5 and the ceramic plate 6 located above the resin material 5 are bonded and fixed in close proximity to each other in the direction of attraction.
During the process in which both the legs 2 and 6 approach each other, the tips of the legs 8 come into contact with the surface of the ceramic substrate 2, thereby causing the ceramic substrate 2, the semiconductor pellet 3, the resin material 5 and the ceramic substrate 2 to come into contact with each other. The plates 6 are assembled and fixed to each other while maintaining their predetermined positions.
〈発明の効果〉
以上のように本発明によれば、セラミツク基板
の面上に半導体ペレツトを取り付け、この半導体
ペレツトを樹脂材で被覆するとともに、この樹脂
材をセラミツク基板とこのセラミツク基板の上方
に配置した方形のセラミツク板とで挟着してな
り、セラミツク板の４隅部にそれぞれ等しい長さ
を有する脚部を突出形成し、セラミツク板が樹脂
材を介してセラミツク基板に接合固着された状態
において、各脚部の先端がそれぞれセラミツク基
板の面上に当接してなるものとした。したがつ
て、半導体ペレツトを封止する樹脂材のゲル化状
態における表面張力によつて、セラミツク板とセ
ラミツク基板とが互いに引き合う方向に近接する
ため、セラミツク板の外側に位置する４隅部それ
ぞれから突出形成された相等しい長さの脚部が半
導体ペレツトを跨いだ状態で配置されることにな
り、各脚部の先端がセラミツク基板の上面に当接
して位置保持することになる。これにより該セラ
ミツク板はセラミツク基板に対して所定間隔をお
いて平行に配置され、セラミツク板の傾きおよび
半導体装置自体の厚みのばらつきがなくなるの
で、寸法および機能の安定化を図ることができ、
製造時における製品の取り扱いの利便性の向上に
も寄与する。<Effects of the Invention> As described above, according to the present invention, semiconductor pellets are attached on the surface of a ceramic substrate, the semiconductor pellets are covered with a resin material, and the resin material is applied to the ceramic substrate and above the ceramic substrate. A state in which the ceramic plate is sandwiched between arranged rectangular ceramic plates, legs having equal lengths are formed protruding from each of the four corners of the ceramic plate, and the ceramic plate is bonded and fixed to the ceramic substrate via a resin material. In this case, the tip of each leg was in contact with the surface of the ceramic substrate. Therefore, due to the surface tension in the gelled state of the resin material that seals the semiconductor pellet, the ceramic plate and the ceramic substrate approach each other in a direction where they are attracted to each other. The protruding legs of equal length are arranged to straddle the semiconductor pellet, and the tip of each leg comes into contact with the upper surface of the ceramic substrate to maintain its position. As a result, the ceramic plate is arranged parallel to the ceramic substrate at a predetermined distance, and the inclination of the ceramic plate and the variation in the thickness of the semiconductor device itself are eliminated, so that the dimensions and functions can be stabilized.
It also contributes to improving the convenience of handling products during manufacturing.
第１図および第２図は本発明の実施例を示し、
第１図はこの実施例の半導体装置の要部を示す縦
断側面図、第２図は該セラミツク板の斜視図、第
３図は従来の封止手段の一例を示す要部縦断側面
図、第４図および第５図イ，ロは従来の封止手段
の他の例を示し、第４図は要部縦断側面図、第５
図イ，ロは樹脂材の変形状態を示す要部縦断側面
図、第６図は従来の改善例を示す要部縦断側面図
である。
２…セラミツク基板、３…半導体ペレツト、５
…樹脂材、６…セラミツク板、８…脚部。
1 and 2 show embodiments of the invention,
FIG. 1 is a longitudinal sectional side view showing the main parts of the semiconductor device of this embodiment, FIG. 2 is a perspective view of the ceramic plate, and FIG. 3 is a longitudinal sectional side view of the main parts showing an example of conventional sealing means. 4 and 5A and 5B show other examples of conventional sealing means, FIG. 4 is a longitudinal sectional side view of the main part, and FIG.
Figures A and B are longitudinal sectional side views of the main parts showing the deformed state of the resin material, and Fig. 6 is a longitudinal sectional side view of the main parts showing an example of a conventional improvement. 2... Ceramic substrate, 3... Semiconductor pellet, 5
...Resin material, 6. Ceramic board, 8. Legs.
Claims (1)
レツトを樹脂材で被覆するとともに、この樹脂材
を介して前記セラミツク基板とその上方に配置さ
れた矩形のセラミツク板とを接合してなる半導体
装置において、 前記セラミツク板の４隅部それぞれに相等しい
長さの脚部を突出形成し、かつ、接合した状態で
は前記脚部が前記半導体ペレツトを跨ぐととも
に、各脚部の先端が前記セラミツク基板の上面に
当接することを特徴とする半導体装置。[Claims] 1. A semiconductor pellet attached to the top surface of a ceramic substrate is covered with a resin material, and the ceramic substrate and a rectangular ceramic plate placed above the ceramic substrate are bonded via the resin material. In the semiconductor device, leg portions of equal length are formed protruding from each of the four corners of the ceramic plate, and when the ceramic plate is bonded, the leg portions straddle the semiconductor pellet, and the tip of each leg portion touches the ceramic plate. A semiconductor device characterized by being in contact with the top surface of a substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59190327A JPS6167944A (en) | 1984-09-11 | 1984-09-11 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59190327A JPS6167944A (en) | 1984-09-11 | 1984-09-11 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6167944A JPS6167944A (en) | 1986-04-08 |
| JPH0231864B2 true JPH0231864B2 (en) | 1990-07-17 |
Family
ID=16256335
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59190327A Granted JPS6167944A (en) | 1984-09-11 | 1984-09-11 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6167944A (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5769232U (en) * | 1980-10-13 | 1982-04-26 |
-
1984
- 1984-09-11 JP JP59190327A patent/JPS6167944A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6167944A (en) | 1986-04-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20030042615A1 (en) | Stacked microelectronic devices and methods of fabricating same | |
| JP2001326236A (en) | Manufacturing method of semiconductor device | |
| US4157611A (en) | Packaging structure for semiconductor IC chip and method of packaging the same | |
| EP0645812B1 (en) | Resin-sealed semiconductor device | |
| US4482781A (en) | Stabilization of semiconductor device package leads | |
| EP1396886A2 (en) | Semiconductor device having the inner end of connector leads placed onto the surface of semiconductor chip | |
| US4262165A (en) | Packaging structure for semiconductor IC chip | |
| US6541856B2 (en) | Thermally enhanced high density semiconductor package | |
| JPH0231864B2 (en) | ||
| JPH0418468B2 (en) | ||
| JPH11168122A (en) | Method for mounting semiconductor element on circuit substrate and semiconductor device | |
| JPH0344040A (en) | Semiconductor device and its manufacture | |
| JPH05267503A (en) | Semiconductor device | |
| JPH1197569A (en) | Semiconductor package | |
| JP2815984B2 (en) | Semiconductor device | |
| JPH0287654A (en) | Surface mounting semiconductor device | |
| JPH04150062A (en) | Semiconductor device | |
| JPH02202042A (en) | Resin-sealed semiconductor device | |
| JPS61214443A (en) | Semiconductor device and manufacture thereof | |
| JPH04150061A (en) | Semiconductor device | |
| JPS60241242A (en) | Lead frame | |
| JPS63248155A (en) | Semiconductor device | |
| JPS5915504Y2 (en) | Resin-encapsulated semiconductor device | |
| JPH0528047U (en) | Semiconductor package | |
| JPH07201913A (en) | Mounting structure of semiconductor element |