JPH0231418A - Electric junction structure of semiconductor device - Google Patents

Abstract

PURPOSE:To enable the semiconductor to maintain the satisfactory electric junction in the state when it is completed by a method wherein the title junction structure is provided with insulating films and electrode.wiring as well as an electrode contact window passing through these elements, a junction material film in the window electrically connecting between the electrode and the wiring or between the electrode.wiring and the semiconductor substrate. CONSTITUTION:The title electric junction structure is provided with insulating films (e.g., an interelement isolation insulating film 2, an interlayer insulating film 4), an electrode, wiring 5 formed on the semiconductor substrate (e.g., silicon semiconductor substrate 1) as well as an electrode contact window 4A passing through the electrode wiring 5 and the insulating film 4, a junction material film 8 in the window 4A electrically junctioning between the electrode and wiring or between the electrode.wiring and a semiconductor substrate. Through these procedures, the junction material film 8 can be arbitrarily selected under no influence of the process requirements for the formation of electrode.wiring, etc., in the lower and upper layers while enabling the film 8 to maintain the satisfactory state when it is formed.

Description

[Detailed description of the invention] [Summary] Electrodes/wirings and substrates in semiconductor devices, or electrodes/wirings and substrates, or electrodes/wirings and substrates in semiconductor devices.
Regarding the improvement of the electrical bonding structure between interconnects, the bonding material film interposed between the lower layer and the upper layer is not affected by the manufacturing process of the upper layer, and has good electrical properties in its completed state. For the purpose of maintaining bonding, an insulating film, an electrode/wiring formed on a semiconductor substrate, an electrode contact window penetrating the electrode/wiring and the insulating film, and an electrode contact window located within the electrode contact window are used. and a bonding material film for electrically bonding between the electrodes and wirings or between the electrodes and wirings and the semiconductor substrate.

[Industrial application field]

The present invention relates to an improvement in an electrical connection structure between an electrode/wiring and a substrate, or between an electrode/wiring in a semiconductor device.

In general, the degree of integration in semiconductor devices is becoming increasingly higher, and along with this, there is a demand for improved reliability of electrical bonding structures.

In order to improve the reliability of this electrical bonding structure, a material different from that of the wiring is interposed in the bonding portion. In such cases, process conditions such as heat treatment for the material used for the bonding portion are often limited by the physical properties of the material constituting the wiring formed thereon.

Therefore, it is necessary to take measures such that the process conditions for the material used for the bonding portion are not affected by the process conditions for the wiring material.

[Conventional technology]

Usually between the wiring and the substrate in a semiconductor device, or
In order to electrically couple the wirings, electrode contact windows are opened in the lower layer of the substrate or in the insulating film covering the wirings, and then the upper layer of the wiring is formed.

FIG. 14 shows a cutaway side view of essential parts for explaining an electrical connection structure in a conventional semiconductor device.

In the figure, 1 is a silicon semiconductor substrate, 2 is an isolation insulating film made of silicon dioxide (SiOz), 3 is an impurity diffusion region, 4 is an insulating film between the eyebrows made of SiO2, and 5
indicate electrodes and wiring, respectively.

In such an electrical bonding structure, if there is a problem with the material to make contact between the lower silicon semiconductor substrate 1 and the upper layer electrode/wiring 5, the silicon semiconductor substrate 1 and the electrode/wiring 5 may be in contact with each other. A bonding material is interposed between the wiring 5 and the wiring 5.

FIG. 15 shows a cutaway side view of essential parts for explaining an electrical bonding structure using a bonding material in a conventional semiconductor device.
The same symbols as those used in FIG. 14 represent the same parts or have the same meaning.

In the figure, 6 is the silicon semiconductor substrate 1 and the electrode/arrangement A
5 shows a bonding material film interposed between 5 and 5.

The illustrated bonding material film 6 needs to be compatible with various conditions in the subsequent semiconductor device manufacturing process.

[Problem to be solved by the invention]

As mentioned above, when a bonding material film is interposed between the substrate and the electrode/wiring, or between the electrode/wiring and the electrode/wiring,
Although it may be fine as long as it is formed, it often deteriorates during subsequent semiconductor device manufacturing processes.

The present invention makes it possible to maintain good electrical bonding in a completed state of a semiconductor device having an electrical bonding structure in which a bonding material film is interposed between a lower layer and an upper layer.

[Means to solve the problem]

1 and 2 show a cutaway side view and a plan view of a main part of a semiconductor device at key points in the process for detailed explanation of the present invention. The same symbol as the one used in this document shall represent the same part or have the same meaning.

In the figure, 4A indicates an electrode contact window, 7' indicates an interlayer insulating film, and 8 indicates a bonding material film.

In the present invention, the bonding material film 8 is formed after the electrode/wiring 5 is formed and processes such as annealing are completed.

For this reason, in the electrical junction structure of the semiconductor device according to the present invention, an insulating film (for example, an element isolation insulating film 2, a glabellar insulating film) formed on a semiconductor substrate (for example, a silicon semiconductor substrate 1) is required. 4 etc.) and electrodes/wirings (e.g. electrodes/wirings 5); electrode contact windows (e.g. electrode contact windows 4A) penetrating the electrodes/wirings and insulating film; It is configured to include a bonding material film (for example, bonding material film 8) for electrically bonding between the wirings or between the electrodes/wirings and the semiconductor substrate.

[Effect]

By adopting the above-mentioned means, the semiconductor substrate, electrodes/wiring,
Alternatively, the bonding material film for electrically bonding between the electrodes and wiring may be an electrode contact window provided to penetrate through the electrodes, wiring, glabella insulating film, etc. after they have been formed and annealed. Since the bonding material film is formed internally, it is completely unaffected by the process conditions for forming not only the lower layer but also the upper layer electrodes, wiring, etc.
Therefore, the material can be selected arbitrarily, and
It is possible to maintain the good state in which it is formed, which can contribute to improving the reliability of the electrical bonding structure.

〔Example〕

3 to 7 are cutaway side views of essential parts of a semiconductor device at key points in the process for explaining the case of manufacturing an embodiment of the present invention, and the following description will be made with reference to these figures. do. Note that the same symbols as those used in FIG. 1, FIG. 2, FIG. 14, and FIG. 15 represent the same parts or have the same meaning.

See Figure 3 (1) By applying a selective thermal oxidation method using, for example, a silicon nitride (Si3N4) film as an oxidation-resistant mask, an inter-element isolation insulating film 2 made of 5i02 is formed on a silicon semiconductor substrate 1. Form.

(2) Usual techniques, such as photolithography techniques;
The impurity diffusion region 3 into which As ions are introduced and other various regions are formed in the silicon semiconductor substrate 1 by applying an ion implantation method, a heat treatment method, or the like.

See Figure 4 (3) For example, chemical vapor deposition (chemical vapor deposition)
By applying a por deposition (CVD) method, a glabellar insulating film 4 made of SiO2 is formed.

(4) For example, by applying the magnetron sputtering method, tungsten (W) can be applied on the glabella insulating film 4.
) form a film.

(5) By applying ordinary photolithography technology, the W film formed in step (4) is patterned to form the electrode/wiring 5.

(6) Anneal the electrode/wiring 5 at a temperature of, for example, 1000 ("C).

Refer to FIG. 5 (71 By applying the CVD method, a glabellar insulating film 7 made of 5i02 covering the electrode/wiring 5 is formed.

(8) By applying normal photolithography technology, an electrode contact window 4A penetrating the glabella insulating film 7, the electrode/wiring 5, and the interlayer insulating film 4 is formed, and a part of the surface of the silicon semiconductor substrate 1 is formed. expose.

Refer to FIG. 6 (9) For example, by applying magnetron sputtering method, the bonding material film 8 made of aluminum (CAl)+2C%]Si is formed including the inside of the electrode contact window 4A.
form.

As a result, electrical bonding between the impurity diffusion region 3 and the electrode/wiring 5 is achieved.

αω Patterning of the bonding material film 8 is performed by applying ordinary photolithography technology.

Referring to FIG. 7, a cover film 9 made of SiO2 is formed by applying the αω CVD method.

In the semiconductor device manufactured in this way, since the upper layer electrode/wiring 5 has been subjected to high-temperature annealing and other treatments before forming the bonding material film 8, As from the impurity diffusion region 3 is made of W. W is not diffused into the electrode/wiring 5, and W of the electrode/wiring 5 does not penetrate (spike) into the silicon semiconductor substrate 1. Note that the bonding material film 8
It is known that AI+2 (%) Si, which is a constituent material, exhibits good electrical bonding characteristics with both the impurity diffusion region 3 formed by introducing As and the electrode/wiring 5 made of W.

FIGS. 8 to 10 are cross-sectional side views of essential parts of a semiconductor device at key points in the process for explaining the manufacturing of other embodiments of the present invention. I will explain with reference. Note that the same symbols as those used in FIGS. 1 to 7, FIG. 14, and FIG. 15 represent the same parts or have the same meanings. Furthermore, since the process up to forming the electrode contact window 4A is the same as that explained with reference to FIGS. 3 to 7, it will be omitted and will be explained from the next step.

See Figure 8 (1) By applying the CVD method, the thickness can be reduced to, for example, 20 mm.
A polycrystalline silicon film 10 having a thickness of approximately 0.00 (person) is formed.

(2) Reactive ion etching using CCl4 as the etching gas.

The polycrystalline silicon film 10 is anisotropically etched by applying the etching (RIE) method.

By this process, the polycrystalline silicon film 10 remains only on the sidewalls within the electrode contact window 4A, and the rest is removed.

See Figure 9 (3) By applying the magnetron sputtering method, platinum CPt with a thickness of, for example, about 900
>Film 11 is formed.

Refer to FIG. 10 (4) Annealing is performed at a temperature of, for example, 450 ('C) and a time of, for example, 30 [minutes].

Through this process, the PT film 11 in contact with silicon
Only that portion is converted into a platinum silicide (ptSt) film 12.

(5) Aqua regia as an etchant (nitric acid: hydrochloric acid = l:3
The remaining PT film 11 that has not been converted into PtSi is removed by applying a wet etching method in which the film is immersed in a temperature of 50 ("C)".

(A cover film 9 made of SiO2 is formed by applying the 61CVD method.

A semiconductor device manufactured in this manner also has the same advantages as a semiconductor device manufactured by the process described with reference to FIGS. 3 through 7.

FIGS. 11 to 13 are cross-sectional side views of essential parts of a semiconductor device at key points in the process for explaining the manufacturing of still another embodiment of the present invention, and these figures will be described below. This will be explained with reference to. In addition, Fig. 1 to Fig. 10, Fig. 1
The same symbols as those used in FIG. 4 and FIG. 15 represent the same parts or have the same meaning. Furthermore, since the process up to forming the glabellar insulating film 7 is the same as that explained with reference to FIGS. 3 to 7, it will be omitted, and the next step will be explained.

(See FIG. 11 Tl) A W film is formed on the glabella insulating film 7 by applying, for example, magnetron sputtering method.

(2) By applying a normal photolithography technique, the W film formed in the step (1) is patterned to form the electrode/wiring 13.

(3) The electrode/wiring 13 is annealed at a temperature of, for example, 1000 ("C). Note that the annealing in this case may also be performed as annealing of the electrode/wiring 5.

(By applying the 41CVD method, the electrode/wiring 13
A glabellar insulating film 14 made of S i 02 is formed to cover the area.

See FIG. 12 (5) Electrode contact windows that penetrate the glabella insulating film 14, the electrode/wiring 13, the interlayer insulating film 7, the electrode/wiring 5, and the interlayer insulating film 4 by applying normal photolithography technology. 4A to expose a part of the surface of the silicon semiconductor substrate 1.

(6) For example, by applying the magnetron sputtering method, the bonding material film 8 made of aluminum (An + 2 (%) St) is formed including the inside of the electrode contact window 4A.
form.

As a result, electrical bonding between impurity diffusion region 3, electrode/wiring 5, and electrode/wiring 13 is completed.

(7) Patterning the bonding material film 8 by applying normal photolithography technology.

(A cover film 9 made of SiO2 is formed by applying the 81CVD method.

The semiconductor device manufactured in this manner also has the same advantages as the semiconductor device manufactured by the process described with reference to FIGS. 3 to 7 or 8 to 10.

In step (5) explained with reference to FIG. 12, when the electrode contact window 4A is stopped up to the surface of the electrode/wiring 5,
Only the electrode/wiring 13 and the electrode/wiring 5 are electrically connected.

〔Effect of the invention〕

In the electrical junction structure of a semiconductor device according to the present invention,
An insulating film and an electrode/wiring formed on a semiconductor substrate, an electrode contact window penetrating through them, and a space between the electrode/wiring or between the electrode/wiring and the semiconductor substrate within the electrode contact window. and a bonding material film that performs electrical bonding.

Adopting the above configuration means that, from the viewpoint of the manufacturing process, the bonding material film for electrically bonding the semiconductor substrate and the electrodes/wirings, or between the electrodes/wirings, is used to connect the electrodes/wirings, the glabella insulating film, etc. is formed and annealed,
Therefore, the bonding material film is formed within the electrode contact window provided to penetrate through them.
It is completely unrelated to the process conditions for forming not only the lower layer but also the upper layer electrodes, wiring, etc. Therefore, the material can be selected arbitrarily, and it can be maintained in good condition as it was formed. This can contribute to improving the reliability of the electrical connection structure.

[Brief explanation of the drawing]

1 and 2 are a cutaway side view and a plan view of a main part of a semiconductor device placed at key points in the process for detailed explanation of the present invention, and FIGS. 3 to 7 show an embodiment of the present invention. 8 to 10 are cross-sectional side views of essential parts of a semiconductor device at key points in the process for explaining the case of manufacturing, and FIGS. 8 to 10 are key points in the process for explaining the case of manufacturing other embodiments of the present invention. FIGS. 11 to 13 are cross-sectional side views of the main parts of the semiconductor device at important points in the process for explaining the case of manufacturing other embodiments. 14 and 15 are cross-sectional side views of essential parts of a semiconductor device at key points in the process for explaining a conventional example. In the figure, 1 is a semiconductor substrate, 2 is an inter-element isolation insulating film,
3 is an impurity diffusion region, 4 is an interlayer insulating film, 4A is an electrode contact window, 5 is an electrode/wiring, 7 is an insulating film between the eyebrows, and 8 is a bonding material film. Patent Applicant Fujitsu Ltd. Representative Patent Attorney Akira Aitani Representative Patent Attorney Hiroshi Watanabe - Figure 3 Figure 2 Figure 4 Figure 5 Figure 9 Figure 1O Figure 7 Figure 11 Figure 12 Figure 13

Claims (1)

[Scope of Claims] An insulating film and an electrode/wiring formed on a semiconductor substrate, an electrode contact window penetrating the electrode/wiring and the insulating film, and an electrode contact window located within the electrode contact window between the electrode/wiring. Alternatively, an electrical bonding structure for a semiconductor device, comprising a bonding material film for electrically bonding the electrode/wiring and the semiconductor substrate.