JPS6373538A - Connectiom method of multilayer interconnection - Google Patents

Abstract

PURPOSE:To prevent decrease of yield due to short circuiting between a first and a second wirings via abnormal apertures of an interlayer insulation film caused by pin holes and the like of a resist film generated in an etching process to make through holes, by forming a second wiring pattern on the interlayer insulating film before the through holes are formed in the interlayer insulating film which covers the first wiring pattern. CONSTITUTION:A first wiring pattern 2 of aluminum is formed on the surface of a semiconductor substrate 1, and a silicon nitride film 3 is stuck on the whole surface thereof. Then aluminum is stuck on the whole surface, and a second wiring pattern 4 is formed by photo-lithography. In this process, a resist film 6 as an etching mask is not eliminated and left as it is. By photo-lithography, an aperture 8 is formed in a resist film 7 so as to span regions A and B, where A is a region in which the wiring pattern 2 and the wiring pattern 4 overlap with each other sandwitching the film 3, and B is a region in which they do not overlap. Then a through hole 9 is formed in the film 3 applying the resist films 6 and 7 to masks to expose the surface of the first wiring pattern 2.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for connecting multilayer wiring, and particularly to a method for connecting multilayer wiring, which connects overlapping wirings with interlayer insulating films in between in a conductor integrated circuit having a multilayer wiring structure. Regarding the method.

[Conventional technology]

Conventionally, this type of connection method involves forming a first wiring pattern using a first material, then covering the entire surface with an interlayer insulating film such as silicon dioxide or silicon nitride using a vapor phase growth method, etc. Through-holes are formed in this interlayer insulating film by etching to expose the surface of the first wiring pattern, and after completely removing the photoresist film used to open the through-holes, the entire surface is etched by sputtering or vacuum evaporation. A second wiring pattern is formed using the second material through the through-holes by photolithography again. It is common to electrically connect the onions.

[Problem that the invention seeks to solve]

The conventional multilayer wiring connection method described above often has the following drawbacks.

■ Because the second wiring pattern was formed after the first through hole was formed in the interlayer insulating film, if a pinhole was inserted into the photoresist film when forming the through hole, an abnormal opening would also be formed in the interlayer insulating film. The first wiring and the second wiring are short-circuited,
The yield of semiconductor integrated circuits decreases.

■ Photomask after the preparation process Master slice type semiconductor integrated circuit and mask R (JMO manufacturing process is long) where patterns are formed differently for each type of metal.

In contrast to the conventional multilayer wiring connection method described above, the present invention
Before forming through holes in the interlayer insulating film covering the first wiring pattern, a second wiring pattern is formed on the interlayer insulating film, and then the first and second wiring patterns are electrically connected. It has an original content.

[Means for solving problems]

The method for connecting multilayer wiring according to the present invention includes the steps of forming a first wiring pattern made of a first material on a substrate and then depositing an insulating film on the entire surface, and forming the first wiring pattern with the RHK sandwiched therebetween. forming a second wiring pattern made of a second material by photolithography so as to have a Σ portion overlapping with the pattern; and
While leaving the resist film of
providing an opening pattern in the resist film that spans both a region where the first wiring pattern overlaps with the second wiring pattern and a region where the first wiring pattern does not overlap, and masking the first and second resist films. Binding process A step of forming a through hole in the insulating film to expose the surface of the first wiring pattern, then a step of depositing a third material on the entire surface, and applying a first resist to the second resist. and removing the third material deposited on the surfaces of the resist film and the first and second resist films.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a drawing showing an embodiment of the present invention in the order of steps.
(a) to (d) are plan views, (e) to (h) are (11
XX@ longitudinal cross-sectional views corresponding to each of 3 to (d).

1 to 5 in FIG. 1 respectively represent semiconductor substrates with built-in semiconductor elements;
wiring pattern with a thickness of LO μm (Q@ silicon film, a second arrangement pattern with an aluminum island with a thickness of 0.8 μm, and a third wiring pattern with an aluminum island with a thickness of 0.2 μm). The wiring is Ruru.

A 0.5 μm thick aluminum film is deposited using a conventional method on the surface of a semiconductor substrate that houses semiconductor elements such as transistors.
A first wiring pattern 2 is formed using a silicon nitride film, and then a silicon nitride film 3 having a thickness of 1 μm is deposited on the entire surface using a plasma vapor deposition method. After that, the thickness is 0.8μ by sputtering method.
A second wiring pattern 4 is formed on the entire surface of the aluminum sheet by photolithographic etching. At this time, the resist film 6 is left as it is without being removed as a mask for etching. ), (e)).

In FIG. 1(a), a region where the first wiring pattern 2 sandwiches the silicon nitride film 3 and overlaps with the second wiring pattern 4 is designated as a region, and a region where they do not overlap is designated as a region B.

Next, holes 8 are formed in the resist film 7 by photolithography.

At this time, the openings 8 are formed so as to extend around both areas A and B shown in FIG.
A through hole 9 is formed in the silicon nitride film 3 using a parallel plate type plasma etching apparatus as a T-mask to expose the surface of the first wiring pattern 20 (FIG. 1(b)).
, (f)).

After that, aluminum with a thickness of α2 μm was applied to the entire surface using the sputtering method, leaving the resist a6.7.

- Deposit the film lO (Fig. 1 tc) = (g)
).

Finally, decide on the lift-off or remove the resist film 6.7 by applying a thinner layer on the resist film 6.7 and removing the resist film 6.7 as shown in Figure 1. d
), (As shown in hJ, the present invention has the first L and second wiring patterns 2 and 4 electrically connected via the third wiring 5 made of a full-I dicrystalline film having a thickness of α2 μm. A semiconductor integrated circuit is obtained.

In the embodiment shown in FIG. 1, the first and twentieth wiring patterns 2 and 4 are connected via the third wiring 5 at only one end of the second wiring pattern 40, but It is also possible to connect both ends of the second wiring pattern 4 by changing the size 'f. In addition, in the embodiment shown in FIG. 1, the number of layers of the wiring pattern was only two, but after the manufacturing process shown in FIG. By repeatedly forming the 31st wiring pattern on the backward film, the present invention can be applied regardless of the number of wiring patterns.

〔Effect of the invention〕

As explained above, in the present invention, before forming a through hole in an interlayer insulating film covering a first wiring pattern,
Since the wiring pattern is formed on the interlayer insulating film, the first and second wiring patterns are formed on the interlayer insulating film through abnormal openings in the interlayer insulating film that occur due to pinholes in the resist film during the etching process to open through holes. The effect of eliminating short-circuits and lower yields is due to the fact that the wiring is short-circuited and the yield decreases.For the same reason, master slicing semiconductor integrated circuits and masks)
It is effective in shortening the construction period of M.

[Brief explanation of the drawing]

FIG. 1 is a drawing showing an embodiment of the present invention in the order of steps,
(a) to (d) are plan views, (el to (hl are (al
It is a longitudinal cross-sectional view taken along the line XX corresponding to each of (d) to (d). DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... First wiring pattern, 3... Silicon nitride film, 4...
...Second Ill pattern, 5...Third wiring, 6a7...Resist film, 8...Opening hole, 9...Through hole, lO... Aluminum oxide film.

Claims (1)

[Claims] forming a first wiring pattern made of a first material on a substrate and then depositing an insulating film over the entire surface; forming a second wiring pattern made of the material by photolithography; and forming a second resist film by photolithography again while leaving the first resist film used to form the second wiring pattern. , providing an opening pattern spanning both an area where the first wiring pattern overlaps with the second wiring pattern and an area where the wiring pattern does not overlap, and forming a hole pattern through the insulating film using the first and second resist films as masks. a step of exposing the surface of the first wiring pattern by forming a hole, a step of depositing a third material on the entire surface, and a step of forming the first and second resist films and the first and second A method for connecting multilayer wiring, comprising the step of removing the third material deposited on the surface of the resist film.