JPH02310969A - Semiconductor element - Google Patents

Abstract

PURPOSE:To provide a semiconductor element having an enhancement-type MOSFET of high electrostatic breakdown strength by forming a protective element, which includes a first-conductivity-type region formed on the main surface of a substrate, a second-conductivity-type region arranged on a periphery thereof, and a high concentration second-conductivity-type region provided on a surface central part of the second-conductivity-type region. CONSTITUTION:A second gate protective element 14 which is provided between a second gate G2 and a source S is a back-to-back protective diode structure of p<+>-n-p. A first gate protective element 13 which is provided between a first gate G1 and the source S is an n<+>-n-p structure. The protective element 13 has the n<+>-n-p structure and formed in a structure which provides breakdown strength in the reverse-direction only when a positive voltage is applied to a first gate. Since the p-n junction is formed to have a large junction area, electrostatic breakdown strength can be improved.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device, particularly an enhancement type silicon MOS F E in which a protection element is arranged between the gate and the source.
T (Metal Oxide Sem1conduc
TOR (metal oxide film semiconductor field effect transistor).

[Conventional technology]

MOSFETs with silicon substrates are often used in tuners for televisions and VTRs.

For example, "National Technical Revo-" published by Ohmsha Co., Ltd.
lReport) J 19 B April 6th issue, Showa 6
On April 18, 1999, PTT to P17, an example of the development of a 4-pole MO3FET (dual gate MO3FET) suitable for electronic tuners for televisions, videos, etc. is described. In addition, Japanese Patent Application No. 62-232967 discloses an enhancement type dual gate silicon MO5FET.
is disclosed.

[Problem to be solved by the invention]

With the demand for lower voltage and cost reduction for TV tuners,
The enhancement type dual gate M03FET is
It is widely used because it can operate at low voltage when the tuner is mounted and has a simple wiring structure. Further, in order to prevent surge damage to the gate of the FET, a protection element is incorporated between the gate and the source. This protective element has a back-to-back structure, as described in the above-mentioned document.

Here, a conventional protection element, ie, a gate protection diode with a back-to-back structure, will be briefly explained with reference to FIG. The protective element 1 is formed directly on a p+ type silicon substrate 2 or, as shown in the figure, on a p type epitaxial layer 3 of the same conductivity type provided on the main surface of the substrate 2.

Selectively n-shaded regions 4 are formed on the main surface of this epitaxial layer 3.
is provided, and along the center (inner side) and outer periphery of this n-shaded area 4, a p÷10-shaped area is provided.

6 is provided, resulting in a pnp structure, in other words, two diodes are formed back-to-back. Further, in the same figure, 7 is an insulating film, 8 is the p-shaped region 5
This is an electrode for extraction.

The protection element with this structure exhibits current characteristics (Ls V.,) as shown in the graph of FIG. 8, which is 10 V.

A diode breakdown voltage of , -V is obtained.

By the way, the breaking strength of this protective element 1 is in the p◆decade region,
It is determined by the surface area (pn junction area) of No. 6 and the value of breakdown resistance, and the larger the area of the pn junction and the lower the resistance, the higher the breaking strength. Actual breakage is likely to occur in the inner p+ dec shape region where the bonding area is small.

Therefore, the present inventor considered increasing the bonding area, in other words, the surface area, of the inner p-type SIT region 5, thereby increasing the fracture strength. However, with this structure, the gate force is too strong! (c+-) increases, power gain (pc
), it has been found that a new problem arises in that it causes deterioration of high frequency characteristics such as noise figure (NF).

-4. There are normally-off enhancement type MOSFETs and normally-on depression type MOSFETs.
We focused on the fact that when using a 3FET, only a positive voltage is applied to the first gate, and no negative voltage is applied.If a negative voltage is applied, that is, if a surge occurs, the current The present invention was realized by realizing that the electrostatic breakdown strength could be improved by creating a forward-direction structure in which the liquid flows as it is.

An object of the present invention is to provide a semiconductor device having an enhancement type MOSFET with high electrostatic breakdown strength.

Another object of the present invention is to provide a semiconductor device with low gate input capacitance, excellent high frequency characteristics, and high electrostatic breakdown strength.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, in the semiconductor device of the present invention, a protection element is disposed between the first gate and the source of an enhancement type MO3FET with a dual gate structure, and this protection element is formed of a p-type epitaxial layer having the same conductivity type as the substrate. It has a structure in which an n-shaded region is provided on the main surface of the n-shaded region, and an n-domain region with a high impurity concentration is provided at the center of the surface of the n-shade region, and a p-domain region is provided at the outer periphery.
The n+ type region is connected to the first gate, and the p type epitaxial layer and the p+ type region are connected to the source.

(Function) According to the above-mentioned means, in the semiconductor device according to the present invention, since the dual-gate structure MOSFET is an enhancement type, a positive voltage is applied to the first gate during use, and a negative voltage is applied to the first gate. Therefore, it is sufficient that the protection element provided between the first gate and the source has a reverse breakdown voltage when the first gate is biased positively (but has a breakdown voltage when a bias is applied negatively). In addition, the reverse breakdown voltage is formed by the pn junction portion formed by the nYi region and the P◆-shaped region provided along the outer periphery of this n shadow region. , and since this portion corresponds to a portion with a large pn junction area in a conventional back-to-back diode, the pn junction area becomes large and the electrostatic breakdown strength against a positive surge at the first gate increases.

Also, pn in the conventional back-to-pack diode
The portion corresponding to the small junction area is the junction surface of the n◆-type region of the same conductivity type with high impurity concentration as the n shadow region, and a pn junction is not formed and a forward bias occurs. A reduction in input capacitance can be achieved.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic diagram showing a cross section of a main part of a semiconductor element constituting a dual-gate silicon MO3FET with a protection diode according to an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram, and FIGS. 3 to 5 are FIG. 3 is a cross-sectional view of a wafer showing a state in which n-shaded regions are selectively formed on the main surface of the substrate; FIG.
The figure is a cross-sectional view of a wafer showing a state in which a p◆-shaped area is formed around the n-shaded area, and FIG. 5 is a cross-sectional view of a wafer showing a state in which an n◆-shaped area is formed in the center of the surface of the n-shaded area. , FIG. 6 is a graph similarly showing the current-voltage characteristics of the protection element provided between the first gate and the source.

As shown in FIG. 1, the semiconductor element (chip) 11 of this embodiment has a dual gate structure MOSFE in the center.
In addition to arranging T12, a protection element 13 for the first gate is monolithically incorporated between the first gate (G,) and the source (S) on the left side, and a protection element 13 for the first gate is monolithically incorporated between the second gate (G, ) and the source on the right side. It has a structure in which a second gate protection element 14 to be incorporated is arranged, and an equivalent circuit as shown in FIG. 2 is constructed. The MOSFET 12 with the dual gate structure is an enhancement type, and a diode 1 is connected between the source and the second gate as in the conventional case.
5.16 is incorporated into the back-to-back. On the other hand, when the first gate is in a positive state, a reverse breakdown voltage of the diode 17 is generated between the first gate and the source.
When the first gate is in a negative state, the direction is forward n◆-n
-p junction structure protection element (first gate protection element)
13 are provided.

Next, each part will be explained.

Enhancement type MOSF with the dual gate structure
The ET 12 has a structure having an n◆ type source region 20 and a drain region 21 in the surface layer portion of a p type epitaxial layer 3 provided on the main surface of a substrate 2 made of p◆ type silicon. Further, the source region 20 and the drain region 21
stoglI! on the main surface of the substrate 2 between. A gate oxide film 22 is provided. Further, on the gate oxide film 22, a first gate electrode 24 and a second gate electrode 25 each made of molybdenum (Mo) are provided from the source region 20 toward the drain region 21. In addition, the first gate electrode 24 and the second gate electrode 2
The main surface side of the substrate 2 including the gate oxide 5 and the gate oxide 11922 is covered with an insulating film 26 made of a SiO2 film. Also,
A contact hole is provided in the insulating film 26 facing the source region 20 and drain region 21, and an electrode made of aluminum is provided in the contact hole, and a source electrode 27 and a drain electrode 28 are formed, respectively. There is.

Furthermore, in this embodiment, between the source region 20 and the drain region 21, a high breakdown voltage layer 29 made of an n-type layer is provided.
is provided to increase the withstand voltage of the FET.

On the other hand, the second gate protection element 14 provided between the second gate (G,) and the source (S) includes the n-shade region 4 provided in the epitaxial layer 3, the surface layer portion of this n-shade region 4, p◆ provided along the center (inside) and outer periphery of
It has a p♦-n-p back-to-back protection diode structure. Further, on the central p♦-type region 5, an electrode 8i30 electrically connected to the second gate electrode 25 is provided.

On the other hand, the first gate protection element 13 provided between the first gate (G1) and the source (S) is connected to the n-shade region (second conductivity type region) provided in the epitaxial layer (first conductivity type region) 3.
conductivity type region) 4, an n-domain region (high concentration second conductivity type region) 31 with a high impurity concentration provided at the center (inner side) of the surface layer of the n shadow region 4, an outer peripheral portion of the n shadow region 4; It consists of a p-type region (first conductivity type region) 6 provided along the n◆-np structure.

Here, a method for manufacturing the first gate protection element 13 will be explained. In manufacturing the first gate protection element 13, as shown in FIG. Phosphorus is partially implanted into the 1 conductivity type region) 3 using the S10□ film 32 as a mask, and is diffused into the n
A shadow region (second conductivity type region) 4 is formed. Said substrate 2
The thickness is about 350 μm, and the impurity concentration, in other words, the specific resistance ρ is 0.01 to 0.02 Ωc.
m. Further, the epitaxial layer 3 has a thickness of about IO μm and a specific resistance of 30 Ωcm, although this is not particularly limited. In addition, the n-shaded region 4 has a diameter of 56 μm and a depth of 4 μm, and has a sheet resistance ρ of 240 Ω/hole (10'4 to 10'4 in impurity concentration).
10"cm-3).

Next, the Si0g film 32 is removed, and a new 5iOz film 33 is partially formed as shown in FIG.
is formed, and a p-type region (first conductivity type region) 6 is formed along the outer periphery of the n-shaded region 4 by deposition and diffusion using this SiO□ film 33 as a mask. This p-decade region 6 has a depth of 1. The inner diameter is 6 μm, the inner diameter is 48 μm, and the sheet resistance ρ is 30Ω/hole.

Next, the Sin film 33 is removed, and an insulating WA 26 is again provided partially as shown in FIG. An n-type region (high concentration second conductivity type region) 31 is formed at the center of the surface of the n-shaded region 4 . This n-shaped region 31 has a depth of 1. 5 μm, and the diameter is 28 μm. This n◆decade region 3゜pdecade region6. The dimensions of the n-shaded region 4 are the same as the dimensions of each part constituting the pnp of the second gate protection element 14. Therefore, the area of the pn junction formed by the p-type region 6, the epitaxial layer 3, and the n-shaded region 4 is wide, as in the conventional case, and the electrostatic breakdown strength is increased.

Further, the n-shaped region 31 and the n-shaded region 4 are a junction of the same conductivity type, and form a forward junction in which no reverse breakdown voltage occurs.

This reduces the pn junction capacitance, so the gate input capacitance! (C+-) can be kept small.

Next, as shown in FIG. 1, an electrode 34 connected to the first gate (G1) is formed on the n◆decade region 31, and a first gate protection element 13 is formed. Current characteristics (Ics Vas characteristics) of this first gate protection element 13
becomes as shown in FIG. That is, when a positive voltage is applied to the first gate, a withstand voltage of +1 is generated and the FET operates without any problem. Furthermore, since the reverse breakdown voltage has a wide pn junction surface as described above, the electrostatic breakdown strength increases. Since the MO3FET is an enhancement type, a negative voltage is not applied to the first gate when it is used. When a negative voltage is applied to the first gate, current flows because reverse breakdown voltage does not occur. Therefore, when a negative surge enters the first gate, a surge current flows, and surge breakdown at the junction does not occur, resulting in an increase in electrostatic breakdown strength.

In addition, although only the manufacturing method of the first gate protection element 13 was explained in the embodiment, the formation of each part was performed using the MO3FET1.
Of course, it is formed in conjunction with the formation of the gate protection element 2 and the second gate protection element 14.

For example, the n+-shaped region 31 is formed at the same time as the source region 20 and drain region 21 .

According to such an embodiment, the following effects can be obtained.

(1) In the enhancement type dual-gate structure MOSFET of the present invention, the protection element provided between the first gate and the source has a structure in which conductivity type regions are joined in three stages, but n◆ -n-p structure, and has a structure in which reverse breakdown voltage is obtained only when a positive voltage is applied to the first gate, and the p-n junction is selected at a location with a large junction area, resulting in electrostatic discharge damage. The effect of increasing strength can be obtained.

(2) According to (1) above, the conductivity type region of the protection element of the present invention has a three-stage series structure, but since the - group is a junction of the same conductivity type, this junction is a p-n junction. Since no is formed, it is possible to reduce the parasitic input capacitance.

(3) According to the above (1), according to the present invention, the conductivity type regions have a three-stage series structure, and since the - group is a junction of the same conductivity type, it is possible to obtain the effect of lowering the resistance. It will be done. For example, in the case of this embodiment, the resistance when a negative bias is applied to the first gate is partially reduced from several tens of ohms to several ohms in the case of a protection element with a back-to-back structure having the same dimensions. (4) According to (3) above, according to the present invention, when a negative surge is applied to the first gate, reverse breakdown voltage is not formed, so current flows easily and the electrostatic breakdown strength increases. Effects can be obtained.

(5) According to the above (1) and (4), the present invention has the effect that a protective element with high electrostatic breakdown strength can be obtained.

(6) According to the above (2), the MOSFET of the present invention can reduce the input capacitance, so that the effect of improving high frequency characteristics such as power gain and 9f1 sound index can be obtained.

(7) According to the above (1) to (6), the present invention provides a synergistic effect in that it is possible to provide a dual-gate MOSFET with excellent high frequency characteristics and high electrostatic breakdown strength.

Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the above Examples (although it is possible to make various changes without departing from the gist of the invention). Not even.

The above explanation will mainly focus on the dual-gate type M
Although the case where the present invention is applied to the O5FET manufacturing technology has been described, the present invention is not limited thereto.

The present invention can be applied at least to enhancement type MOSFET manufacturing technology.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

According to the present invention, the protection element provided between the first gate and the source of the enhancement type MO3FET is the same as that of the conventional back-to-back structure protection diode instead of using a pn junction in the junction part where current control is not required. Since the conductivity type regions are connected to each other and the pn junction is formed in the outer portion where the junction area is large, the electrostatic breakdown strength is increased along with the reduction in gate resistance. Furthermore, since some of the junctions are not pn junctions, input capacitance can be reduced and high frequency characteristics can be improved.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram showing a cross section of a main part of a semiconductor element constituting a dual-gate silicon MO3FET with a protection diode according to an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram, and FIG. 3 is a process for manufacturing a semiconductor element. selectively on the main surface of the substrate
FIG. 3 is a cross-sectional view showing a wafer with a shadow region formed thereon; FIG. 4 is a cross-sectional view of the wafer showing a p-shaped region formed around the n-shaded region, and FIG.
A cross-sectional view of the wafer showing a state in which an n+ dec-shaped region is formed at the center of the surface of the Y3jiff area, FIG. 6 is a graph showing the current-voltage characteristics of the protection element similarly provided between the first gate and the source, and FIG. FIG. 8 is a cross-sectional view showing a conventional protection diode structure, and a graph showing the current-voltage characteristics. DESCRIPTION OF SYMBOLS 1... Protective element, 2... Substrate, 3... Epitaxial layer, 4... N shadow region, 5, 6... P 10-shaped region,
7... Insulating film, 8... Electrode, 11... Semiconductor element (chip), 12... Protection element, 13... MOSF
ET section, I4... second gate protection element, 15-17
...Diode, 20... Source region, 21...
Drain region, 22... Gate oxide film, 24... First gate electrode, 25... Second gate electrode, 26...
Insulating film, 27... Source electrode, 28... Drain scraper, 29... High breakdown voltage layer, 30... Electrode, 31 =.
n-shaped region, 32.333-3in film, 1st
Figure 2 Figure 3 Next to Figure 3+
Punishment 4 @ Area゛

Claims (1)

[Claims] 1. A semiconductor device in which a protection element for preventing gate breakdown is monolithically provided between the gate and source of a field effect transistor, wherein the protection element is provided on a first main surface of a substrate.
A conductivity type region, a second conductivity type region disposed along the outer periphery of the first conductivity type region, and a high concentration second conductivity type region provided at the center of the surface of the second conductivity type region. A semiconductor element characterized in that: 2. The field effect transistor has a dual gate structure and is an enhancement type, and the protection element is disposed between the first gate and the source, and the first gate is connected to the high concentration second conductivity type region. The semiconductor device according to claim 1, characterized in that it has a structure.