JPH02310658A - Address control system - Google Patents

Abstract

PURPOSE:To realize high-speed transfer by providing the inside of a data transferring device with the register of a transfer processing identification number, a flag register, an address register, and a buffer address generating means, and updating the address register by half the number portion after the processing of half of the identification numbers is finished, and starting the processing of a following half portion. CONSTITUTION:When the processing of half the number close to an address shown by the address register is finished wholly, base addresses are updated by the area portion of the processing of half the number, and simultaneously, the contents of a flag is turned into an unprocessed state. The buffer address generation circuit 11 generates the address of a buffer memory 21 from the value of a base address register 14 and the value of an ID register 15. Since the base address holds the head address of the area of half the number portion of parallel processing, it has the higher order of the address necessary for the buffer memory 21, and a lower order is generated from the identification number. Thus, data transfer is speeded up.

Description

[Detailed Description of the Invention] [Summary] Regarding an address control method for a data transfer buffer memory in a data transfer device arranged between a main storage device and an external device, Address control in a data transfer device that is placed between a main storage device and an external device and controls data transfer between the external device and the main storage device, with the aim of transferring data at high speed and efficiently. In the method, the data transfer device has a transfer memory for transfer, and transfer processing is performed in parallel via the buffer memory, in which each of the continuous areas of the buffer memory is provided in the data transfer device. , a register that stores a series of identification numbers assigned for transfer processing, a flag register that holds the processing status for each processing of the identification number, and an address register that holds the base address of the area to which the identification number is allocated. and buffer address creation means for adding the identification number and the base address to calculate a new base address, and updating an address corresponding to an area corresponding to half of the identification numbers of all the identification numbers based on the new base address. When the processing of the half of the identification numbers closest to the address indicated by the address register is completed, the address register is updated for the half, the flag of the corresponding processing status is reset, and the processing for the next half is completed. Configure to start processing.

[Industrial application field]

The present invention relates to an address control method in a data transfer device that controls data transfer between a main storage device and an external device such as a high-speed input/output device or an expanded storage device, and in particular to a buffer for transfer in the data transfer device. Concerning memory area allocation and control of its addresses.

[Conventional technology]

FIG. 6 is a layout diagram of the data transfer device, and as shown, the data transfer device 2 is arranged between the main storage device 1 and the external device 3. The data transfer device 2 is provided with a buffer memory 21 for transfer. During data transfer from the main storage device 1 to the external device 3, the buffer memory 21 uses ■, ■,
The data is received from the main storage device 1 in the order of (2), and when all data is received, it is transferred to the external device 3 in the order of (a), (b), and (C).

FIGS. 7(a) and 7(b) are explanatory diagrams of transfer processing in the data transfer device. (a) is sequential processing, and (ra) is parallel processing.

In the sequential processing of (a), when the data transfer device 2 sends (REQ) (REQ) to the main storage device 1,
After the time required for accessing the main storage device 1, the data (3) is returned from the main storage device 1.

When the data transfer device 2 receives the data (■), it then sends the REQ (■) to the main storage device 1 and at the same time
Perform the data transfer in a).

In this way, the data transfer device 2 sends the REQ to the main storage device 1.
No processing is performed until the data for that REQ is returned.

On the other hand, in the parallel processing of (a), when the data transfer device 2 sends the REQ (■) to the main storage device 1, the data (■) from the main storage device 1 is received one after another without waiting for the data to be received.
Sends the REQ (2) to the main storage device 1. In this way, R
The EQ is sent out continuously, and the data is transferred from the main memory l.
When ■ and ■ are returned, immediately send ■ to the external device 3.
While receiving data, send (a), which is data in ■,
Transfer is performed sequentially as shown in (b) and (C).

[Problem to be solved by the invention]

According to the conventional data transfer described above, the successive data (fetch data) of ■, ■, ■ from the main storage device 1 is accessed not only from the external device 3 but also from the CPU, etc. ■It is not necessarily fetched in the order of
The fetch order varies depending on whether the main storage device I is busy or the like, and the data are not necessarily sent sequentially. Therefore, it is necessary to manage how far the buffer memory 21 has received data, and the amount of circuitry required for this management becomes enormous.

FIG. 8 is an explanatory diagram of the storage state of the buffer memory 21, where the diagonal line IA indicates the received data area, and the blank area B
indicates an area where data has not yet arrived because another device is using the area in the main storage device l. In this manner, the buffer memory 21 has areas in which data has been received from the main storage device l and areas in which data has not yet arrived, and is in a so-called "unselected" state. Therefore, after sending the area A that can be sent to the external device 3 from the buffer memory 21, the data transfer device 2 must wait before sending data to the external device 3 until the unarrived area is filled with received data.

The flag registers F1 to Fn and address registers R1 to Rn in the data transfer device 2 are provided as many as the number of parallel processes. The flag issues REQ to the main memory 1 and stores the data transfer from the main memory 1 in two states: received and unarrived, and the address register stores the address of the data unarrived area of the buffer memo IJ21. I'll keep it. Therefore, this address indicates the location where data should be stored when it is returned from the main memory device 1. In this way RE
Among the issued buffer addresses of Q, an area smaller than the smallest address among the unarrived area addresses becomes an area that can be sent to the external device 3.

Therefore, address registers for the number of parallel processes are required to store the addresses of the unarrived areas, and a comparison circuit is required to find the minimum value of the addresses of the unarrived areas, which requires an enormous amount of circuitry. .

An object of the present invention is to provide an address control method that simplifies the amount of hardware for data transfer in a data transfer device and that can transfer data between an external device and a main storage device at high speed and efficiently. It is about providing.

[Means to solve the problem]

The present invention provides an address control method in a data transfer device (2) that is disposed between a main storage device (1) and an external device (3) and controls data transfer between the external device and the main storage device. The data transfer device is a transfer buffer memo! J (21) and performs transfer processing in parallel via the buffer memory, the data transfer device includes a series of data allocated to each continuous area of the buffer memory for transfer processing. 1 of the identification numbers
a flag register (support) that holds the processing status for each process of the identification number, an address register register that holds the base address of the area to which the identification number is assigned, and an address register register that holds the base address of the area to which the identification number is assigned; and a buffer address creation means 0υ for calculating a new base address by adding the base address and updating the address corresponding to an area corresponding to half of the identification numbers of all the identification numbers based on the new base address, When the processing of the half of the identification numbers closest to the address indicated by the address register is completed, the address register is updated for the half, the flag of the corresponding processing status is reset, and the processing for the next half is started. It is characterized by being made to do.

FIG. 1 is a diagram showing the principle configuration of the present invention. In the figure, 11 is a buffer address creation circuit that adds identification number 10 and base address BADD to create a buffer address, 12 is a flag register that stores the status of each area of the buffer memory 21, and 13 is a flag that decodes identification number 10. a decoder that sets a flag for the relevant area of the register 12; 14 a pace address register that stores a base address; 15;
1 is an IO register that stores an identification number corresponding to the fetch data currently being transferred, and 16 is an address incrementing means. These circuits and the buffer memory 21 are provided in the data transfer device 2 as described above, and the data transfer device 2 is arranged between the main storage device 1 and the external device 3.

[For production]

FIGS. 2(a) and 2(a) are schematic diagrams for explaining the present invention shown in FIG. 1. This figure shows a case where there are eight pieces of data to be processed in parallel. In (a), the buffer memory 21
For example, process identification numbers In from 0 to 7 are assigned to a continuous series of areas. In this case, base address B
ADD indicates 100. In the state of (a), the shaded areas of IO 0 to 3 and 5 are areas where data has been received,
4. 6. 7 is an area where no data has arrived. Such a state is indicated in the flag register 12 as being received or requested, corresponding to the identification number 10, as shown in FIG. 3(a). That is, identification numbers IQ00-3 and 5 have been received, and 4, 6.7 indicate that a request is being made.

Here, if the first half of all the identification numbers have been received, the data in this area is transferred to the external device 3, and it waits until the latter half, including the unarrived area, is filled with data.

In the example of (a), data 0 to 3 are first sent to the external device 3, and data 4 to 7 are placed on standby because there is an unarrived area. Then, as shown in (b), the areas 0 to 3 whose transfer has been completed are provided as the next unprocessed area after 7. In this case, the base address BADD moves to area 4.

The state of (b) is shown in the flag register as shown in FIG. 3, et al. That is, 0 to 3 indicate that a request is yet to be issued, 5 indicates that it has been received, and 4°6.7 indicates that a request is in progress.

In order to perform such an operation, the base address BADD is held in the base address register 14 shown in FIG. The incrementing means, for example, the counter 16, increments the base address and can update the address corresponding to half the area of parallel processing, as shown in FIG. 3, et al. The state of the flag is stored as either accessing the main storage device 1 by issuing a REQ, or completion of access from the main storage device 1 has been received.

In this way, in the present invention, as shown in FIG. 2(a),
Fetch requests to the main storage device 1 for processes 0 to 7 associated with each area of the buffer memory are sequentially issued. As mentioned above, the time it takes for the fetch data to be returned from the main storage device 1 varies, and when the hatched part in (a) indicates that the fetch data has been received, the contents of the flag are as shown in FIG. 3 (a). become that way. Then, half of the processes close to the address indicated by the address register (in the example of FIG. 2(a), identification numbers 0 to 3) are processed.
) is completed, update the base address by half of the processing area, and at the same time update the contents of the corresponding flag as shown in Figure 3 (
Leave it in an untreated state as shown in 0 to 3 of b). Therefore, the states of the address register and flag become respectively (FIG. 2 et al.) and FIG. 3 et al.), and access to the newly unprocessed parts of identification numbers 0 to 3 is started.

〔Example〕

FIG. 4 is a block diagram of an embodiment of the present invention, and FIG. 5 is an explanatory diagram of a method of creating a buffer address. In FIG. 4, the buffer address generation circuit 11 generates a buffer memory 21 from the value of the base address register 14 and the value of the 0 register 15.
Create an address for. Since the base address holds the start address of half the area for parallel processing, it has the upper address of the address necessary for the buffer memory 21, and the lower address is created from the identification number. In other words, in the case of Fig. 2 (a), it is obtained by concatenating the base address excluding the lowest bit (LSB) and the identification number, and in the case of Fig. 2 (a), for the identification numbers 4 to 7. Do the same, and for 0 to 3, the 5th
It is obtained by adding one bit of "1" to the position shown in the figure. Therefore, the condition for adding “1” is BAD
D (LSB) -10 (MSB).

〔Effect of the invention〕

As described above, according to the present invention, it is possible to simplify the amount of hardware for data transfer within a data transfer device, and to transfer data between a main storage device and an external device at high speed and efficiency. It can be done in a specific manner. In other words, it is not necessary to have as many buffer memory address registers as there are parallel processes, and it is only necessary to have one base address register and one buffer address creation circuit each. Therefore, it is possible to reduce the amount of hardware and perform address control efficiently. can.

[Brief explanation of the drawing]

Figure 1 is a diagram of the principle configuration of the present invention; Figures 2 (a) and 2) are explanatory diagrams of the area of the buffer memory of the present invention; Figures 3 (a) and (b) are the contents of the flag register of the present invention. 4 is a configuration diagram of an embodiment of the present invention. FIG. 5 is an explanatory diagram of addition of a base address and an identification number. FIG. 6 is a layout diagram of a data transfer device. b) is an explanatory diagram of a conventional transfer process, and FIG. 8 is an explanatory diagram of a data area of a buffer memory. (Explanation of symbols) 1... Main memory device, 2... Data transfer device, 3... External device, 11... Buffer address creation circuit, 12... Flag register, 13... Decoder, 14...Base address register, 15...IO register, 16...Addition circuit, 21...Buffer memory, IO...Identification number, BADD...Base address.

Claims (1)

[Scope of Claims] 1. An address control method in a data transfer device that is disposed between a main storage device and an external device and controls data transfer between the external device and the main storage device, The data transfer device has a buffer memory for transfer, and performs transfer processing in parallel via the buffer memory, and in the data transfer device, each continuous area of the buffer memory is provided with a series of data for transfer processing. a register that stores an identification number for a transfer process that accesses the buffer memory, a flag register that holds the processing status for each process of the identification number, and a base address of the area to which the identification number is allocated. Add the identification number and base address to the address register to be held, calculate a new base address, and update the address corresponding to the area for half of the identification numbers of all identification numbers based on the new base address. buffer address creation means, when processing of the half of the identification numbers closer to the address indicated by the address register is completed, updates the address register by half, and resets the flag of the corresponding processing status; A buffer memory address control method characterized in that processing for the next half is started.