JPH02310658A - Address control system - Google Patents

Address control system

Info

Publication number
JPH02310658A
JPH02310658A JP13128089A JP13128089A JPH02310658A JP H02310658 A JPH02310658 A JP H02310658A JP 13128089 A JP13128089 A JP 13128089A JP 13128089 A JP13128089 A JP 13128089A JP H02310658 A JPH02310658 A JP H02310658A
Authority
JP
Japan
Prior art keywords
address
register
processing
identification
buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13128089A
Other languages
Japanese (ja)
Inventor
Hiroyuki Tsujita
Miyuki Maeda
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP13128089A priority Critical patent/JPH02310658A/en
Publication of JPH02310658A publication Critical patent/JPH02310658A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To realize high-speed transfer by providing the inside of a data transferring device with the register of a transfer processing identification number, a flag register, an address register, and a buffer address generating means, and updating the address register by half the number portion after the processing of half of the identification numbers is finished, and starting the processing of a following half portion.
CONSTITUTION: When the processing of half the number close to an address shown by the address register is finished wholly, base addresses are updated by the area portion of the processing of half the number, and simultaneously, the contents of a flag is turned into an unprocessed state. The buffer address generation circuit 11 generates the address of a buffer memory 21 from the value of a base address register 14 and the value of an ID register 15. Since the base address holds the head address of the area of half the number portion of parallel processing, it has the higher order of the address necessary for the buffer memory 21, and a lower order is generated from the identification number. Thus, data transfer is speeded up.
COPYRIGHT: (C)1990,JPO&Japio
JP13128089A 1989-05-26 1989-05-26 Address control system Pending JPH02310658A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13128089A JPH02310658A (en) 1989-05-26 1989-05-26 Address control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13128089A JPH02310658A (en) 1989-05-26 1989-05-26 Address control system

Publications (1)

Publication Number Publication Date
JPH02310658A true JPH02310658A (en) 1990-12-26

Family

ID=15054252

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13128089A Pending JPH02310658A (en) 1989-05-26 1989-05-26 Address control system

Country Status (1)

Country Link
JP (1) JPH02310658A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7447696B1 (en) 1998-09-17 2008-11-04 Ricoh Company, Ltd. Subcode-data generating circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7447696B1 (en) 1998-09-17 2008-11-04 Ricoh Company, Ltd. Subcode-data generating circuit

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