JPH04308945A - Cache memory device - Google Patents

Abstract

PURPOSE:To simultaneously process plural refiles by providing a selecting means which selects a way to be refiled according to selection information outputted from an updating means. CONSTITUTION:At the time of the refine of a cache memory, an updating circuit 5 updates information for selecting the way to be refiled from among the plural ways set at each cache memory of the plural cache memories by a way selecting circuit 3, during the pertinent refile. Then, the way to be refiled is selected by the way selecting circuit 3 according to this selection information. For example, at a port O side, a port 0 side reference way code being a way code in the case that an access at the port 0 side is cache-hit, and a replacement way code outputted from a decode circuit 7A, and replaced with an LRU algorithm in the case the access is cache-missed, are inputted to the port 0 side way selecting circuit 3A. Then, the way is selected by a hit signal at the port 0 side and a miss signal at the port 0 side.

Description

[Detailed description of the invention]

[Object of the invention]

0002

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory device, and more particularly to a cache memory device that simultaneously processes a plurality of refill requests.

0003

[Prior Art] In recent years, in computer systems, CP
A cache memory device provided between the U and the main storage device has come to be widely used. This cache memory device has a shorter access time than the main memory device, and is configured using multiple small-capacity cache memories.By retaining part of the contents of the main memory device in the cache memory device, the main memory Access to the device is replaced with access to the cache memory device, thereby reducing the time required to access data in main memory.

0004

However, when the above-described conventional cache memory device is introduced into a computer system or the like in which a plurality of refill requests occur simultaneously, problems may occur. For example, among refill requests that occur simultaneously, if any two refill requests have the same set address, LRU (Least
Assume that the ``Recently Used'' algorithm is used. In the case of this LRU algorithm, the oldest referenced way is selected as the way to be replaced, so in the conventional method of changing the LRU information by referring to the data after the previous refill is completed, the refill occurs at the same time. The referenced LRU when
Subsequent refills will be performed before the information is changed.

[0005] Therefore, if refill requests that occur simultaneously as described above have the same set address,
The same way is selected, so that the previously refilled data does not remain in the cache, or two refills result in both refills being repeated indefinitely so that the data remains in the cache memory. It turns out.

The present invention has been made in view of the above problems, and provides cache memory that is refilled in different ways even when the same set address is requested for refill requests that occur simultaneously. The purpose is to provide equipment.

[Configuration of the invention]

[0008]

[Means for Solving the Problems] In order to achieve the above object, the cache memory device of the present invention includes a plurality of cache memories, a plurality of ways set for each cache memory, and when refilling the cache memory, It has an updating means for updating information for selecting a way to be refilled from among the plurality of ways during the refilling, and a selection means for selecting a way to be refilled according to selection information output from the updating means. The gist is:

[0009]

[Operation] When refilling the cache memory, the cache memory device of the present invention updates information for selecting a way to be refilled from among the plurality of ways during the refilling, and gives priority to the selection of the way to be refilled. Change the ranking. Therefore, for subsequent refills having the same set address, a way different from the previously performed way will be selected.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a diagram showing an example of the configuration of a device using a cache memory device according to the present invention. In addition,
In this embodiment, the LRU algorithm is used as the replacement algorithm.

In FIG. 1, the cache memory device of this embodiment performs cache access on port 0 side and port 1 side.
It is configured so that it can be performed simultaneously on two ports on the side, and the port 0 side will be explained first.

The port 0 side way selection circuit 3A as a selection means outputs the port 0 side reference way code which is the way code when the port 0 side access results in a cache hit, and the port 0 side reference way code which is the way code when the access on the port 0 side results in a cache miss. Replacement way codes to be replaced by the LRU algorithm are input to each of the input terminals, and a way is selected by a hit signal on the port 0 side and a miss signal on the port 0 side. In the way selection circuit 3A on the port 0 side, when the port 0 side hit signal is on, the reference way code of the port 0 side is outputted, and when the port 0 side miss signal is on, the replacement way code is outputted. . The output of the port 0 side way selection circuit 3A is input to the port 0 side update circuit 5A as an update means, and the LRU memory 1 is updated.

The reference history stored in the LRU memory 1 is updated by the port 0 side update circuit 5A.
The LRU corresponding to the port 0 side reference set address according to the way code selected by the side way selection circuit 3A.
The reference history recorded in memory 1 is updated.

On the other hand, a decoding circuit 7A is connected to the output of the LRU memory 1. LRU memory 1 is port 0
When the side miss signal is on, the contents of the LRU memory 1 corresponding to the port 0 side reference set address are output. The port 0 side decoding circuit 7A decodes the reference history recorded in the LRU memory 1 and outputs the code of the way that was referenced the oldest. This output is the port 0 side replacement way code. The port 0 side replacement way code is connected to the input of the port 0 side way selection circuit 3A,
The way to be replaced is registered in the LRU memory 1 so that it becomes the most recently referenced way.

In this embodiment, there are two memory ports, and the port 1 side has the same circuit configuration as the port 0 side, so a detailed explanation will be omitted. However, the LRU memory 1 is shared between the port 0 side and the port 1 side.

Next, the operation of this embodiment will be explained with reference to FIG.

In the cache memory device shown in FIG. 1, it is assumed that cache access is performed simultaneously on two ports, port 0 side and port 1 side. This cache memory device is connected to a CPU (not shown) that simultaneously performs two memory accesses, and each memory access is connected to the port 0 side and the port 1 side. When a memory access occurs in step S1, the CPU first performs a hit check in step S5, and if there is a cache hit, data is read from the cache memory in step S25 and the LRU is updated at the same time, and the process ends.

[0018] If one or both ports has a cache miss, the process proceeds to step S7, where the CPU is stalled and the CPU is stopped. The cache memory is refilled while the CPU is stopped.

The refilling procedure will be explained below. When refilling, a way to be replaced is determined in advance, and then refilling is performed for that way. Refilling is performed first on the port 0 side, and then on the port 1 side. Even during refilling, a hit check is performed at each machine cycle, and refill requests continue to occur until the data for the required address is refilled.

[0020] Furthermore, if both the port 0 side and the port 1 side have a cache hit (steps S11 and S17),
Steps S13, S15 and Step S19, respectively.
The process proceeds to step S23 without going through S21, and after the CPU stall is released, the process returns to step S3 and the CPU
U performs a hit check again in step S5. The data for the requested address is then accessed and
If there is a cache hit, the data is read from the cache memory in step S25 and at the same time the LRU
is updated and exits.

[0021] If there is no cache hit here, the process advances to step S7 and further refilling is performed.

Now, if the cache memory is referenced through the port 0 side, the way selection circuit 3A selects the port 0 side reference way code. As a result, the contents of the LRU memory 1 are changed by the port 0 side update circuit 5A.

The same applies when the cache from port 1 is referenced.

[0024] When the cache is referenced from both port 0 and port 1, two sets of changes to the LRU memory 1 are performed at the same time.

If a cache miss occurs on the port 0 side, the process advances to step S13, where the LRU memory 1 outputs the oldest accessed replacement way code at the port 0 side set address. This waycode determines the refill port.

If a cache miss occurs simultaneously on the port 0 side and the port 1 side, the refill for the data request with the highest priority, that is, the refill on the port 0 side is performed before the refill on the port 1 side. That is,
Proceeding from step S11 to steps S13 and S15, first, a replacement way on the port 0 side is found, and after refilling there, a hit check is performed again in steps S5 and S11. Then, a cache hit occurs on the port 0 side. If a cache miss occurs on the port 1 side, the port 1 side is refilled. Since the LRU memory 1 of the way to be replaced at this time has been changed by refilling on the port 0 side, different ways are refilled even if the port 0 side and port 1 side have the same set address.

As described above, according to this embodiment, even if the same set address is requested for refill requests that occur simultaneously, refills are performed in different ways.

[0028]

[Effects of the Invention] As explained above, according to the present invention,
Since the priority information related to way selection is changed during refilling, even if refills performed at the same time have the same set address, different ways will be refilled.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a configuration example of a cache memory device according to the present invention.

FIG. 2 is a flowchart showing a processing procedure of the cache memory device shown in FIG. 1;

[Explanation of symbols]

1 LRU memory 3A Port 0 side way selection circuit 5A Port 0 side update circuit 7A Port 0 side decoding circuit 3B Port 1 side way selection circuit 5B Port 1 side update circuit 7B Port 1 side decoding circuit

Claims (2)

[Claims] Claim 1: A plurality of cache memories, a plurality of ways set for each cache memory, and updating of information for selecting a way to be refilled from among the plurality of ways when refilling the cache memory. What is claimed is: 1. A cache memory device comprising: updating means for performing internal updating; and selecting means for selecting a way to be refilled according to selection information output from the updating means. 2. The cache memory device according to claim 1, further comprising the step of confirming that data at a requested address exists in the cache memory at the end of refilling.