JP3490006B2 - Instruction control apparatus and method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an instruction control device and a method thereof, and more particularly, in an information processing device having a reservation station, when an address dependency relationship occurs between a preceding store instruction and a subsequent fetch request, The present invention relates to an instruction control device and method for performing efficient arithmetic control with a small amount of hardware.

[0002]

2. Description of the Related Art In an information processing apparatus capable of executing instructions out of order in order to execute instruction processing at high speed, a decoded instruction is stored in a decoded instruction storage means called a reservation station after an instruction decoding cycle. Then, the instruction for which the source operand is usable is selected regardless of the decoding order, and the instruction is issued from the reservation station to the arithmetic unit.

By the way, when there is an address dependency between instructions that require memory access, it must be guaranteed that the memory is referenced in program order. That is, when the subsequent instruction fetches data from the memory area updated by the preceding store instruction, it must be guaranteed that the latest data is fetched.

FIG. 1 shows an example of the configuration of a conventional instruction control device. In FIG. 1, the address adder 1
At 1 , the register contents are added and a memory address is generated. The address is sent to the cache RAM 12 , the corresponding memory contents are read out and supplied to the arithmetic unit 13. At the same time, the address is stored in the address array 14
And is used to check address dependency.

FIG. 2 shows an example of a conventional instruction execution time chart including a store instruction which is a memory operation instruction. Further, FIG. 3 shows an example of address data stored in the address array 14 when accessing the cache RAM. In FIG. 2, D cycle is instruction decoding cycle, P cycle is priority cycle, A cycle is address calculation and memory request cycle, and B cycle is B.
Is a cache RAM access cycle, and E is an operation cycle.

FIG. 2 shows an example in which the address of the preceding store instruction is obtained after the fetch request of the subsequent load instruction is completed as a result of performing the address calculation and the request out of order. Instructions are stored in the address array 14 according to a program order. Therefore, FIG.
3A, the load address of the subsequent instruction is at the subsequent address storage position at clock 3, and the store address which is the preceding instruction is at the previous stage of the address array 14 at the next clock 4 shown in FIG. 3B. Is stored in the storage location of.

The comparator 15 of FIG. 1 compares the memory access address of the succeeding instruction on the address array 14 with the store access address of the preceding instruction on the clock 4 and outputs an instruction re-fetch request signal if there is a match. To do. As a result, the subsequent load instruction is temporarily canceled by the signal output, and the canceled subsequent instruction is fetched again and executed after the preceding store instruction is executed. Conventionally, even if there is an address dependency relationship (store fetch relationship) between instructions that request memory access by the above processing, memory reference is guaranteed in program order.

[0008]

As described above, in the conventional device which attempts to execute the address calculation for memory access out of order, the memory request by the subsequent load instruction and the request to the arithmetic unit are executed. Has already disappeared by.

Therefore, in order to re-execute the subsequent instruction after canceling it, it is necessary to newly take out the instruction and decode the re-instruction, and the execution speed of the memory operation instruction including the store instruction is greatly reduced. There was a problem of doing.

[0010]

According to the present invention, a reservation station having a flag indicating a store instruction, and a table indicating that the source operand of the instruction stored in the reservation station can be used,
An instruction is issued from the reservation station when the table indicates that the source operand can be used, and when an issue of a store instruction is detected by the flag, a fetch request for the subsequent instruction is issued and a request for calculating the address of the store instruction is made. And an instruction issue control means for making the device wait for completion of the instruction.

The instruction control device further comprises a plurality of request ports capable of simultaneously executing a plurality of memory access requests, and the instruction issue control means issues a store request by the store instruction to only one of the request ports. The memory fetch request that is permitted and is issued to another request port at the same time as the store request is limited to the request from the preceding instruction of the store instruction.

According to the invention, the instruction control device further comprises means for dispatching the decoded instruction directly to the address calculation unit at the same time as decoding the instruction, and when the decoded instruction is accompanied by a memory access request, Decoded when the address calculation unit is unavailable, the source operand from the table is unavailable, or there is a store instruction for which the address calculation is not completed in the reservation station. The instruction creates a reservation station entry.

The instruction controller further comprises means for simultaneously dispatching a plurality of simultaneously decoded instructions to the address calculation unit, and if a preceding instruction of the simultaneously decoded instructions is accompanied by a store request, then Instructions with subsequent memory requests create reservation station entries.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 4 shows an example of the basic configuration of an instruction control device according to the present invention. In FIG. 4, the instruction on the instruction register 21 is decoded and stored in the reservation station 22. The command issuance control unit 23
The address adder (EAG1) 25 is selected by selecting two instructions with the same source on the reservation station 22.
And 26 (EAG2).

The instructions issued to the address adders 25 and 26 include register addresses for address calculation as necessary information. The general purpose register (GR) 24 is accessed based on each of the register addresses,
The contents thus read out are sent to the corresponding address adders (EAG1) 25 and (EAG2) 26, respectively. The address adders 25 and 26 correspond to the address adder 11 shown in FIG. 1, and their outputs are the same as in the conventional cache RAM 12 and address array 1.
Given to 4.

FIG. 5 shows the reservation station 22.
1 shows an example of the configuration. Further, FIG. 6 shows a configuration example of the instruction issue control unit 23. In FIG. 5, the decoded instruction from the instruction register 21 is temporarily stored in each entry (RSA) on the reservation station 22.
0, RSA1, RSA2, ...) are stored in the decoding order. Each entry has a base register number (BA),
The index register number (XA) and the validity flag (V) are included. Further, in the present invention, a store flag (ST) is especially provided.

The instruction issue control unit 23 of FIG. 6 indexes the register update pending table 27 by the base register number and index register number of each entry on the reservation station 22, and the general register 24 used by the instruction in each entry is It outputs a signal indicating whether it is available. For example, when the base register number (BA) and the index register number (XA) are composed of 4 bits, 16 general-purpose registers are individually designated. The register update suspension table 27 indicates that the general-purpose register is being updated in the preceding instruction, and if the general instruction is being updated, the subsequent instruction cannot use the register.

The selection circuit 28 decodes the signal from the register update pending table 27, appropriately accesses the general purpose register 24 that can be used by the decoded signal, and the content read from it is used as the address adder 25 of the next stage. Two
6 is selectively output.

FIG. 7 shows an operation flow example of the selection circuit 28. In this example, three entries RSA0 to RSA0 on the reservation station 22 are read in the order of decoding the instructions.
RSA2 is formed. Therefore, the instruction with the oldest decoding order is RSA0, and the instruction with the newest decoding order is RSA.
Stored in 2 respectively.

In FIG. 7, first, whether or not the source register of the instruction stored in each entry RSA0-RSA2 of the reservation station 22 can be used is indexed by the register update pending table 27. Then, it is determined whether or not the instruction having the oldest entry (that is, the preceding instruction) among the instructions usable in the source register (S10).
1).

Next, using the store flag (ST) provided on the reservation station, it is judged whether or not there is a store instruction in an entry older than itself and whether or not it is a store instruction (S102 and S10).
3). As a result, if the user is not the store instruction (ST = 0), the address adder (EAG1) is moved to (S104),
On the contrary, when the self is the store instruction (ST = 1), it is given to the address adder (EAG2) (S105).

On the other hand, if the source register can be used by 2
If it is the instruction of the second oldest entry and there is no store instruction in the entry older than itself, the address adder (EA
It is given to G2) 26 (S106-108). Other commands are temporarily stopped.

FIGS. 8 to 13 show an example of a decoder of the selection circuit which realizes the flow of FIG. In FIG. 8, each entry R of the reservation station 22
A + RSAx_READY signal (x = 0 to 2) indicating the availability of the source data is generated for each of SA0 to RSA2. Here, the + RSAx_V signal indicates that the instruction of the corresponding entry is valid (V = 1), and also + R.
The SAx_BA_R and + RSAx_XA_R signals indicate that they are available (READY) as a result of indexing the base register and index register of the instruction of the corresponding entry in the register update pending table 27.

FIG. 9 shows the address adder (EAG1) 2
5 shows an example of a decoder that selects the 5 side (S10).
4). Here, the RSAx_GO1 signal indicates that the instruction of the corresponding entry is given to the EAG1 side. FIG. 10 shows the logical table of FIG. For example, the RSA1_GO1 signal is the oldest entry available in the source register (-RSA0_REA
DY and + RSA1_READY), and there is no store instruction older than itself and neither is the store instruction itself (-R
SA0_ST and -RSA1_ST).

FIG. 11 shows an address adder (EAG2).
26 shows an example of a decoder that selects the 26 side (S1
05 and 108). Here, the RSAx_GO2 signal indicates that the instruction of the corresponding entry is given to the EAG2 side. FIG. 12 shows the logical table of FIG. For example, for the RSA1 instruction, the RSA1_GO2 signal is generated in the following cases.

That is, two source registers can be used.
Second oldest entry (+ RSA0_READY and +
It is in RSA1_READY) and it is not a store instruction (-RSA1_ST), or the oldest entry (-RSA0_READ) that can use the source register.
Y and + RSA1_READY) and (+ RSA1_ST) when it is a store instruction.

FIG. 13 shows the above-mentioned + RSAx_GO1.
An example of a signal (+ EAG1_BA) which is a logical product of a signal and a + RSAx_BA signal (BA flag) and outputs a base address to the address adder (EAG1) 25 side is shown. Although not shown here, the + EAG1_XA signal is similarly output for the index address. Also, + EAG2_BA and + EAG2_X
The same applies to the A signal. These are output from the selection circuit 28 of FIG. 6 as addresses of the general-purpose register 24 at the next stage.

FIG. 14 shows an example of an arithmetic instruction execution time chart according to the present invention. According to the selection operation flow of FIG. 7, the address information of the store instruction of the oldest entry is given to the address adder (EAG2) 26 side. Therefore, as shown in FIG. 14, the address information of the subsequent load instruction that fetches the address destination of the preceding store instruction is given to the address adder (EAG1) 25 side in the next clock cycle.

FIG. 15 shows an example of data stored in the address array 14 in FIG. In the present invention, the address of the store instruction is always obtained first (clock 4 in this example), and the address of the subsequent load instruction is obtained at the next clock 5. As a result, even if there is an address dependency between the instructions requesting the memory access, the memory reference is guaranteed in the program order without re-executing the subsequent instruction unlike the conventional example.

FIG. 16 shows another configuration example of the instruction control device according to the present invention. The difference between FIG. 16 and FIG. 4 described above is that the instruction register 21 is configured to be able to decode a plurality of instructions at the same time, and the decoded instructions are issued under certain conditions without going through the reservation station 22. Bypass route 29 issued directly to the control unit 23
Is the point. In this example, the instruction register 21 can simultaneously decode two instructions, IWR0 and IWR1.

FIG. 17 shows an operation flow example of the selection circuit 28 in this example. 18 to 22 show an example of a decoder of the selection circuit that realizes the flow of FIG. In FIG. 17, first, steps S201 to S2
At 04, it is judged whether or not an instruction can be issued from the reservation station 22 to the address adders (EAG1) 25 and (EAG2) 26. That is, when there is no entry for storing the command issued from the reservation station 22 to the EAG1, 1 is set to the 0_RSA_GO signal indicating that (S202 and 202).

Subsequently, when there is no entry for storing the instruction issued from the reservation station 22 to the EAG2, 1 is set to the 1_RSA_GO signal indicating the instruction (S203 and 204). As shown in the upper part of FIG. 18, the 0_RSA_GO signal and the 1_RSA_GO signal include a logical product of the negative values of the RSAx_GO1 signals and a negative value of the RSAx_GO2 signals shown in FIGS. 9 and 11.

Next, in step S205, it is determined whether the decoded instruction IWR0 in the instruction register 21 can be issued to EAG1. That is, if IWR0 is valid and EAG1 is available, IWR0 directly
1 is issued (S206). Also, if IWR0 is valid and EAG2 is available, IWR0 is issued to EAG2, while IWR0 is valid and EAG1 and EA
If the G2 cannot be used together, the IWR0 is stored in the reservation station 22 (S211).

The lower part of FIG. 18 shows an example of a concrete decoder for realizing the above logic. Further, FIG. 19 shows the logical table. Here, if IWR0 is valid (+ IWR0_BA_R, + IWR0_XA_R, and + IWR0_V) and EAG1 and EAG2 are available (+ 0_RSA_GO and + 1_RSA_GO), I
WR0 is issued to EAG1 (+ IWR0_GO
1). Also, EAG1 cannot be used (-0_RSA_G
If O), IWR0 is issued to EAG2 (+ IWR0
_GO2). In addition, IWR0 is valid (+ IWR0_
V) but EAG2 cannot be used (-1_RSA_
GO), IWR0 is reservation station 2
2 (+ IWR0_RSA).

The decoded instruction IWR1 in the instruction register 21 is also determined in the same manner. That is,
If IWR1 is valid and EAG1 is available, IW1
R1 is directly issued to EAG1 (S213). Also,
IW1 if IWR1 is valid and EAG2 is available
R1 is issued to EAG2 (S207). On the other hand, IW
If R1 is valid and both EAG1 and EAG2 are unusable, IWR1 reserves station 22.
(S209).

FIG. 20 shows an example of a concrete decoder for realizing the above logic. Further, FIG. 21 shows the logical table. For example, when IWR0 is neither valid nor a store instruction (-IWR0_V,-
IWR0_ST) and IWR1 are valid (+ IWR1_BA
_R, + IWR1_XA_R, and + IWR1_V) enable EAG1 and EAG2 (+ 0_RSA_GO
And + 1_RSA_GO), IWR1 is issued to EAG1 (+ IWR1_GO1).

IWR1 is valid (+ IWR1_V)
However, when the address calculators 25 and 26 are not usable (-0_RSA_GO, -1_RSA_GO), when the source operand is not usable (-IWR1
_BA_R, -IWR1_XA_R), preceding IWR
When 0 is a store instruction (+ IWR0_ST) in which the address calculation of the reservation station is not completed, or when the issuing conditions are not met, IWR1 is temporarily stored in the reservation station 22 (+ IWR
1_RSA). Note that the decoding circuit of FIG.
Works the same as the circuit.

FIG. 23 shows an example of arithmetic operation of the instruction control device of FIG. FIG. 23A shows a case (+ IWR0_GO1, + IWR1_GO2) when two load instructions from the instruction register 21 are simultaneously issued to the address adders (EAG1) 25 and (EAG2) 26. In this case, there is no address dependency between the load instructions, and the two instructions are executed independently.

In FIG. 23 (b), the preceding load instruction (IWR0) is in EAG1 and the following store instruction (IWR0) is in EAG1.
1) is issued to EAG2 at the same time (+ IWR0_
GO1, + IWR1_GO2) is shown. In this case as well, the preceding load instruction does not have an address dependency relationship with the following instruction, so that the two instructions are executed independently.

FIG. 23C shows the case where the preceding instruction is the store instruction (IWR0) and the subsequent instruction is the load instruction. In this case, the preceding store instruction is issued to EAG2 (+ IWR0_GO2), and the subsequent load instruction (IWR1) is temporarily stored in the reservation station 22 (+ IWR1_RS) at the same clock timing.
A). Then, at the next clock timing, the reservation station 22 issues the load instruction to EAG1 (+ RSAx_GO1). Therefore, also in this case, the address dependency due to the store fetch does not occur as described with reference to FIG.

[0041]

As described above, according to the present invention, the address calculation start timing of the instruction issued from the reservation station is controlled by a simple decoding means,
This prevents the address calculation request of the subsequent instruction from overtaking the address calculation request of the preceding instruction, thereby enabling high-speed arithmetic execution of the load instruction following the store instruction.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration example of a conventional instruction control device.

FIG. 2 is a diagram showing an example of a conventional instruction operation execution time chart including a store instruction.

FIG. 3 is a diagram showing an example of address data stored in an address array when accessing the cache RAM of FIG.

FIG. 4 is a diagram showing a basic configuration example of an instruction control device according to the present invention.

FIG. 5 is a diagram showing a configuration example of a reservation station.

FIG. 6 is a diagram showing a configuration example of an instruction issuance control unit.

FIG. 7 is a diagram showing an operation flow example (1) of the selection circuit.

FIG. 8 is a diagram showing a configuration example (1-1) of a selection circuit.

FIG. 9 is a diagram showing a configuration example (1-2) of a selection circuit.

FIG. 10 is a diagram showing a logical table of FIG. 9.

FIG. 11 is a diagram showing a configuration example (1-3) of a selection circuit.

12 is a diagram showing the logical table of FIG. 11. FIG.

FIG. 13 is a diagram showing a configuration example (1-4) of a selection circuit.

FIG. 14 is a diagram showing an example of an arithmetic instruction execution time chart according to the present invention.

FIG. 15 is a diagram showing an example of data stored in an address array according to FIG.

FIG. 16 is a diagram showing another configuration example of the instruction control device according to the present invention.

FIG. 17 is a diagram showing an operation flow example (2) of the selection circuit.

FIG. 18 is a diagram showing a configuration example (2-1) of a selection circuit.

19 is a diagram showing the logical table of FIG. 18. FIG.

FIG. 20 is a diagram showing a configuration example (2-2) of the selection circuit.

FIG. 21 is a diagram showing the logical table of FIG. 20.

FIG. 22 is a diagram showing a configuration example (2-3) of the selection circuit.

FIG. 23 is a diagram showing another example of the arithmetic instruction execution time chart according to the present invention.

[Explanation of symbols]

12 ... Cache RAM 13 ... Arithmetic unit 14 ... Address array 15 ... Comparator 21 ... Instruction register 22 ... Reservation station 23 ... Instruction issue control unit 24 ... General-purpose register 11, 25, 26 ... Address adder 27 ... Register update pending table 28 ... Selection circuit

Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G06F 9/38

Claims (7)

(57) [Claims] 1. A reservation station having a flag indicating a store instruction, a table indicating that a source operand of an instruction stored in the reservation station can be used, and an instruction issued from the reservation station is used by the table as a source operand. And an instruction issue control means for holding the fetch request of the subsequent instruction when the issue of the store instruction is detected by the flag and waiting until the address calculation and the request of the store instruction are completed. An instruction control device characterized by the above. 2. A plurality of request ports capable of simultaneously executing a plurality of memory access requests are provided, and the instruction issuance control means permits the store request by the store instruction to be issued to only one of the request ports. The memory fetch request issued to another request port at the same time as the store request is only a request from a preceding instruction of the store instruction.
The command control device described. 3. Further comprising means for dispatching the decoded instruction directly to the address calculation unit at the same time as decoding the instruction, wherein the address calculation unit is unusable when the decoded instruction involves a memory access request, The decoded instruction creates a reservation station entry if either the source operand from the table indicates an unusable instruction or the reservation station has a store instruction whose address calculation is not complete. The instruction control device according to 1 or 2. 4. The method further comprises means for simultaneously dispatching a plurality of simultaneously decoded instructions to an address calculation unit, and if a preceding instruction of the simultaneously decoded instructions accompanies a store request, its subsequent memory. The command controller according to claim 1 or 2, wherein the command accompanied by the request creates a reservation station entry. 5. An instruction control method for an information processing apparatus having a reservation station for storing a plurality of decoded instructions, wherein a store instruction is detected when the instruction is issued from the reservation station. fetch request instructions issued following a store instruction consists, to wait for the address calculation and the request of the store instruction is completed, further wherein the information processing apparatus memory access request
Equipped with multiple request ports that can execute multiple
And is issued subsequent to the detected store instruction.
Waiting for an instruction fetch request waits for a store request by the store instruction.
Permission to issue to only one of the export ports, and to other request ports at the same time as the store request
The memory fetch request issued is the store instruction
The instruction control method is characterized in that the request is only from the preceding instruction of . 6. The instruction control method according to claim 5, which is executed by. 6. The information processing device further decodes an instruction.
At the same time, the decoded instruction is directly converted to the address calculation unit.
Means for dispatching to the detected
Fetch request for instruction issued after store instruction
Waits if the decoded instruction is accompanied by a memory access request.
If the address calculation unit cannot be used,
Source operand from the table indicates that it cannot be used, or
Completion of address calculation at the reservation station
There is a store instruction that has not been executed.
Reservation Station
6. The temporary storage in
Command control method. 7. The information processing device further decodes at the same time.
Multiple instructions that have been executed simultaneously to the address calculation unit.
A means for patching the detected store
Wait fetch request of instructions to be issued following the instruction
The machine stores the instruction that precedes among the instructions decoded at the same time.
If accompanied by an est,
Instructions can be stored temporarily in the reservation station.
The instruction control method according to claim 5, which is executed by: