JPH02309694A - Multilayer circuit substrate - Google Patents

Abstract

PURPOSE:To response to a request for a high density mounting and to prevent its yield from decreasing by incorporating capacitor electrodes, and exposing at least one of the electrodes on the surface. CONSTITUTION:A capacitor section 4 has capacitor electrodes 5, 5a laminated in an opposed state, and the uppermost electrode 5a of the electrodes 5, 5' is exposed on the surface of a multilayer circuit substrate 1. Thus, the substrate 1 of the state in which passive components are contained or substantially contained including a capacitor, to respond to a request for a high density mounting. After the substrate 1 is obtained, the electrode 5a exposed of the surface can be trimmed, and an obtained capacity can be regulated. Accordingly its yield can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multilayer circuit board, and particularly to a multilayer circuit board incorporating a capacitor section.

[Background Art] In order to miniaturize electronic devices, high-density packaging of electronic circuits is rapidly progressing. In order to meet this demand, electronic components are being miniaturized and made into chips, but there are limits to miniaturization due to problems such as the accuracy of mounters. Therefore, in order to achieve higher density packaging of electronic circuits, methods have even been adopted in which passive components such as capacitors, inductors, and resistors are built into multilayer circuit boards made of ceramic, for example.

[Problems to be Solved by the Invention] However, simply incorporating passive components into a substrate results in a low yield of the resulting circuit. For example, if you build in 10 capacitors with a non-defective rate of 99%, the yield will be 90%, and if you build in 100 capacitors, the yield will be 5.
It drops to nearly 0%.

SUMMARY OF THE INVENTION An object of the present invention is to provide a multilayer circuit board including a capacitor portion that can meet the demands for high-density packaging and prevent a decrease in yield.

[Means for Solving the Problems] A multilayer circuit board according to the present invention includes a built-in capacitor section including capacitor electrodes stacked in a facing state.

And one of the capacitor electrodes is exposed on the surface.

[Function] In the multilayer circuit board according to the present invention, by trimming the capacitor electrode exposed on the surface with a laser beam or the like, the capacitance given by the capacitor section can be adjusted after the multilayer circuit board is obtained. be able to.

[Effects of the Invention] Therefore, according to the present invention, it is possible to obtain a multilayer circuit board in which passive components including capacitors are built-in or almost built-in, and it is possible to meet the demand for high-density packaging.

Further, as described above, after the multilayer circuit board is obtained, the capacitor electrodes exposed on the surface can be trimmed, and the acquired capacitance can be adjusted, so that the yield can be improved.

[Embodiment] FIG. 1 shows a multilayer circuit board 1 according to an embodiment of the present invention.
A part of is shown in cross-section.

The multilayer circuit board 1 includes a plurality of insulating ceramic layers 2 and a plurality of dielectric ceramic layers 3. A capacitor portion 4 is formed in the dielectric ceramic layer 3 so as to be surrounded by a broken line. The capacitor section 4 includes capacitor electrodes 5 and 5a stacked in a facing manner. These capacitor electrodes 5,
Among the capacitor electrodes 5a, the uppermost capacitor electrode 5a is exposed on the surface of the multilayer circuit board 1.

The capacitor electrodes 5, 5a are alternately connected by via hole connections 6 or 7, and the via hole connections 6, 7 are then connected to wiring portions 8, 9 formed between the insulating ceramic layers 2, respectively. Ru. Note that the wiring portions 8.9 do not necessarily need to be formed in different layers.

Note that illustration of other electrical elements connected to the wiring sections 8 and 9 is omitted.

In manufacturing such a multilayer circuit board 1, for the insulating ceramic layer 2, B a O-A Q 203
, S102, etc. as a main component and can be fired at 950'C.On the other hand, for the dielectric ceramic layer 3, a ceramic green sheet that has lead-based perovskite as a main component and can be fired at 950'C is prepared. It will be prepared. On these sheets are the necessary capacitor electrodes 5.5a.

In order to provide the via hole connection portions 6.7 and the wiring portions 8, 9, a metal base mainly composed of copper, for example, is formed by printing or the like. After these sheets are laminated, they are fired together.

In the thus obtained multilayer circuit board 1, for example, while measuring the capacitance provided by the capacitor section 4 at an appropriate part on the extension of the wiring section 8.9, by a method such as laser or sandblasting, The capacitor electrode 5a exposed on the surface can be trimmed.

High-density packaging made possible by the present invention will be explained with reference to FIGS. 2 and 3.

These drawings are drawn to scale. Also, the second
The figures show the case of the present invention, and FIG. 3 shows the case where a chip capacitor 11 is mounted on an ordinary printed circuit board 10. In both cases, four capacitors are included.

In FIG. 2, capacitor electrodes 13 exposed on the surface of the capacitor electrodes forming four capacitor sections are shown on the multilayer circuit board 12, and a via is associated with each of these capacitor electrodes 13. A hole connection 14 is shown.

On the other hand, in FIG. 3, on the printed circuit board 10,
Land wiring portions 15 are formed, and these land wiring portions 15
Chip capacitor 11 is mounted in a state where it is electrically connected to.

As can be seen from the comparison between FIG. 2 and FIG. 3, the multilayer circuit board 12 according to the present invention has a smaller area than the case where the chip capacitor 11 is mounted on the printed circuit board 10. can.

The reason for this is, first, that the land wiring portion 15 shown in FIG. 3 is unnecessary. In addition, as shown in FIG. 3, when using discrete chip capacitors 11, the dimensions of the chip capacitors 11 themselves are required for handling purposes, and the spacing between these chip capacitors 11 must also be It needs to be large enough to
As shown in FIG. 2, if the capacitor part is formed built into the multilayer circuit board 12, there will be no handling problems, and the area given by the multilayer circuit board 12 can be efficiently used to acquire capacitance. This is because the area can be used as a region for forming a capacitor electrode. Furthermore, the external dimensions of the discrete chip capacitor 11 cannot be used 100% for forming the capacitor electrode, and the fact that the external dimension is larger than that of the capacitor electrode is also the reason why the area becomes larger in FIG. 1
It is one.

In addition, in the above-described embodiment, a high dielectric constant lead-based perovskite was used as the dielectric material constituting the dielectric ceramic layer 3 (FIG. 1), but the invention is not limited to this. The material constituting the ceramic layer 3 may be used as it is for the ceramic layer 3.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing a part of a multilayer circuit board 1 according to an embodiment of the present invention. 2 and 3 are schematic plan views for explaining the present invention in detail, in which FIG. 2 shows a multilayer circuit board 12 according to the present invention, and FIG.
The figure shows a chip capacitor 11 on a printed circuit board 10.
The case is shown when equipped with . In the figure, 1.12 is a multilayer circuit board, 3 is a dielectric ceramic layer, 4 is a capacitor section, and 5.5a. 13 is a capacitor electrode; 6. 7. 14 is a via hole connection part.

Claims (1)

[Claims] A multilayer circuit board having a built-in capacitor section including capacitor electrodes stacked in a facing state, and at least one of the capacitor electrodes being exposed on the surface.