JPH02308556A - Semiconductor device and method of mounting the same - Google Patents
Semiconductor device and method of mounting the sameInfo
- Publication number
- JPH02308556A JPH02308556A JP1131000A JP13100089A JPH02308556A JP H02308556 A JPH02308556 A JP H02308556A JP 1131000 A JP1131000 A JP 1131000A JP 13100089 A JP13100089 A JP 13100089A JP H02308556 A JPH02308556 A JP H02308556A
- Authority
- JP
- Japan
- Prior art keywords
- resin composition
- semiconductor device
- epoxy resin
- mounting
- cured
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 238000000034 method Methods 0.000 title claims abstract description 14
- 239000003822 epoxy resin Substances 0.000 claims abstract description 37
- 229920000647 polyepoxide Polymers 0.000 claims abstract description 37
- 239000000203 mixture Substances 0.000 claims abstract description 31
- 229910000679 solder Inorganic materials 0.000 claims abstract description 19
- 238000010521 absorption reaction Methods 0.000 claims description 16
- 229920005989 resin Polymers 0.000 abstract description 6
- 239000011347 resin Substances 0.000 abstract description 6
- 239000004593 Epoxy Substances 0.000 abstract description 5
- 238000007789 sealing Methods 0.000 abstract description 4
- 238000007598 dipping method Methods 0.000 abstract description 2
- 230000015556 catabolic process Effects 0.000 abstract 3
- 239000011342 resin composition Substances 0.000 abstract 2
- 238000005336 cracking Methods 0.000 abstract 1
- 239000011256 inorganic filler Substances 0.000 description 7
- 229910003475 inorganic filler Inorganic materials 0.000 description 7
- 229920003986 novolac Polymers 0.000 description 5
- 239000005011 phenolic resin Substances 0.000 description 5
- 239000000654 additive Substances 0.000 description 4
- 238000002156 mixing Methods 0.000 description 4
- 239000002245 particle Substances 0.000 description 4
- 239000003795 chemical substances by application Substances 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 3
- 125000002887 hydroxy group Chemical group [H]O* 0.000 description 3
- 238000013001 point bending Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- RNFJDJUURJAICM-UHFFFAOYSA-N 2,2,4,4,6,6-hexaphenoxy-1,3,5-triaza-2$l^{5},4$l^{5},6$l^{5}-triphosphacyclohexa-1,3,5-triene Chemical compound N=1P(OC=2C=CC=CC=2)(OC=2C=CC=CC=2)=NP(OC=2C=CC=CC=2)(OC=2C=CC=CC=2)=NP=1(OC=1C=CC=CC=1)OC1=CC=CC=C1 RNFJDJUURJAICM-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000003063 flame retardant Substances 0.000 description 2
- 238000007656 fracture toughness test Methods 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- 239000006082 mold release agent Substances 0.000 description 2
- 239000000843 powder Substances 0.000 description 2
- 239000002994 raw material Substances 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- QTWJRLJHJPIABL-UHFFFAOYSA-N 2-methylphenol;3-methylphenol;4-methylphenol Chemical compound CC1=CC=C(O)C=C1.CC1=CC=CC(O)=C1.CC1=CC=CC=C1O QTWJRLJHJPIABL-UHFFFAOYSA-N 0.000 description 1
- 102100027199 Cell death-inducing p53-target protein 1 Human genes 0.000 description 1
- 101100136092 Drosophila melanogaster peng gene Proteins 0.000 description 1
- 101000914537 Homo sapiens Cell death-inducing p53-target protein 1 Proteins 0.000 description 1
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N Phenol Chemical compound OC1=CC=CC=C1 ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 1
- -1 Polyethylene Polymers 0.000 description 1
- 239000004698 Polyethylene Substances 0.000 description 1
- 239000004793 Polystyrene Substances 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910000410 antimony oxide Inorganic materials 0.000 description 1
- 239000003054 catalyst Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
- 239000007891 compressed tablet Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 239000007822 coupling agent Substances 0.000 description 1
- 229930003836 cresol Natural products 0.000 description 1
- GYZLOYUZLJXAJU-UHFFFAOYSA-N diglycidyl ether Chemical compound C1OC1COCC1CO1 GYZLOYUZLJXAJU-UHFFFAOYSA-N 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 125000003700 epoxy group Chemical group 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004898 kneading Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- VTRUBDSFZJNXHI-UHFFFAOYSA-N oxoantimony Chemical compound [Sb]=O VTRUBDSFZJNXHI-UHFFFAOYSA-N 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 229920000573 polyethylene Polymers 0.000 description 1
- 229920002223 polystyrene Polymers 0.000 description 1
- 238000002203 pretreatment Methods 0.000 description 1
- 238000010298 pulverizing process Methods 0.000 description 1
- 239000003826 tablet Substances 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置およびその実装方法に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device and a method for mounting the same.
トランジスタ、ＩＣ，ＬＳＩ等の半導体素子は、外部環
境゛からの保護の観点および素子のハンドリングを可能
にする観点から、プラスチックパッケージ等により封止
され半導体装置化されている。この種のパッケージの代
表例としては、デユア。2. Description of the Related Art Semiconductor elements such as transistors, ICs, and LSIs are sealed in plastic packages and the like to form semiconductor devices from the viewpoint of protection from the external environment and from the viewpoint of enabling handling of the elements. A typical example of this type of package is Dua.
ルインラインパッケージＣＤＩＰ）がある、このＤＩＰ
は、ビン挿入型のものであり、実装基板に対してビンを
挿入することにより半導体装置を取りつけるようになっ
ている。This DIP has a Ruin Line Package CDIP)
is a bottle insertion type, and the semiconductor device is mounted by inserting the bottle into the mounting board.
最近は、ＬＳＩチップ等の半導体装置の高集積化と高速
化が進んでおり、加えて電子装置を小形で高機能にする
要求から、実装の高密度化が進んでいる。このような観
点からＤＩＰのようなピン挿入形のパッケージに代えて
、表面実装型パッケージが主流になってきている。この
種のパッケージを用いた半導体装置においては、平面的
にピンを取り出し、これを実装基板表面に、載せその状
態で半田浴に浸漬し半田によって実装固定するようにな
っている。このような表面実装型半導体装置は、薄い、
軽い、小さいという利点を備えており、したがって実装
基板に対する占有面積が小さくてすむという利点を備え
ているうえ、基板に対する両面実装も可能であるという
長所も有している。Recently, the integration and speed of semiconductor devices such as LSI chips have been increasing, and in addition, the demand for smaller and more highly functional electronic devices has led to higher density packaging. From this point of view, surface mount type packages have become mainstream instead of pin insertion type packages such as DIP. In a semiconductor device using this type of package, pins are taken out in a plane, placed on the surface of a mounting board, immersed in a solder bath, and mounted and fixed with solder. Such surface-mounted semiconductor devices are thin,
It has the advantage of being light and small, and therefore occupies a small area on the mounting board, and also has the advantage of being able to be mounted on both sides of the board.
ところが、上記のような表面実装用パッケージを用いた
半導体装置において、実装前にパッケージ自体が吸湿し
ている場合には、半田実装時に水分の蒸気圧によって、
パッケージにクラックが生じるという問題がある。すな
わち、第１図に示すような表面実装型半導体装置におい
て、水分は矢印へのように封止樹脂１を通って、またリ
ードフレーム２と封止樹脂１との隙間を通ってパッケー
ジ３内に侵入し、主としてリードフレーム２のグイボン
ドパッド４の裏面に滞溜する。そして、半田表面実装を
行う際に、上記滞溜水分が、上記半田実装における加熱
により気化し、その蒸気圧により、第２図に示すように
、グイボンドバッド４の裏面の樹脂部分を下方に押しや
り、そこに空隙５をつくると同時にパッケージ３にクラ
ック６を生じさせる。第１図および第２図において、７
は半導体素子、８はワイヤーボンディングである。However, in a semiconductor device using a surface mount package as described above, if the package itself absorbs moisture before mounting, the vapor pressure of the moisture during solder mounting causes
There is a problem that cracks occur in the package. That is, in the surface-mounted semiconductor device as shown in FIG. It invades and accumulates mainly on the back surface of the bond pad 4 of the lead frame 2. Then, when performing solder surface mounting, the accumulated moisture is vaporized by the heating during the solder mounting, and the vapor pressure causes the resin part on the back side of the Guibond pad 4 to move downward, as shown in FIG. The package 3 is pushed away, creating a gap 5 there and at the same time causing a crack 6 in the package 3. In Figures 1 and 2, 7
8 is a semiconductor element, and 8 is a wire bonding.
このような間−に対する解決策として、半導体素子をパ
ッケージで封止した後、得られる半導体装置全体を密封
し、表面実装の直前に開封して使用する方法や、表面実
装の直前に上記半導体装置を１０′０℃で２４時間乾燥
させ、その後半田実装を行うという方法が提案され、す
でに実施されている。しかしながら、このような前処理
方法によれば、製造工程が長くなるうえ、手間が掛かる
という問題がある。As a solution to this problem, there are methods in which the semiconductor element is sealed in a package, the entire semiconductor device obtained is sealed, and the package is opened and used immediately before surface mounting, or the semiconductor device is sealed immediately before surface mounting. A method of drying at 10'0° C. for 24 hours and then performing solder mounting has been proposed and has already been implemented. However, such a pretreatment method has the problem that the manufacturing process becomes long and labor-intensive.
本発明は、このような事情に鑑みなされたもので、半田
浸漬による表面実装時の耐クラツク性に優れた半導体装
置およびそれを効率よく実装する方法の提供をその目的
とする。The present invention was made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device with excellent crack resistance during surface mounting by solder dipping, and a method for efficiently mounting the same.
上記の目的を達成するため、本発明は、下記の特性（Ａ
）および（Ｂ）の少なくとも一方を備えたエポキシ樹脂
組成物で半導体素子を封止する半導体装置を第１の要旨
とし、
（Ａ）エポキシ系樹脂組成物の硬化物の破壊じん性値が
、２５０″Ｃテ１．３ ｋｇ／ｍ”以上。In order to achieve the above object, the present invention has the following characteristics (A
) and (B). ``Cte 1.3 kg/m'' or more.
（Ｂ）エポキシ樹脂系組成物の硬化物の円板状成形品（
直径５０＋＋ｍｘ厚み３■）の吸湿率が０．３重量％以
下。(B) Disc-shaped molded product of cured epoxy resin composition (
Diameter 50++m x thickness 3cm) Moisture absorption rate is 0.3% by weight or less.
基板に半導体装置を搭載して半田浴に浸漬する実装方法
において、上記半導体装置が、（１）それ自体の硬化物
の破壊じん性値が２５０℃で１．３）ｃｇ／鵬３／を以
上か、もしくは■それ自体の硬化物の円板状成形品（直
径５０ｍＸ厚み３閣）の吸湿率が０゜３重量％以下かの
いずれか一方もしくは双方の特性を有するエポキシ系樹
脂組成物で樹脂封止されている半導体装置の実装方法を
第２の要旨とする。In a mounting method in which a semiconductor device is mounted on a substrate and immersed in a solder bath, the semiconductor device has: (1) a fracture toughness value of the cured product of itself at 250°C of 1.3) cg/Peng 3/ or more; or ■ The moisture absorption rate of the cured disc-shaped molded product (diameter 50 m x thickness 3 cm) is 0.3% by weight or less.An epoxy resin composition having one or both of the following characteristics The second gist is a method for mounting a sealed semiconductor device.
半田浸漬時におけるパッケージクラックの発生を防止す
る方法としては、■封止樹脂に対する吸湿を抑制する、
■グイボンドパッドの裏面および半導体素子の表面と封
止樹脂との間の接着力を高める、■封止樹脂自体の強度
もしくは破壊じん性値を高めるという三つの方法が考え
られる。本発明は、本発明者らが、多数の半導体装置の
実装実験の集積の結果、上記■に関連する要因としてエ
ポキシ樹脂組成物硬化物の円板状成形品の吸湿率を０．
３重量％（以下「％」と略す）にし、また■に関連する
要因としてエポキシ樹脂組成物硬化物の破壊じん性値を
２５０℃で１．３ ｋｇ／１ｘｉａ””にしそのいずれ
か一方もしくは双方を満足させると、半導体装置を半田
浴に浸漬して実装する際に、パッケージに全（クラック
が生じなくなるという知見にもとづいてなされたもので
ある。Methods to prevent package cracks from occurring during solder immersion include: - suppressing moisture absorption into the sealing resin;
Three methods can be considered: (1) increasing the adhesive strength between the back surface of the Guibond pad and the surface of the semiconductor element and the sealing resin; and (2) increasing the strength or fracture toughness of the sealing resin itself. In the present invention, as a result of the accumulation of numerous semiconductor device mounting experiments, the inventors determined that the moisture absorption rate of a disc-shaped molded product of a cured epoxy resin composition was 0.0.
3% by weight (hereinafter abbreviated as "%"), and as a factor related to (2), the fracture toughness value of the cured epoxy resin composition was set at 250°C to 1.3 kg/1xia'', either or both. This was based on the knowledge that if the above conditions are satisfied, no cracks will occur in the package when the semiconductor device is immersed in a solder bath and mounted.
本発明に用いるエポキシ系樹脂組成物は、エポキシ樹脂
（Ａ成分）とフェノール樹脂（Ｂ成分）と無機質充填剤
（Ｃ成分）とを用いて得られるものであって、通常、粉
末状もしくはそれを打錠したタブレット状になっている
。The epoxy resin composition used in the present invention is obtained using an epoxy resin (component A), a phenol resin (component B), and an inorganic filler (component C), and is usually in powder form or in powder form. It is in the form of a compressed tablet.
上記Ａ成分のエポキシ樹脂としては、特に限定するもの
ではなく、通常用いられるエポキシ樹脂があげられる。The epoxy resin of component A is not particularly limited, and includes commonly used epoxy resins.
なかでも、エポキシ当量が１５０〜２５０で軟化点が５
０〜１３０℃のノボラック型エポキシ樹脂を用いるのが
好適である。Among them, those with an epoxy equivalent of 150 to 250 and a softening point of 5
It is preferable to use a novolak type epoxy resin having a temperature of 0 to 130°C.
上記Ａ成分とともに用いられるＢ成分のフェノール樹脂
は、エポキシ樹脂の硬化剤として作用するものであり、
水酸基当量が７０〜１５０で軟化点が５０〜１１０℃の
ノボラック型フェノール樹脂を用いるのが好ましい。The phenol resin of the B component used together with the above A component acts as a curing agent for the epoxy resin,
It is preferable to use a novolak type phenol resin having a hydroxyl equivalent of 70 to 150 and a softening point of 50 to 110°C.
上記エポキシ樹脂（Ａ成分）とフェノール樹脂（Ｂ成分
）との配合比は、上記エポキシ樹脂中のエポキシ基１当
量当たりフェノール樹脂中の水酸基が０．８〜１．２当
量の範囲内に配合することが好適である。The blending ratio of the epoxy resin (A component) and the phenol resin (B component) is such that the amount of hydroxyl groups in the phenol resin is 0.8 to 1.2 equivalents per 1 equivalent of epoxy groups in the epoxy resin. It is preferable that
上記Ａ成分およびＢ成分とともに用いられるＣ成分の無
機質充填剤としては、特に限定するものではな〈従来公
知のものがあげられ、特に最大粒径１５０μｍ、平均粒
径２０μｍのものを用いるのが好ましい。そして、Ｃ成
分の無機質充填剤の含有量は、エポキシ樹脂組成物全体
の７５％以上に設定するのが好適である。特に好適なの
は７８％以上である。すなわち、無機質充填剤の含有量
が７８％を下回ると得られるエポキシ樹脂組成物の硬化
物の破壊じん性値が７．３ ｋｇ／ｍｍ””未満となり
耐クラツク性が低下するからである。ちなみに、無機質
充填剤の含有量が７８％の場合と７０％の場合とを比較
すると、７８％の場合の破壊じん性値は７０％の約２〜
３倍となる。また、得られるエポキシ樹脂組成物の硬化
物を特定のサイズの円板（直径５０ＩＩＩＩ１１×厚み
３ａｕａ）に成形してこの吸湿率の経時変化を測定する
と、含有１７８％の場合、８５℃／８５％ＲＨで７２時
間の条件において０．２５％となり、含有！−７０％の
場合と比較するとこの６０％程度に抑制される。The inorganic filler of component C used together with component A and component B is not particularly limited, and may include conventionally known inorganic fillers, and it is particularly preferable to use one with a maximum particle size of 150 μm and an average particle size of 20 μm. . The content of the inorganic filler as component C is preferably set to 75% or more of the entire epoxy resin composition. Particularly preferred is 78% or more. That is, if the content of the inorganic filler is less than 78%, the fracture toughness value of the cured product of the resulting epoxy resin composition will be less than 7.3 kg/mm'', resulting in a decrease in crack resistance. By the way, when comparing cases where the inorganic filler content is 78% and 70%, the fracture toughness value in the case of 78% is about 2 to 70%.
It will be tripled. In addition, when the cured product of the obtained epoxy resin composition was molded into a disk of a specific size (diameter 50III11 x thickness 3aua) and the change in moisture absorption rate over time was measured, when the content was 178%, it was 85°C/85% Contains 0.25% at RH for 72 hours! Compared to the case of -70%, it is suppressed to about 60%.
また、上記エポキシ樹脂組成物には、Ａ−Ｃ成分以外に
必要に応じてその他の添ｈ■剤を配合することができる
。In addition to the A-C components, other additives may be added to the epoxy resin composition as required.
上記その他の添加剤としては、硬化促進剤、離型剤２着
色剤、難燃剤、カップリング剤等があげられる。Examples of the above-mentioned other additives include a curing accelerator, a mold release agent, a coloring agent, a flame retardant, and a coupling agent.
本発明におけるエポキシ樹脂組成物は、例えばつぎのよ
うにして製造することができる。すなわち、上記Ａ−Ｃ
成分および必要に応じてその他の添加剤を適宜配合し予
備混合したのち、ミキシングロール機等の混練機にかけ
加熱状態で混練して溶融混練し、これを室温に冷却する
。つぎに、これを公知の手段によって粉砕し、必要に応
じて打錠するという一連の工程により製造することがで
きる。The epoxy resin composition in the present invention can be produced, for example, as follows. That is, the above A-C
After suitably blending and premixing the components and other additives as necessary, the mixture is kneaded in a heated state using a kneader such as a mixing roll machine to melt and knead the mixture, and the mixture is cooled to room temperature. Next, it can be manufactured through a series of steps of pulverizing this by known means and, if necessary, compressing it into tablets.
このようなエポキシ樹脂組成物を用いての半導体素子の
封止は、特に限定するものではなく、通常のトランスフ
ァー成形等の公知のモールド方法により行うことができ
る。上記半導体素子のモールドに用いるエポキシ樹脂組
成物としては、■その硬化物の破壊じん性値が２５０℃
で１．３ ｋｇ／■３″以上であるか、もしくは■その
硬化物からなる円板状成形品（直径５０閣×厚み３ｍｌ
１１）の吸湿率（８５℃／８５％ＲＨ）が０．３％以下
の値をとるか、または上記■、■の双方を備えているも
のを用いる必要がある。The encapsulation of a semiconductor element using such an epoxy resin composition is not particularly limited, and can be performed by a known molding method such as ordinary transfer molding. As for the epoxy resin composition used in the mold of the semiconductor element mentioned above, the fracture toughness value of the cured product is 250°C.
1.3 kg/■3" or more, or ■A disc-shaped molded product made of the cured product (diameter 50 mm x thickness 3 ml)
It is necessary to use a material having a moisture absorption rate (85° C./85% RH) of 11) of 0.3% or less, or having both of the above conditions (1) and (2).
このようにして作製された半導体装置を基板に搭載し、
従来公知の方法に従い半田浴に浸漬する。The semiconductor device manufactured in this way is mounted on a substrate,
It is immersed in a solder bath according to a conventionally known method.
ことにより、パッケージクラックを生じさせることなく
表面実装することができる。This allows surface mounting without causing package cracks.
なお、上記破壊じん性値は、エポキシ樹脂組成物の硬化
物を２５０℃２支点間距離６４ｍｍの３点曲げ破壊じん
性試験を行うことにより得られる値である。The above fracture toughness value is a value obtained by conducting a three-point bending fracture toughness test at 250° C. with a distance between two supporting points of 64 mm on the cured product of the epoxy resin composition.
また、上記吸湿率は、得られるエポキシ樹脂組成物を゛
トランスファープレスにより直径５０ａｕ＋＋。Moreover, the above moisture absorption rate was determined by applying the obtained epoxy resin composition to a diameter of 50 au++ using a transfer press.
厚み３ｍ＋ｉの円板に成形したのち、１７５℃で５時間
アフターキ五アーを行う。そして、この円板状成形品を
用い下記の値を求め、それを下記の式にしたがって演算
することにより得られる値である。After forming into a disk with a thickness of 3m+i, after-cooling was performed at 175°C for 5 hours. Then, the following values are determined using this disk-shaped molded product, and the values are obtained by calculating them according to the following formula.
以上のように、本発明によれば、硬化物が所定の破壊じ
ん性値および吸湿率を呈するエポキシ系樹脂組成物によ
って半導体素子を樹脂封止している。したがって、この
ものは、半田実装に際して、優れた耐クラツク性を奏す
る。また、本発明は、上記のようにして得られる半導体
装置を基板に搭載し半田浴に浸漬して表面実装する。こ
の場合、パッケージにクラックが全く生じない。このよ
うに、本発明は半田実装時にパッケージにクラックを全
く生じさせないものであり、特に薄形フラットパッケー
ジの表面実装において最適である。As described above, according to the present invention, a semiconductor element is resin-sealed with an epoxy resin composition whose cured product exhibits a predetermined fracture toughness value and moisture absorption rate. Therefore, this product exhibits excellent crack resistance during solder mounting. Further, in the present invention, the semiconductor device obtained as described above is mounted on a substrate and immersed in a solder bath for surface mounting. In this case, no cracks will occur in the package. As described above, the present invention does not cause any cracks in the package during solder mounting, and is particularly suitable for surface mounting of thin flat packages.
つぎに、実施例について比較例と併せて説明する。Next, examples will be described together with comparative examples.
まず、実施例および比較例で使用する成分原料を下記に
示す。First, the component raw materials used in Examples and Comparative Examples are shown below.
（主剤）
Ａ：クレゾールノボラック型エポキシ樹脂（ｎ＝４．エ
ポキシ当量１９５）
（硬化剤）
Ｂ：フェノールノボラック（ｎ＝４．水酸基当量１０６
）
（ｎはＧＰＣポリスチレン換算データの重量平均分子量
より計算した。）
（無機質充填剤）
Ｃ：最大粒径１５０μｍ、平均粒径２０ＤＩ１１の破砕
型溶融５ｉＯ２
（難燃剤）
Ｄ：ノボラック型ブロム化エポキシ樹脂Ｅ：亘酸化アン
チモン
（硬化触媒）
Ｆニジメチルイミダゾール
（離型剤）
Ｇ：ポリエチレンワックス
（添加剤）
Ｈニトリメトキシシラングリシジルエーテル〔実施例、
比較例１，２〕
上記に示した原料を後記の第１表に示す割合で配合し、
ミキシングロール機にかけてｌｏｏ″Ｃで１０分間混練
してシート状エポキシ樹脂組成物を作製した。ついで、
このシート状エポキシ樹脂組成物を粉砕し粉末状のエポ
キシ樹脂組成物を得た。(Main agent) A: Cresol novolac type epoxy resin (n = 4. Epoxy equivalent: 195) (Curing agent) B: Phenol novolac (n = 4. Hydroxyl equivalent: 106)
) (n was calculated from the weight average molecular weight of GPC polystyrene conversion data.) (Inorganic filler) C: Crushed type molten 5iO2 with maximum particle size of 150 μm and average particle size of 20 DI11 (Flame retardant) D: Novolak type brominated epoxy resin E: Antimony oxide (curing catalyst) F Nidimethylimidazole (mold release agent) G: Polyethylene wax (additive) H Nitrimethoxysilane glycidyl ether [Example,
Comparative Examples 1 and 2] The raw materials shown above were blended in the proportions shown in Table 1 below,
A sheet-like epoxy resin composition was prepared by kneading on a mixing roll machine at loo''C for 10 minutes. Then,
This sheet-like epoxy resin composition was crushed to obtain a powdered epoxy resin composition.
（以下余白）
（！□、
上記エポキシ樹脂組成物を用いてトランスファープレス
により３点曲げ破壊じん性試験用成形品を、１７５ ”
Ｃ，７０ｋｇ／ｃｄ、 ２分間の条件で成形し、つづ
いて１７５℃で５時間キュアーした。この破壊じん性試
験用成形品について、２５０℃下で支点間距離６４ｍの
３点曲げ試験を行った。その結果を後記の第２表に示し
た。また、上記と同様の条件で直径５０ｍｍ、厚み３Ｉ
ｎＩｎの円板状の硬化物を成形し、１７５℃，５時間キ
ュアーを行い、４８時間、７２時間、９６時間、１９２
時間の各吸湿率を前述の弐により算出した。その結果を
後記の第２表に示した。なお、吸湿条件：８５℃／８５
％ＲＨで測定した。(The following is a blank space) (!□, Using the above epoxy resin composition, a molded article for three-point bending fracture toughness test was made using a transfer press.
C, 70 kg/cd for 2 minutes, and then cured at 175° C. for 5 hours. This molded article for fracture toughness testing was subjected to a three-point bending test at 250° C. with a distance between fulcrums of 64 m. The results are shown in Table 2 below. Also, under the same conditions as above, a diameter of 50 mm and a thickness of 3I
A disc-shaped cured product of nIn was molded and cured at 175°C for 5 hours, followed by 48 hours, 72 hours, 96 hours, and 192 hours.
The moisture absorption rate for each hour was calculated as described above. The results are shown in Table 2 below. In addition, moisture absorption conditions: 85℃/85
Measured in %RH.
つぎに、上記エポキシ樹脂組成物を用いて薄形フラット
パッケージ（ＱＦＰ）（チップサイズ二幅６．０ｍｍ、
長さ６．０ｍｍ、厚み２．５ｍｍ）を上記と同様の条件
によりトランスファープレスで成形し、アフターキュア
ーした後、２６０℃の半田槽に１０秒間浸漬してクラッ
ク発生の有無を調べた。その結果を、後記の第２表に併
せて示した。Next, using the above epoxy resin composition, a thin flat package (QFP) (chip size 2 width 6.0 mm,
A piece (length: 6.0 mm, thickness: 2.5 mm) was molded using a transfer press under the same conditions as above, after-cured, and then immersed in a solder bath at 260° C. for 10 seconds to check for cracks. The results are also shown in Table 2 below.
（以下余白）
第２表の結果から、エポキシ樹脂組成物の硬化物の破壊
じん性値が１．３ ｋｇ ／ ｍｍ ””および円板状
成形品に成形した硬化物の吸湿率が０．３％以下である
実施例品は半田槽に浸漬径長時間経過してもパッケージ
クラックを生じなかった。このことから、実施例品が耐
クラツク性に優れていることがわかる。なお、上記第２
表の結果について、パッケージクランクの発生状態を第
３図に示した。図−において、縦軸は破壊じん性値、横
軸は吸湿率であり、斜線部分はパッケージクラックが発
生した領域である。このことから、エポキシ樹脂組成物
の硬化物の破壊じん性値が１．３ ｋｇ ／ ｍｍ””
もしくは円板状成形品に成形した硬化物の吸湿率が０．
３％以下のいずれか一方を満足していれば、パッケージ
クラックが生じていない。(Margins below) From the results in Table 2, it can be seen that the fracture toughness value of the cured product of the epoxy resin composition is 1.3 kg/mm "" and the moisture absorption rate of the cured product molded into a disc-shaped molded product is 0.3. % or less did not cause package cracks even after being immersed in a solder bath for a long time. This shows that the example products have excellent crack resistance. In addition, the above second
Regarding the results shown in the table, the state of occurrence of package crank is shown in FIG. In the figure, the vertical axis is the fracture toughness value, the horizontal axis is the moisture absorption rate, and the shaded area is the area where package cracks have occurred. From this, the fracture toughness value of the cured product of the epoxy resin composition is 1.3 kg/mm.
Or, the moisture absorption rate of the cured product molded into a disc-shaped molded product is 0.
If either one of 3% or less is satisfied, package cracks have not occurred.
第１図および第２図は従来の半導体装置のクラック発生
状態の説明図、第３図はパッケージクラック発生に対す
る吸湿率と破壊じん性値との関係を示す相関図である。
第１図
第２図FIGS. 1 and 2 are explanatory diagrams of the state of crack occurrence in a conventional semiconductor device, and FIG. 3 is a correlation diagram showing the relationship between the moisture absorption rate and the fracture toughness value with respect to the occurrence of package cracks. Figure 1 Figure 2
Claims (2)
を備えたエポキシ樹脂組成物で半導体素子を封止してな
ることを特徴とする半導体装置。 （Ａ）エポキシ系樹脂組成物の硬化物の破壊じん性値が
、２５０℃で１．３ｋｇ／ｍｍ＾３＾／＾２以上。 （Ｂ）エポキシ樹脂系組成物の硬化物の円板状成形品（
直径５０ｍｍ×厚み３ｍｍ）の吸湿率が０．３重量％以
下。(1) A semiconductor device characterized in that a semiconductor element is sealed with an epoxy resin composition having at least one of the following properties (A) and (B). (A) The fracture toughness value of the cured product of the epoxy resin composition is 1.3 kg/mm^3^/^2 or more at 250°C. (B) Disc-shaped molded product of cured epoxy resin composition (
(diameter 50mm x thickness 3mm) moisture absorption rate is 0.3% by weight or less.
装方法において、上記半導体装置が、（１）それ自体の
硬化物の破壊じん性値が２５０℃で１．３ｋｇ／ｍｍ＾
３＾／＾２以上か、もしくは２それ自体の硬化物の円板
状成形品（直径５０ｍｍ×厚み３ｍｍ）の吸湿率が０．
３重量％以下かのいずれか一方もしくは双方の特性を有
するエポキシ系樹脂組成物で樹脂封止されていることを
特徴とする半導体装置の実装方法。(2) In a mounting method in which a semiconductor device is mounted on a board and immersed in a solder bath, the semiconductor device has: (1) a fracture toughness value of the cured product itself of 1.3 kg/mm^ at 250°C;
3^/^2 or more, or the moisture absorption rate of a disk-shaped molded product (diameter 50 mm x thickness 3 mm) of the cured product of 2 itself is 0.
1. A method for mounting a semiconductor device, characterized in that the semiconductor device is encapsulated with an epoxy resin composition having one or both of the characteristics in an amount of 3% by weight or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13100089A JP3259958B2 (en) | 1989-05-23 | 1989-05-23 | Semiconductor device mounting method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13100089A JP3259958B2 (en) | 1989-05-23 | 1989-05-23 | Semiconductor device mounting method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02308556A true JPH02308556A (en) | 1990-12-21 |
| JP3259958B2 JP3259958B2 (en) | 2002-02-25 |
Family
ID=15047604
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13100089A Expired - Lifetime JP3259958B2 (en) | 1989-05-23 | 1989-05-23 | Semiconductor device mounting method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3259958B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014131053A (en) * | 2014-01-22 | 2014-07-10 | Nitto Denko Corp | Dicing tape integrated semiconductor rear face film, and method of manufacturing semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02175749A (en) * | 1988-12-28 | 1990-07-09 | Nippon Steel Chem Co Ltd | Sealing resin composition |
-
1989
- 1989-05-23 JP JP13100089A patent/JP3259958B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02175749A (en) * | 1988-12-28 | 1990-07-09 | Nippon Steel Chem Co Ltd | Sealing resin composition |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014131053A (en) * | 2014-01-22 | 2014-07-10 | Nitto Denko Corp | Dicing tape integrated semiconductor rear face film, and method of manufacturing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3259958B2 (en) | 2002-02-25 |
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