JPH02304651A - Data processor - Google Patents

Abstract

PURPOSE:To eliminate a storage system designation for storing in a high speed storage executed from a host device, and also, to store actually data whose use frequency is high in the high speed storage, and moreover, to improve the processing performance by providing a low speed storage address storage means, etc. CONSTITUTION:In the case a read-out/write instruction of low speed storage data is outputted from a host device, the data read-out/write frequency requested from the host device is stored at every address in a low speed storage address storage means 200 by keeping pace with a data processing operation executed by a high speed storage address comparing means 400, etc. Subsequently, by a low speed storage address comparing means 300, the data read-out/write frequency is compared at every address, and only a signal line 3N1 corresponding to the address in which magnitude of the read-out/write frequency becomes an N + 1-th address becomes effective. Next, a data processing means 700 executes a data processing through an N-th data high speed storage means 6N0, and in a first - an N-th high speed storage means 600 - 6N0, the storage contents of first and N-th magnitude of the read-out/write frequency of the data are always stored, the data storage system designation from the host device becomes unnecessary, and the processing performance can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a data processing device, and particularly to a data caching type data processing device.

[Conventional technology]

Conventionally, this type of data processing device specifies the data storage method to be stored in high-speed storage from the host device.
A part of the data in the low-speed memory is stored in the high-speed memory, and when there is a read/write request from the host device, the address of the subsequent write request is compared with the address of the data stored in the high-speed memory,
If it is the desired data, reading and writing operations to the low-speed storage are not performed, but reading and writing operations to the high-speed storage are performed to improve processing performance.

[Problem to be solved by the invention]

Therefore, in the past, it was necessary to specify the storage method for data to be stored in high-speed memory from the host device, and if the specified method did not match the actual frequency of use, performance could not be sufficiently improved. .

The purpose of the present invention is to solve the above-mentioned drawbacks by using statistical information of data read/write addresses in low-speed storage, eliminate the need to specify a storage method for storing data in high-speed storage from a host device, and store data that is frequently used in practice. The object of the present invention is to provide a device that stores information in a high-speed memory and has higher processing performance than conventional devices.

[Means to solve the problem]

The data processing device of the present invention includes a low-speed memory address register for storing data read/write addresses in low-speed memory, a low-speed memory address storage means for storing data read/write counts for each output address of the low-speed memory address register, and low-speed memory. A low-speed storage address comparison means for comparing the number of data read/writes in the address storage means for each address; a data high-speed storage means for storing a part of the data already stored in the low-speed storage; Comparison of high-speed memory address register for storing successive write addresses, high-speed memory address comparison means for comparing data read/write addresses of high-speed memory address register and low-speed memory address register, and high-speed memory address comparison means and low-speed memory address comparison means It is configured to include data processing means for determining a data processing method based on the results.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings.

In FIG. 1 showing an embodiment of the present invention, the data processing device of the present invention includes a low-speed memory address register 100 that stores data read/write addresses in low-speed memory, and a data read/write function for each output address 101 of the low-speed memory address register 100. Low-speed memory address storage means 20 for storing the number of writes
0. Low-speed memory address comparison means 300 that compares the number of data read and write times of the low-speed memory address storage means 200 for each address; first data that stores data at a different address of data already stored in the low-speed memory in each high-speed memory; High speed storage means 600, second data high speed storage means 610.・・・
Nth data high-speed storage means 6NO1 Corresponding to each data high-speed storage means, a first high-speed storage address register 500, a second high-speed storage address register 510 . . . . Nth high-speed memory address register 5NO, output address 501 of the first high-speed memory address register 500, output address 511 of the second high-speed memory address register 510. . . . High-speed memory address comparison means 400 that compares the data read/write addresses of the output address 5N1 of the N-th high-speed memory address register 5NO and the output address 101 of the low-speed memory address register 100, and the data high-speed memory means of the high-speed memory address comparison means 400 Comparison result output 401, 411.・・・
- 4N1, comparison result output 301, 311 for each data high speed storage means of the low speed storage address comparison means 300. ...
3N1, data line 701 of low speed storage (not shown)
, a data line 711 of a host device (not shown), and a data processing means 700 that connects data lines 601, 611, . . . 6N1 of each high-speed data storage means.

In this configuration, when a command to write successive data to the low-speed storage is issued from the host device, the read/write address of the data is first stored in the low-speed storage address register 100, and the output 101 of the low-speed address register and the first to Nth data high speed storage means 600, 601. . . . 1st to Nth high-speed address registers 500, 510 storing respective read/write addresses of data stored in 6NOs, . . . ... 5N1 is performed by the high-speed storage address comparison means 400, and only the signal line 4N1 corresponding to the matched address is enabled, and the data processing means 700 is notified. In the data processing means 700,
If a high-speed memory with a matching address exists, the data line 711 of the host device is connected to the data line 6N1 of the high-speed storage with a matching address, and data is exchanged between the host device and the high-speed storage 6Nl. If the addresses do not match, the data line 711 of the host device and the data line 7 of the low-speed memory
01 to exchange data between the host device and low-speed storage.

In parallel with the above operation, the number of data read/writes requested by the host device is stored in the low-speed memory address storage means 200 for each address, and the low-speed memory address comparison means 300 stores the number of data reads and writes requested by the host device.
The number of data read/writes is compared for each address, and only the signal line 3N1 corresponding to the address whose number of reads/writes is the N+1st is enabled. Data processing means 70
0, the comparison result signal 3N1 of the low-speed storage address comparison means
When becomes valid, the data line 701 of the low-speed memory is connected to the data line 6N1 of the N-th data high-speed storage means 6NO corresponding to the comparison result signal 3N1, and the After writing back the data in the data high-speed storage means 6NO to the low-speed storage, when connecting the data line 711 of the host device and the data line 701 of the low-speed storage to exchange data between the host device and the low-speed storage, At the same time, the Nth data high speed storage address register 5NO is updated via the Nth data high speed storage means 6NO. As a result of the above, the first to Nth high-speed memories 600 to 6
The storage contents of the first to Nth data read/write counts are always stored in NO.

〔Effect of the invention〕

As explained above, the present invention is configured to store statistical information of data read/write addresses of low-speed storage, and to store the data in the storage means of the processing device in the order of the magnitude of the value of the statistical information. This has the effect of eliminating the need to specify a data storage method from a host device and further improving processing performance.

Brief description of the drawing FIG. 1 is a block diagram of one embodiment of the present invention.

In FIG. 1, 100 is a low-speed storage address register;
101 is a low-speed storage address register output, 200 is a low-speed storage address storage means, 201 is a low-speed storage address storage means output, 300 is a low-speed storage address comparison means, 301
, 311. ...3N1 are the 1st. Second. ... No. N
A low-speed storage address comparison means corresponding to data high-speed storage results output; 400 is a high-speed storage address comparison means; 401;
411, . . . 4N1 are the first . Second. . . . High-speed storage address comparison means result output corresponding to Nth data high-speed storage, 500, 510. ... 5 NOs are the 1st. Second
, . . . Nth high-speed storage address register, 501°51
1,...5N1 are the 1st . Second. . . . Nth high-speed storage address register output, 600, 610. ...6N
O is the first. Second. ... Nth data high-speed storage means,
601,611. ...6 NOs are the 1st. Second,...
・Nth high-speed storage means output, 700 is data processing means, 7
01 is a low-speed storage data line, and 702 is a data line of the host device.

Claims (1)

[Claims] A low-speed memory address register for storing data read/write addresses of low-speed memory, low-speed memory address storage means for storing the number of data read/writes for each output address of the low-speed memory address register, and data reading of the low-speed memory address storage means. Low-speed storage address comparison means for comparing the number of writes for each address, one of the data already stored in the low-speed storage
a data high-speed storage means for storing the data read/write address of the data stored in the data high-speed storage means; a high-speed storage address register for storing the read/write address of the data stored in the data high-speed storage means; a data read/write address of the high-speed storage address register and the low-speed storage address register; A data processing device comprising: high-speed storage address comparison means for comparing; and data processing means for determining a data processing method based on the comparison results of the high-speed storage address comparison means and the low-speed storage address comparison means.