JPH02303034A - Manufacture of multilayer wiring structure - Google Patents
Manufacture of multilayer wiring structureInfo
- Publication number
- JPH02303034A JPH02303034A JP12391189A JP12391189A JPH02303034A JP H02303034 A JPH02303034 A JP H02303034A JP 12391189 A JP12391189 A JP 12391189A JP 12391189 A JP12391189 A JP 12391189A JP H02303034 A JPH02303034 A JP H02303034A
- Authority
- JP
- Japan
- Prior art keywords
- film
- thin film
- silicon thin
- halation
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 239000010408 film Substances 0.000 claims abstract description 38
- 239000010410 layer Substances 0.000 claims abstract description 34
- 239000010409 thin film Substances 0.000 claims abstract description 31
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 29
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 29
- 239000010703 silicon Substances 0.000 claims abstract description 29
- 239000011229 interlayer Substances 0.000 claims abstract description 7
- 238000000059 patterning Methods 0.000 claims abstract description 7
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 6
- 239000007772 electrode material Substances 0.000 claims abstract 5
- 238000009413 insulation Methods 0.000 claims abstract 2
- 238000000034 method Methods 0.000 claims description 14
- 238000000137 annealing Methods 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 230000002265 prevention Effects 0.000 abstract description 7
- 239000000758 substrate Substances 0.000 abstract description 7
- 230000001590 oxidative effect Effects 0.000 abstract description 4
- 238000002955 isolation Methods 0.000 abstract description 2
- 230000003449 preventive effect Effects 0.000 abstract 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 101150081243 STA1 gene Proteins 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 239000005368 silicate glass Substances 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000009835 boiling Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は、アルミニウム（Ａｅ）合金配線を有する半導
体集積回路に適用して最適な多層配線構造の製造方法に
関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a method for manufacturing a multilayer wiring structure that is optimally applied to a semiconductor integrated circuit having aluminum (Ae) alloy wiring.
（ロ）従来の技術
近年、ＬＳＩにおいては、配線幅の微細化や配線の多層
化が進み、これに伴い配線の信頼性の向上が従来以上に
重要になっている。この配線の信頼性を決定する要因と
しては、エレクトロマイグレーション、いわゆるヒロッ
ク（ｈｉｌｌｏｃｋ ）の成長による積層配線間のショ
ート等が考えられる。(B) Prior Art In recent years, in LSIs, the wiring width has become smaller and the wiring has become more multilayered, and as a result, improving the reliability of the wiring has become more important than ever. Possible factors that determine the reliability of this wiring include short circuits between laminated wirings due to electromigration, the growth of so-called hillocks, and the like.
ヒロックはアルミニウム（Ａｆ！、）Ｎ１堆積後の長時
間熱処理によって成長するので、これらの問題に対処す
るために、近時、ＡＩ！、合金膜上に還移金属等の硬質
膜を設けた構造の積層膜から成る配線が注目されている
。（例えば、特開昭８３−１４３８４２号）
一方、Ａｆｆｉ層のホトレジスト工程においては、Ａｆ
！層表面が光を反射（ハレーション）することによる、
レジスト膜のパターン精度の劣化という問題がある。こ
の問題に対しては、反射光を吸収する物質をレジストに
含ませることで解決していた。Since hillocks grow due to long-term heat treatment after aluminum (Af!,)N1 deposition, recently AI! , wiring made of a laminated film with a structure in which a hard film of reduced metal or the like is provided on an alloy film is attracting attention. (For example, Japanese Patent Laid-Open No. 83-143842) On the other hand, in the photoresist process of the Affi layer,
! Due to the layer surface reflecting light (halation),
There is a problem of deterioration in pattern accuracy of the resist film. This problem has been solved by including a substance in the resist that absorbs reflected light.
（ハ）発明が解決しようとする課題
しかしながら、配線幅の微細化を押し進めるには、上記
したハレーション対策では対処しきれないことが本願発
明者によって明らかになった。(c) Problems to be Solved by the Invention However, the inventors of the present invention have found that the above-mentioned halation countermeasures are not sufficient to advance the miniaturization of wiring width.
また、上記ヒロック対策とハレーション対策が別個に行
われるので、プロセスが煩雑になる欠点を有していた。Furthermore, since the hillock countermeasures and the halation countermeasures are performed separately, there is a drawback that the process becomes complicated.
〈二）課題を解決するための手段
本発明は上記従来の課題に鑑み成されたもので、先ずＡ
２層表面にシリコン薄膜（８）を形成してハレーション
防止膜とし、続いてシリコン薄膜を酸化してヒロック防
止膜とすることにより、ヒロック対策とハレーション対
策との両方を同時的に行える多層配線構造のプロセスを
提供するものである。(2) Means for solving the problems The present invention has been made in view of the above-mentioned conventional problems.
By forming a silicon thin film (8) on the surface of the two layers to form an anti-halation film, and then oxidizing the silicon thin film to form an anti-hillock film, this multilayer wiring structure can simultaneously provide both hillock and halation countermeasures. It provides a process for
（＊）作用
本発明によれば、Ａり層表面に非透明のシリコン薄膜（
８）を形成するので１、ホトレジスト工程においてＡ！
層表面での露光光の反射を防止できる。また、ＲＴＡ処
理を行なうので、シリコン薄膜（８）を酸化してヒロッ
ク成長防止膜に転用できる他１．１１層側面の表面を改
質できる。(*) Effect According to the present invention, a non-transparent silicon thin film (
8), so 1, A! in the photoresist process.
Reflection of exposure light on the layer surface can be prevented. Further, since RTA treatment is performed, the silicon thin film (8) can be oxidized and used as a hillock growth prevention film, and the surface of the side surface of the 1.11 layer can be modified.
（へ）実施例
以下に本発明の一実施例を図面を参照して詳細に説明す
る。(F) Example An example of the present invention will be described below in detail with reference to the drawings.
先ず第１図Ａに示すように、本実施例によるＭｏＳ型Ｌ
ＳＩにおいては、例えばＰ型シリコン基板（１）の表面
を選択酸化して素子分離用のフィールド酸化膜（２）を
形成し、フィールド酸化膜〈２）で囲まれた基板（１）
表面にはポリシリコン（Ｐｏ１ｙ−５ｉｌｉｃｏｎ ）
から成るゲート電極（３）がゲート酸化膜（４）を介し
て形成される。ゲート電極（３）両脇の基板（１）表面
にはソース・ドレイン領域（５）が設けられる。ゲート
電極（３）は例えば減圧ＣＶＤ法によるＰＳＧ（リン・
シリケート・グラス）又はＢＰＳＧ（ボロン・リン・シ
リケート・グラス）等の絶縁膜（６）で覆われている。First, as shown in FIG. 1A, the MoS type L according to this embodiment is
In SI, for example, the surface of a P-type silicon substrate (1) is selectively oxidized to form a field oxide film (2) for element isolation, and the substrate (1) is surrounded by the field oxide film (2).
Polysilicon (Poly-5ilicon) on the surface
A gate electrode (3) consisting of is formed via a gate oxide film (4). Source/drain regions (5) are provided on the surface of the substrate (1) on both sides of the gate electrode (3). The gate electrode (3) is made of, for example, PSG (phosphorus) by low pressure CVD method.
It is covered with an insulating film (6) such as silicate glass (silicate glass) or BPSG (boron phosphorus silicate glass).
この絶縁膜（６）上に、例えばスパッタ法によりシリコ
ン（５ｉ）を数％含むアルミニウム（Ａ ｌ ）を約１
μｍ厚に堆積して１ｓｔＡ１層（７）とし、続いて１
ｓｔＡ １層（７）上に同じくスパッタ法によりシリコ
ン（Ｓｉ）を１００〜３００人程度積層してシリコン薄
膜（８）とする。これらの工程は比較的簡単な工程で済
ませることができる。つまり、１ｓｔＡｆｆｉ層（７）
として使用するアルミ・シリコン（Ａｊ！−５ｉ）形成
用のスパッタ装置は、アルミニウム（Ａ２）とシリコン
（Ｓｉ）との２つのターゲットを有するものであり、先
ず２つのターゲットで１ｓｔＡ１層（７）を堆積し、続
いてシリコン（Ｓｉ）ターゲットだけに切換えてシリコ
ン薄膜（８）を積層することにより、同一装置内の１回
の処理で積層構造にできる。On this insulating film (6), approximately 1% of aluminum (A l ) containing several percent of silicon (5i) is deposited, for example, by sputtering.
1stA1 layer (7) is deposited to a thickness of μm, and then 1stA1 layer (7) is deposited.
About 100 to 300 layers of silicon (Si) are laminated on the stA 1 layer (7) by the same sputtering method to form a silicon thin film (8). These steps can be completed with relatively simple steps. In other words, 1stAffi layer (7)
The sputtering equipment used for forming aluminum silicon (Aj!-5i) has two targets, aluminum (A2) and silicon (Si), and first, the 1st A1 layer (7) is By depositing and subsequently layering a silicon thin film (8) by switching only to a silicon (Si) target, a layered structure can be obtained in one process in the same apparatus.
次に第１図Ｂに示すように、例えばポジ型レジストを基
板（１）上にスピンオン塗布、ベーキングを処し、続い
て下層配線パターンに対応するパターンをホトマスクを
使用して例えばステッパ装置により露光し、現像液で現
像して前記配線パターンに対応したレジスト膜（９）パ
ターンを形成する。上記露光時に、１ｓｔＡ １２層（
７）表面がシリコン薄膜（８）で覆われるので、光干渉
による反射光の打消し合いにより露光光が１ ｓｔＡ
１層（７）表面で反射（ハレーション）することが無く
、従ってホトマスクパターンに対応する高精度のレジス
ト膜（９）パターンを得ることができる。その後、例え
ばプラズマ等の異方性エツチングにより１ｓｔＡＮ層（
７）とシリコン薄膜（８）を同時的にパターニングして
下層配線パターンを形成する。Next, as shown in FIG. 1B, for example, a positive resist is spin-on coated onto the substrate (1) and subjected to baking, and then a pattern corresponding to the lower layer wiring pattern is exposed using a photomask using, for example, a stepper device. , a resist film (9) pattern corresponding to the wiring pattern is formed by developing with a developer. At the time of the above exposure, 1stA 12 layers (
7) Since the surface is covered with a silicon thin film (8), the exposure light is reduced to 1 stA due to the cancellation of reflected light due to optical interference.
There is no reflection (halation) on the surface of the first layer (7), and therefore a highly accurate resist film (9) pattern corresponding to the photomask pattern can be obtained. After that, the 1st AN layer (
7) and the silicon thin film (8) are simultaneously patterned to form a lower wiring pattern.
次に第１図Ｃに示すように、レジスト膜（９）を沸酸系
溶液で除去した後ランプヒートアニール（ＲＴＡ）方式
によって基板（１）表面を短時間熱処理する。雰囲気は
酸化性とし、この処理によってシリコン薄膜（８）のシ
リコン（Ｓｉ）を酸化してシリコン酸化膜（Ｓｉｎ、）
とする、パターニングによって露出した１ ｓｔＡ １
２層（７）の側面もランプヒートアニール処理により酸
化（Ａ ｆｆｉ ＊Ｏｓ＞される。Next, as shown in FIG. 1C, after removing the resist film (9) with a boiling acid solution, the surface of the substrate (1) is heat-treated for a short time using a lamp heat annealing (RTA) method. The atmosphere is oxidizing, and this treatment oxidizes the silicon (Si) of the silicon thin film (8) to form a silicon oxide film (Sin).
1 stA 1 exposed by patterning
The side surfaces of the second layer (7) are also oxidized (Affi *Os>) by the lamp heat annealing process.
次に第１図りに示すように、減圧ＣＶＤ法等の手段によ
り１ ｓｔＡ ｅ Ｂ （７）とシリコン薄膜（８）を
覆うようにＰＳＧ等から成る層間絶縁膜（１０）を形成
する１本工程は数百℃、３０分〜１時間もの長時間熱処
理となる。Next, as shown in the first diagram, one step is performed to form an interlayer insulating film (10) made of PSG or the like so as to cover the 1stA e B (7) and the silicon thin film (8) by means such as low pressure CVD. This involves heat treatment at several hundred degrees Celsius for a long time of 30 minutes to 1 hour.
次に第１図Ｅに示すように、層間接続を行う為のスルー
ホール（１１）を異方性、又は等方性＋異方性の組合せ
エツチングにより形成する。シリコン薄膜（８）はラン
プヒートアニール処理によってシリコン酸化膜（ＳｉＯ
ｘ）と°化しているので、同じくシリコン酸化物から成
る層間絶縁膜（１０）と同一工程で除去する。Next, as shown in FIG. 1E, through holes (11) for making interlayer connections are formed by anisotropic or a combination of isotropic and anisotropic etching. The silicon thin film (8) is made into a silicon oxide film (SiO) by lamp heat annealing treatment.
x), so it is removed in the same process as the interlayer insulating film (10) also made of silicon oxide.
そして第１図Ｆに示すように、再びスパッタ法等により
２ ｎｄＡ Ｉ ＭＡ （１２）を堆積し、これをパタ
ーニングすることにより上層配線とする。Then, as shown in FIG. 1F, 2nd A I MA (12) is deposited again by sputtering or the like and patterned to form an upper layer wiring.
以上に説明した本発明のプロセスによれば、シリコン薄
膜（８）が露光光の反射（ハレーション）を防止するの
で、レジスト膜（９）パターンヲＸＷｔ度に現像でき、
従って１ ｓｔＡ １層（２）の微細化を更に押し進め
ることができる。According to the process of the present invention described above, since the silicon thin film (8) prevents reflection (halation) of exposure light, the resist film (9) pattern can be developed to XWt degrees.
Therefore, the miniaturization of the 1 stA 1 layer (2) can be further promoted.
一方、１ ｓｔＡ １層（７）表面が酸化シリコン薄膜
（８）で覆われるので、層間絶縁膜り１０）形成時のヒ
ロック（ｈｉｌＬｏｃｋ ）の成長を、防止し、従って
層間耐圧の劣化を防止できる。尚、シリコン薄膜（８）
が無い状態で１ ｓｔＡ １層（７）表面にランプヒー
トアニール処理を実施することにより、ある程度ヒロッ
ク成長を抑制できることが本願発明者により確認きれて
いるので、本願によれば１ ｓｔＡ ９層（７）の横方
向へのヒロック成長をも防止できる。On the other hand, since the surface of the 1stA 1 layer (7) is covered with the silicon oxide thin film (8), it is possible to prevent the growth of hillocks during the formation of the interlayer insulating film 10), thereby preventing deterioration of the interlayer breakdown voltage. . In addition, silicon thin film (8)
The inventor of the present application has confirmed that hillock growth can be suppressed to some extent by performing lamp heat annealing treatment on the surface of the 1 stA 1 layer (7) in the absence of the 1 stA 9 layer (7). ) can also prevent hillock growth in the lateral direction.
（ト）発明の詳細
な説明した如く、本発明によれば１ ｓｔＡ １１層（
７）表面のシリコン薄膜（８）が露光光の反射（ハレー
ション）を防止するので、下層配線層の微細化を押し進
められる利点を有する。(G) As described in detail, according to the present invention, 1 stA 11 layers (
7) Since the silicon thin film (8) on the surface prevents reflection (halation) of exposure light, there is an advantage that miniaturization of the lower wiring layer can be promoted.
また、ランプヒートアニール処理により短時間で１ｓｔ
Ａ１層（７）表面を酸化されたシリコン薄膜（８）で覆
うので、ヒロックの成長を防止でき、従って信頼性の高
い多層配線を形成できる利点を有する。In addition, lamp heat annealing allows for 1st operation in a short time.
Since the surface of the A1 layer (7) is covered with the oxidized silicon thin film (8), it is possible to prevent the growth of hillocks, which has the advantage that a highly reliable multilayer wiring can be formed.
さらに、ランプヒートアニール処理によって横方向への
ヒロック成長をも防止できるので、１ｓｔＡｆｉ層（７
）の微細化に寄与できる利点をも有する。Furthermore, since the lamp heat annealing treatment can also prevent hillock growth in the lateral direction, the 1stAfi layer (7
) also has the advantage of contributing to miniaturization.
そしてさらに、シリコン薄膜（８）をハレーション防止
とヒロック成長防止との両方に利用できるので、工程の
簡略化が図れる利点をも有する。Furthermore, since the silicon thin film (8) can be used for both prevention of halation and prevention of hillock growth, there is an advantage that the process can be simplified.
第１図Ａ−Ｆは本発明を説明する為の断面図である。 FIGS. 1A to 1F are cross-sectional views for explaining the present invention.
Claims (2)
を形成し、続いてその表面にシリコン薄膜を堆積する工
程、 前記シリコン薄膜上にホトレジスト膜を塗布しこれをパ
ターニングすると共に、前記ホトレジストパターンをマ
スクとして前記電極材料層とシリコン薄膜をパターニン
グする工程、 前記半導体装置の主面を短時間熱処理し、前記電極材料
層上のシリコン薄膜を酸化する工程、前記シリコン薄膜
の上に層間絶縁膜を堆積し、続いて上層配線となる電極
材料層を形成し、これをパターニングして上層配線とす
る工程とを具備することを特徴とする多層配線構造の製
造方法。(1) A step of forming an electrode material layer to serve as a lower wiring on the main surface of a semiconductor device, and then depositing a silicon thin film on the surface thereof; applying a photoresist film on the silicon thin film and patterning it; a step of patterning the electrode material layer and the silicon thin film using a photoresist pattern as a mask; a step of briefly heat-treating the main surface of the semiconductor device to oxidize the silicon thin film on the electrode material layer; and interlayer insulation on the silicon thin film. 1. A method for manufacturing a multilayer wiring structure, comprising the steps of: depositing a film, subsequently forming an electrode material layer to become an upper layer wiring, and patterning this to form an upper layer wiring.
ことを特徴とする請求項第１項に記載の多層配線構造の
製造方法。(2) The method for manufacturing a multilayer wiring structure according to claim 1, wherein the short-time heat treatment is lamp heat annealing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12391189A JPH02303034A (en) | 1989-05-17 | 1989-05-17 | Manufacture of multilayer wiring structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12391189A JPH02303034A (en) | 1989-05-17 | 1989-05-17 | Manufacture of multilayer wiring structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02303034A true JPH02303034A (en) | 1990-12-17 |
Family
ID=14872397
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12391189A Pending JPH02303034A (en) | 1989-05-17 | 1989-05-17 | Manufacture of multilayer wiring structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02303034A (en) |
-
1989
- 1989-05-17 JP JP12391189A patent/JPH02303034A/en active Pending
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