JPH02302052A - Tape carrier - Google Patents

Tape carrier

Info

Publication number
JPH02302052A
JPH02302052A JP12308489A JP12308489A JPH02302052A JP H02302052 A JPH02302052 A JP H02302052A JP 12308489 A JP12308489 A JP 12308489A JP 12308489 A JP12308489 A JP 12308489A JP H02302052 A JPH02302052 A JP H02302052A
Authority
JP
Japan
Prior art keywords
sides
inner leads
electrodes
semiconductor element
tape
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12308489A
Other languages
Japanese (ja)
Inventor
Yuko Tsujimura
辻村 優子
Kenichiro Tsubone
坪根 健一郎
Hiroyuki Takabayashi
高林 博幸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP12308489A priority Critical patent/JPH02302052A/en
Publication of JPH02302052A publication Critical patent/JPH02302052A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To reduce the number of kinds of tape carriers, to improve an economical efficiency and to enhance a productivity by a method wherein an inner lead is formed to be longer in advance and an excess length is cut so as to be connected to different kinds of semiconductor elements. CONSTITUTION:In tape carriers 1, 11, inner leads 1b, composed of conductors, which surround, from peripheral edges of four sides, a square mounting hole 1a-1 which has been made in a tape-shaped film 1a composed of a polyimide resin or the like and into which a semiconductor element is inserted in such a way that the inner leads correspond to electrodes formed at the four sides on the rear of the square semiconductor element protrude into the hole. Out of the inner leads 1b at the four sides, inner leads 1b-x at two opposite sides in an X-direction are extended, from both sides, between inner leads 1b-y at the other two sides in a Y-direction and are formed to be longer in advance so as to cut excess lengths to prescribed mounting lengths. The inner leads 1b-y at the other two sides are formed so as to be overlapped exactly with the electrodes (figure omitted) of the semiconductor element.

Description

【発明の詳細な説明】 〔概要〕 半導体素子を絶縁基板などに実装接続するテープキャリ
アに係り、さらに詳しくは、インナーリードの形状に関
し、 1種類で数種類の半導体素子を接続し種類をできるだけ
少なくすることを目的とし、 テープ状フィルムに開けた半導体素子を挿入する四角形
の実装孔の四辺周縁から孔内に突出し、前記半導体素子
の電極に重ね合わせて接続するインナーリードを備える
テープキャリアにおいて。
[Detailed Description of the Invention] [Summary] This invention relates to a tape carrier for mounting and connecting semiconductor elements to an insulating substrate, etc., and more specifically, regarding the shape of an inner lead, connecting several types of semiconductor elements with one type and minimizing the number of types. A tape carrier comprising inner leads that protrude from the four sides of a rectangular mounting hole in a tape-like film into which a semiconductor element is inserted, and are connected to the electrodes of the semiconductor element by overlapping them.

前記インナーリードの中、対向する二辺のインナーリー
ドを他の二辺のインナーリードの間に両側から突出延ば
し実装所定長さに余長を切除するように予め、長くして
構成する。
Among the inner leads, the inner leads on two opposing sides are lengthened in advance so as to protrude from both sides between the inner leads on the other two sides, and the excess length is cut off to a predetermined length for mounting.

〔産業上の利用分野) 本発明は半導体素子を絶縁基板などに実装接続するテー
プキャリアに係り、さらに詳しくは、インナーリードの
形状に関する。
[Industrial Application Field] The present invention relates to a tape carrier for mounting and connecting a semiconductor element to an insulating substrate or the like, and more specifically relates to the shape of an inner lead.

半導体素子(チップ)の信号接続及び実装に利用される
テープキャリアは、半導体素子の電極に対応するインナ
ーリードをテープ状のフィルムに繰り返し形成し、イン
ナーリードボンディング後、アウターリードを切り取り
それを匁色本濠基牟反などの配線電極に実装接続する。
Tape carriers used for signal connection and mounting of semiconductor devices (chips) are made by repeatedly forming inner leads corresponding to the electrodes of the semiconductor device on a tape-like film, and after bonding the inner leads, cut out the outer leads and roll them into a momme color. Mount and connect to wiring electrodes such as the main moat base.

インナーリードは通常、半導体素子のサイズや電極の配
置形状に合わせて形成されるため、非常に多種類のテー
プキャリアを製作している。テープキャリアの種類をで
きるだけ少なくするため、1種類のテープキャリアで数
種類の半導体素子を接続できることが要望されている。
Inner leads are usually formed to match the size of the semiconductor element and the arrangement shape of the electrodes, so a wide variety of tape carriers are manufactured. In order to reduce the number of types of tape carriers as much as possible, it is desired to be able to connect several types of semiconductor elements with one type of tape carrier.

(従来の技術〕 従来のテープキャリア10は第7図の要部平面図に示す
ように、テープ状のポリイミド樹脂などのフィルム10
a上に導体リードをパターン形成し、一方の端部を半導
体素子の電極(図示路)に接合するインナーリード10
bとし、他方の端部を絶縁基板の配線電極(図示路)に
接合するアウターリード10c としている。
(Prior Art) As shown in the plan view of the main part of FIG. 7, a conventional tape carrier 10 is a tape-shaped film 10 made of polyimide resin or the like.
Inner lead 10 on which a conductor lead is patterned on a and one end is connected to an electrode (as shown in the figure) of a semiconductor element.
b, and the other end is an outer lead 10c which is connected to a wiring electrode (path shown in the figure) of an insulating substrate.

フィルム10aにはインナーリード10bを半導体素子
の電極と熱圧着可能に露出するために四角形の実装孔1
0a−1が開けられ、インナーリード10bはその実装
孔10a−1の四辺周縁から孔内に突出しその先端は半
導体素子の電極とちょうど重なる形状に形成されている
A rectangular mounting hole 1 is formed in the film 10a to expose the inner lead 10b so that it can be thermocompression bonded to the electrode of the semiconductor element.
0a-1 is opened, and the inner lead 10b protrudes into the hole from the four peripheries of the mounting hole 10a-1, and its tip is formed in a shape that exactly overlaps with the electrode of the semiconductor element.

また、同様にアウターリード10cも絶縁基板の配線電
極と熱圧着可能に露出するために四角枠形孔10a−2
を開けている。
Similarly, the outer lead 10c is also exposed through the square frame hole 10a-2 so that it can be bonded by thermocompression to the wiring electrode of the insulating substrate.
is open.

このテープキャリア10に、例えば、第8図に示す四角
形の半導体素子30の裏面四辺に備える電極30aを接
続する場合、第9図の平面図に示すように、それぞれの
インナーリード10bを半導体素子30 (斜線で示す
)の電極30 aに重ね合わせて半田などの共晶合金接
合剤(図示路)で接合する。インナーリードボンディン
グした後はアウターリード10cを四角枠形孔10a−
2の周縁から突出するように所定位置A線で切り取り、
別工程でその先端を絶縁基板の配線電極に実装接続して
いる。
When connecting the electrodes 30a provided on the four sides of the back surface of the rectangular semiconductor element 30 shown in FIG. 8 to this tape carrier 10, for example, as shown in the plan view of FIG. It is overlapped with the electrode 30a (indicated by diagonal lines) and bonded with a eutectic alloy bonding agent such as solder (as shown). After inner lead bonding, the outer lead 10c is connected to the square frame hole 10a-
Cut it at a predetermined position along line A so that it protrudes from the periphery of 2,
The tip is mounted and connected to the wiring electrode of the insulating substrate in a separate process.

〔発明が解決しようとする課題] しかしながら、このような上記構成のテープキャリアは
半導体素子と1対1に対応して製作されることから、非
常に種類が多く不経済で生産性が悪いといった問題があ
った。
[Problems to be Solved by the Invention] However, since the tape carrier having the above-mentioned structure is manufactured in one-to-one correspondence with the semiconductor elements, there are problems such as a large number of types, which are uneconomical and poor productivity. was there.

上記問題点に鑑み、本発明は1種類で数種類の半導体素
子を接続し種類をできるだけ少なくすることのできるテ
ープキャリアを提供することを目的とする。
In view of the above problems, an object of the present invention is to provide a tape carrier that can connect several types of semiconductor elements with one type and minimize the number of types.

〔課題を解決するための手段〕[Means to solve the problem]

上記目的を達成するために、本発明のテープキャリアに
おいては、テープ状フィルムに開けた半導体素子を挿入
する四角形の実装孔の四辺周縁から孔内に突出し、前記
半導体素子の電極に重ね合わせて接続するインナーリー
ドを備えるテープキャリアにおいて、前記インナーリー
ドの中、対向する二辺のインナーリードを他の二辺のイ
ンナーリードの間に両側から突出延ばし実装所定長さに
余長を切除できるように予め、長くして構成する。
In order to achieve the above object, the tape carrier of the present invention protrudes into the hole from the four sides of a rectangular mounting hole cut in a tape-like film into which a semiconductor element is inserted, and is overlapped and connected to the electrode of the semiconductor element. In a tape carrier equipped with inner leads, the inner leads on two opposing sides are extended from both sides between the inner leads on the other two sides so that the excess length can be cut off to a predetermined length for mounting. , lengthen and compose.

(作用) 対向する二辺のインナーリードを他の二辺のインナーリ
ードの間に両側から突出延ばし実装所定長さに余長を切
除するように予め、長くすることにより、接続する半導
体素子の電極に合わせてインナーリードを切断し異なる
種類の半導体素子に適用することができる。
(Function) By lengthening the inner leads on two opposing sides in advance so that they protrude from both sides between the inner leads on the other two sides and cutting off the excess length to a predetermined length for mounting, the electrodes of the semiconductor element to be connected are The inner leads can be cut to suit different types of semiconductor devices.

〔実施例〕〔Example〕

以下図面に示した実施例に基づいて本発明の要旨を詳細
に説明する。
The gist of the present invention will be explained in detail below based on embodiments shown in the drawings.

第1の実施例のテープキャリア1、即ち11は第1図の
要部平面図に示すように、ポリイミド樹脂などからなる
テープ状のフィルム1aに開けた半導体素子を挿入する
四角形の実装孔1a−1の四辺周縁から図示撓い四角形
の半導体素子の裏面四辺に形成された電極に対応する導
体からなるインナーリード1bを孔内に突出する。そし
て、四辺のインナーリード1bの中、X方向の対向する
二辺のインナーリード1b−x (図は2電極/X辺を
示す)をY方向の他の二辺のインナーリード1b−y 
(図は8電極/Y辺を示す)の間に両側から突出延ばし
実装所定長さに余長を切除するように予め、長く形成す
る。他の二辺のインナーリード1b−y(8電1/Y辺
)の方は半導体素子の電極(図示時)とちょうど重ね合
わさるようにする。
As shown in the main part plan view of FIG. 1, the tape carrier 1 of the first embodiment, that is, the tape carrier 11 has a rectangular mounting hole 1a, into which a semiconductor element is inserted, which is made in a tape-shaped film 1a made of polyimide resin or the like. Inner leads 1b made of conductors corresponding to the electrodes formed on the four sides of the back surface of the semiconductor element having a rectangular flexible shape as shown in the figure are protruded into the hole from the periphery of the four sides of the semiconductor element. Among the inner leads 1b on the four sides, the inner leads 1b-x on two opposing sides in the X direction (the figure shows two electrodes/X side) are connected to the inner leads 1b-y on the other two sides in the Y direction.
(The figure shows 8 electrodes/Y side) It is formed long in advance so that it protrudes from both sides and the excess length is cut off to a predetermined length for mounting. The other two inner leads 1b-y (8-electron 1/Y sides) are made to overlap exactly with the electrodes of the semiconductor element (as shown).

このテープキャリア11は、インナーリード1b−x。This tape carrier 11 has inner leads 1b-x.

1b−yの配列ピッチと同じ配列ピッチの電極で2×(
2電極/X辺+8電極/Y辺)の20電極まで対応する
ことができる。
2×(
It can accommodate up to 20 electrodes (2 electrodes/X side + 8 electrodes/Y side).

このテープキャリア11に、第2図の平面図に示すよう
に例えば、2×(2電極/ X i22 + 4電極/
Y辺)の12電極2aを備える半導体素子2 (斜線で
示す)を接続する場合、半導体素子2を実装孔1a−1
に置き、それぞれのインナーリード1b−x、 1b−
yを電極2aに重ね合わせて半田などの共晶合金接合剤
(図示時)で接合する。対応する電極がなく接合されな
いインナーリードは遊びとなるため、接合前に予め、切
除しておいてもよい。
As shown in the plan view of FIG. 2, this tape carrier 11 has, for example, 2×(2 electrodes/X i22 + 4 electrodes/
When connecting a semiconductor element 2 (shown with diagonal lines) having 12 electrodes 2a (Y side), the semiconductor element 2 is connected to the mounting hole 1a-1.
and each inner lead 1b-x, 1b-
y is superimposed on the electrode 2a and bonded with a eutectic alloy bonding agent such as solder (as shown). Since the inner leads that do not have corresponding electrodes and are not joined become loose, they may be cut off before joining.

いま、第3図の平面図に示すように電極の配列ピッチは
同じで電極数の異なる、例えば2×(2電極/X辺+6
電極/ Y ’y12 )の16を極を備える半導体素
子2、即ち2−1(斜線で示す)を接読する場合は、電
極数に合わせて接合前に予め、延ばしたインナーリード
1b−xの先端部をパンチング加工により切除した後、
接合する。接合されないインナーリードは遊びとなるた
め、同様に接合前に予め、切除しておいてもよい。
Now, as shown in the plan view of Fig. 3, the arrangement pitch of the electrodes is the same but the number of electrodes is different, for example, 2 × (2 electrodes/X side + 6
When reading a semiconductor element 2 having 16 electrodes (Y'y12), that is, 2-1 (indicated by diagonal lines), the inner leads 1b-x, which are stretched out in advance before bonding according to the number of electrodes, are to be read directly. After cutting off the tip by punching,
Join. Since the inner leads that are not joined become loose, they may be cut out in advance before joining.

第4図は第2の実施例のテープキャリアの平面図を示す
。このテープキャリア1、即ち12は、四辺のインナー
リード12bの中、X方向の対向する二辺のインナーリ
ード12b−x(図は4電極/X辺を示す)をY方向の
他の二辺のインナーリード12b−y(図は8電極/Y
辺を示す)の間に両側から突出延ばしたものである。
FIG. 4 shows a plan view of the tape carrier of the second embodiment. This tape carrier 1, that is, 12, has inner leads 12b-x (the figure shows 4 electrodes/X side) on two opposing sides in the X direction among the inner leads 12b on four sides, and inner leads 12b-x on the other two sides in the Y direction. Inner lead 12b-y (8 electrodes/Y
It extends protruding from both sides between the sides (indicated by the sides).

このテープキャリア12は、インナーリード12bの配
列ピッチと同じ配列ピンチの電極で2×(4電極/X辺
+8電極/Y辺)の24電極まで対応することができる
This tape carrier 12 can accommodate up to 24 electrodes (2×(4 electrodes/X side+8 electrodes/Y side)) with the same arrangement pitch as the inner lead 12b.

第5図の平面図は、2×(4電極/X辺+2電極/Y辺
)の12電極を備える半導体素子2、即ち2−2(斜線
で示す)を接続した場合を示し、第6図の平面図は、2
×(4電極/X辺+6電極/Y辺)の20電極を備える
半導体素子2、即ち2−3(斜線で示す)を接続した場
合を示す。
The plan view of FIG. 5 shows the case where a semiconductor element 2 having 12 electrodes of 2×(4 electrodes/X side + 2 electrodes/Y side), that is, 2-2 (shown with diagonal lines) is connected. The plan view of 2
A case is shown in which a semiconductor element 2 having 20 electrodes (4 electrodes/X side + 6 electrodes/Y side), ie, 2-3 (indicated by diagonal lines) is connected.

このように、対向する二辺のインナーリードを他の二辺
のインナーリードの間に両側から突出延ばし実装所定長
さに余長を切除するように予め、長くすることにより、
電極数の異なる半導体素子で電極の配列ピッチが同じで
あれば、実装する際に電極に合わせてインナーリードを
切除し異なる種類の半導体素子に適用することができる
In this way, by lengthening the inner leads on two opposing sides in advance so that they protrude from both sides between the inner leads on the other two sides, and cutting off the excess length to a predetermined length for mounting,
If the arrangement pitch of the electrodes is the same for semiconductor elements having different numbers of electrodes, the inner leads can be cut out to match the electrodes during mounting, and the invention can be applied to different types of semiconductor elements.

〔発明の効果〕〔Effect of the invention〕

以上、詳述したように本発明によれば、インナーリード
を予め、長(しておくことにより、余長を切断して異な
る種類の半導体素子を接続することができ、テープキャ
リアの種類を少なくして経済性を改善し生産性を向上す
ることができるといった産業上極めて有用な効果を発揮
する。
As described in detail above, according to the present invention, by making the inner lead long in advance, it is possible to cut the extra length and connect different types of semiconductor elements, thereby reducing the number of types of tape carriers. It has extremely useful effects in industry, such as improving economic efficiency and productivity.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明による第1の実施例の要部平面図、 第2図は第1図に接続した半導体素子の一実装例を示す
平面図、 第3図は第1図に接続した他の半導体素子の実装例を示
す平面図、 第4図は本発明による第2の実施例の要部平面図、 第5図は第4図に接続した半導体素子の一実装例を示す
平面図、 第6図は第4図に接続した他の半導体素子の実装例を示
す平面図、 第7図は従来技術によるテープキャリアの要部平面図、 第8図は裏面から見た半導体素子の斜視図、第9図は第
7図に接続した半導体素子の実装状態を示す平面図であ
る。 図において、 1はテープキャリア、 1aはフィルム、 13−1は実装孔、 1b、 1b−x、 1b−yはインナーリード、2は
半導体素子、 2aは電極を示す。 琳  4  凶 第7図に接続した半導体素子の実装伏壱を示す平面図第
9図
FIG. 1 is a plan view of essential parts of a first embodiment of the present invention, FIG. 2 is a plan view showing an example of mounting a semiconductor element connected to FIG. 1, and FIG. 3 is a plan view of a semiconductor device connected to FIG. 1. 4 is a plan view of a main part of a second embodiment of the present invention; FIG. 5 is a plan view showing an example of mounting a semiconductor element connected to FIG. 4; Fig. 6 is a plan view showing an example of mounting another semiconductor element connected to Fig. 4, Fig. 7 is a plan view of main parts of a tape carrier according to the prior art, and Fig. 8 is a perspective view of the semiconductor element seen from the back side. , FIG. 9 is a plan view showing the mounting state of the semiconductor elements connected to FIG. 7. In the figure, 1 is a tape carrier, 1a is a film, 13-1 is a mounting hole, 1b, 1b-x, and 1b-y are inner leads, 2 is a semiconductor element, and 2a is an electrode. Figure 9 is a plan view showing the mounting layout of the semiconductor elements connected to Figure 7.

Claims (1)

【特許請求の範囲】 テープ状フィルム(1a)に開けた半導体素子(2)を
挿入する四角形の実装孔(1a−1)の四辺周縁から孔
内に突出し、前記半導体素子(2)の電極(2a)に重
ね合わせて接続するインナーリード(1b)を備えるテ
ープキャリアにおいて、 前記インナーリード(1b)の中、対向する二辺のイン
ナーリード(1b−x)を他の二辺のインナーリード(
1b−y)の間に両側から突出延ばし実装所定長さに余
長を切除するように予め、長くしたことを特徴とするテ
ープキャリア。
[Scope of Claims] A rectangular mounting hole (1a-1) made in a tape-like film (1a) into which a semiconductor element (2) is inserted, protrudes into the hole from the four side peripheries, and an electrode ( 2a), in which inner leads (1b-x) on two opposing sides are connected to inner leads (1b-x) on the other two sides of the inner leads (1b).
A tape carrier characterized in that the tape carrier is lengthened in advance so as to protrude from both sides between 1b and y) and cut off the extra length to a predetermined length for mounting.
JP12308489A 1989-05-16 1989-05-16 Tape carrier Pending JPH02302052A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12308489A JPH02302052A (en) 1989-05-16 1989-05-16 Tape carrier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12308489A JPH02302052A (en) 1989-05-16 1989-05-16 Tape carrier

Publications (1)

Publication Number Publication Date
JPH02302052A true JPH02302052A (en) 1990-12-14

Family

ID=14851810

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12308489A Pending JPH02302052A (en) 1989-05-16 1989-05-16 Tape carrier

Country Status (1)

Country Link
JP (1) JPH02302052A (en)

Similar Documents

Publication Publication Date Title
JP2002124544A (en) Tape carrier for cof and semiconductor device in cof structure manufactured by the tape carrier
JP3569025B2 (en) Semiconductor device and electronic device using the same
JPH04273451A (en) Semiconductor device
US5559305A (en) Semiconductor package having adjacently arranged semiconductor chips
JPH02302052A (en) Tape carrier
KR100196119B1 (en) Semiconductor device and manufacturing method thereof and electron device
JPH01132142A (en) Package structure of semiconductor device
JP3192238B2 (en) Method of assembling semiconductor device
JP3229068B2 (en) TAB film and semiconductor device using the TAB film
JPH0451056B2 (en)
JPS6366959A (en) Multiple lead frame
JPH07201928A (en) Film carrier and semiconductor device
JP2836208B2 (en) Film carrier tape
JP2806816B2 (en) Bonding apparatus and bonding method using the same
JP2556204B2 (en) Film carrier semiconductor device mounting method
JPS62155546A (en) Memory module
JPS6343897B2 (en)
JP2504969Y2 (en) Semiconductor mounting structure
CN113130472A (en) Fan-out type packaging structure and packaging method
JP3158480B2 (en) Tape carrier mounting method and liquid crystal display device manufacturing method
JP2734761B2 (en) TAB film carrier and inner lead bonding method for TAB mounted semiconductor device
JPH07201914A (en) Semiconductor device and manufacture thereof
JPH01119045A (en) Lead frame
JPH03248543A (en) Film carrier tape
JPH04279052A (en) Semiconductor integrated circuit device