JPH02301133A - Forming method for back side electrode of semiconductor device - Google Patents
Forming method for back side electrode of semiconductor deviceInfo
- Publication number
- JPH02301133A JPH02301133A JP12118089A JP12118089A JPH02301133A JP H02301133 A JPH02301133 A JP H02301133A JP 12118089 A JP12118089 A JP 12118089A JP 12118089 A JP12118089 A JP 12118089A JP H02301133 A JPH02301133 A JP H02301133A
- Authority
- JP
- Japan
- Prior art keywords
- film
- back side
- electrode
- etching
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000000034 method Methods 0.000 title claims abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 230000001590 oxidative effect Effects 0.000 claims abstract description 6
- 239000007772 electrode material Substances 0.000 claims abstract description 5
- 238000000151 deposition Methods 0.000 claims abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 11
- 239000000853 adhesive Substances 0.000 abstract description 11
- 230000001070 adhesive effect Effects 0.000 abstract description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 11
- 229920005591 polysilicon Polymers 0.000 abstract description 11
- 229910052710 silicon Inorganic materials 0.000 abstract description 11
- 239000010703 silicon Substances 0.000 abstract description 11
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 11
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 abstract description 4
- 238000004544 sputter deposition Methods 0.000 abstract description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 abstract description 2
- 239000002253 acid Substances 0.000 abstract description 2
- 229910052804 chromium Inorganic materials 0.000 abstract description 2
- 239000011651 chromium Substances 0.000 abstract description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052737 gold Inorganic materials 0.000 abstract description 2
- 239000010931 gold Substances 0.000 abstract description 2
- 229910052759 nickel Inorganic materials 0.000 abstract description 2
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000003746 surface roughness Effects 0.000 description 2
- VZGDMQKNWNREIO-UHFFFAOYSA-N tetrachloromethane Chemical compound ClC(Cl)(Cl)Cl VZGDMQKNWNREIO-UHFFFAOYSA-N 0.000 description 2
- 238000007738 vacuum evaporation Methods 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical group [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- PXBRQCKWGAHEHS-UHFFFAOYSA-N dichlorodifluoromethane Chemical compound FC(F)(Cl)Cl PXBRQCKWGAHEHS-UHFFFAOYSA-N 0.000 description 1
- 235000019404 dichlorodifluoromethane Nutrition 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
（概 要〕
本発明は、各種半導体装置の裏面電極を形成する方法に
関し、半導体基板に対する裏面電極の接着強度を高める
ため、半導体基板の裏面に多結晶膜を形成し、その表面
を酸化した後、これらを十分に大きな選択比でエツチン
グすることにより、上記半導体基板の裏面に上記多結晶
膜表面の粒状の凹凸に対応して増幅された荒れを生じさ
せ、このように荒れて表面積（接着面）の大きくなった
裏面に電極を形成することにより、接着強度の増大を図
ったものである。[Detailed Description of the Invention] (Summary) The present invention relates to a method for forming a back electrode of various semiconductor devices, in which a polycrystalline film is formed on the back surface of a semiconductor substrate in order to increase the adhesive strength of the back electrode to the semiconductor substrate. After oxidizing the surface, etching them with a sufficiently large selection ratio produces amplified roughness on the back surface of the semiconductor substrate corresponding to the granular irregularities on the surface of the polycrystalline film. By forming electrodes on the back surface, which has become rough and has a large surface area (adhesive surface), the adhesive strength is increased.
本発明は、例えばパワー用トランジスタ等のような裏面
電極を有する半導体装置の製造工程におＣする、裏面電
極の形成方法に関する。The present invention relates to a method for forming a back electrode, which is used in the manufacturing process of a semiconductor device having a back electrode, such as a power transistor.
従来は、第２図に示すように、単にシリコン基板ｌの裏
面ｌａ上に、電極材料を真空蒸着法やスパッタ法により
堆積させて、裏面電極２を形成していた。Conventionally, as shown in FIG. 2, the back electrode 2 has been formed by simply depositing an electrode material on the back surface la of a silicon substrate l by vacuum evaporation or sputtering.
上記のよう、にして裏面電極２が形成され、素子が完成
すると、今度は素子全体が上記裏面電極２を介してモリ
ブデン板等にハンダ等でダイホンディングされる。After the back electrode 2 is formed as described above and the device is completed, the entire device is die-bonded to a molybdenum plate or the like using solder or the like via the back electrode 2.
ところが、上記のようにして形成された裏面電極２は、
シリコン基板ｌの裏面１ａとの接着強度が弱いため、温
度サイクルに基づくシリコン基板ｌと上記モリブデン板
との熱膨張率の違い等により、シリコン基板ｌの裏面１
ａから剥がれてしまい易いという問題があった。However, the back electrode 2 formed as described above is
Since the adhesive strength with the back side 1a of the silicon substrate l is weak, the back side 1 of the silicon substrate l is
There was a problem that it was easy to peel off from a.
本発明は、上記従来の問題点に鑑みてなされたものであ
り、その目的は、半導体基板に対する裏面電極の接着強
度を高めて、温度サイクル等による剥がれを防止するこ
とのできる裏面電極形成方法を提供することにある。The present invention has been made in view of the above-mentioned conventional problems, and its purpose is to provide a method for forming a back electrode that can increase the adhesive strength of the back electrode to a semiconductor substrate and prevent it from peeling off due to temperature cycles, etc. It is about providing.
（課題を解決するための手段）
本発明の裏面電極形成方法は、半導体基板の裏面に多結
晶膜を形成する工程と、該多結晶膜の表面を酸化して酸
化膜を形成する工程と、該酸化膜に対する前記多結晶膜
のエツチング選択比が十分に大きい条件で、前記酸化膜
及び多結晶膜にエツチングを施して除去する工程と、該
エツチングによって露出された前記半導体基板の裏面に
電極材料を堆積させて裏面電極を形成する工程とを備え
たことを特徴とする。(Means for Solving the Problems) The method for forming a backside electrode of the present invention includes a step of forming a polycrystalline film on the backside of a semiconductor substrate, a step of oxidizing the surface of the polycrystalline film to form an oxide film, etching and removing the oxide film and the polycrystalline film under conditions where the etching selectivity of the polycrystalline film to the oxide film is sufficiently large; and applying an electrode material to the back surface of the semiconductor substrate exposed by the etching. and forming a back electrode by depositing.
半導体基板の裏面に形成された上記多結晶膜は多数の単
結晶粒の集まりであり、その表面には微細な粒状の凹凸
ができている。そのため、この多結晶膜の表面を酸化し
てできた酸化膜は、上記凹凸の状態に応じて、膜厚にむ
らが生じる。そこで、上記のように酸化膜に対する多結
晶膜のエツチング選択比が十分に大きい条件でエツチン
グを行うと、酸化膜の膜厚の薄い部分では厚い部分より
も短時間で除去されるので、その時間差に応じて、酸化
膜直下の多結晶膜におけるエツチングの進行度合に大き
な差が生じ、このエツチングの差がそのまま半導体基板
の裏面に影響を及ぼす。すなわち、上記多結晶膜表面の
凹凸に応じて生じた酸化膜の膜厚むらが増幅されて、半
導体基板の裏面に荒れとなって生じる。The polycrystalline film formed on the back surface of the semiconductor substrate is a collection of many single crystal grains, and its surface has fine granular irregularities. Therefore, the oxide film formed by oxidizing the surface of this polycrystalline film has unevenness in film thickness depending on the state of the unevenness. Therefore, if etching is performed under conditions where the etching selectivity of the polycrystalline film to the oxide film is sufficiently large as described above, the thinner parts of the oxide film will be removed in a shorter time than the thicker parts, and the time difference will increase. Depending on the degree of etching, a large difference occurs in the degree of progress of etching in the polycrystalline film immediately below the oxide film, and this difference in etching directly affects the back surface of the semiconductor substrate. That is, the unevenness in the thickness of the oxide film caused by the unevenness on the surface of the polycrystalline film is amplified and becomes rough on the back surface of the semiconductor substrate.
これにより、半導体基板の裏面の表面積、すなわち裏面
電極との接着面が増大し、よって非常に大きな接着力が
得られる。This increases the surface area of the back surface of the semiconductor substrate, that is, the bonding surface with the back electrode, and thus provides a very large adhesive force.
［実 施 例］
以下、本発明の実施例について、図面を参照しながら説
明する。[Examples] Examples of the present invention will be described below with reference to the drawings.
第１図は、本発明の裏面電極形成方法の一実施例を示す
製造工程図である。FIG. 1 is a manufacturing process diagram showing an embodiment of the back electrode forming method of the present invention.
まず第１図（ａ）に示すように、シリコン基板１１の裏
面１１ａ上に、厚さ３０００人程度０ポリシリコン膜１
２を成長させる。ここで１１図面上ではわからないが、
ポリシリコン膜１２は直径１００〜２００人程度または
それ以下の微細な単結晶粒が多数集まってできており、
その表面には上記単結晶粒による微細な粒状の凹凸がで
きている。First of all, as shown in FIG.
Grow 2. 11 Although it is not clear on the drawing,
The polysilicon film 12 is made up of a large number of fine single crystal grains with a diameter of about 100 to 200 grains or less,
The surface has fine granular irregularities formed by the single crystal grains.
続いて、第１図（ｂ）に示すように、上記ポリシリコン
膜１２の表面を酸化性雰囲気中で熱処理するか、或いは
酸によりウェット酸化することにより、シリコン酸化膜
（ＳｉＯ□）１３を薄く形成する。Subsequently, as shown in FIG. 1(b), the surface of the polysilicon film 12 is heat-treated in an oxidizing atmosphere or wet-oxidized with acid to thin the silicon oxide film (SiO□) 13. Form.
この際、シリコン酸化膜１３は図面上では均一な膜厚に
描かれているが、実際は均一な膜厚にならず、ポリシリ
コン膜１２表面にできている上記凹凸の状態に応じて、
膜厚にむらが生じる。上記の酸化は、シリコン酸化膜１
３の膜厚が、厚い所で例えば１００〜１５０人程度にな
るまで行う。At this time, although the silicon oxide film 13 is drawn to have a uniform thickness in the drawing, in reality it is not uniform in thickness, and varies depending on the unevenness formed on the surface of the polysilicon film 12.
The film thickness becomes uneven. The above oxidation is performed on silicon oxide film 1
The process is continued until the film thickness in step 3 reaches about 100 to 150 people in thick places.
次に、シリコン酸化膜１３に対するポリシリコン膜１２
のエツチング選択比が十分に大きい条件で、全面にドラ
イエツチングを施す。例えば、シリコン酸化膜１３のエ
ツチング速度を１とした場合、ポリシリコン膜１２のエ
ツチング速度が１０〜２０程度となるような条件を選ぶ
。このような選択比を得るためのエツチングガスとして
は、例えばＣＦａ 、ＣＣｌ２Ｆ２ 、ＣＣｌ４等を使
用できる。Next, the polysilicon film 12 is applied to the silicon oxide film 13.
Dry etching is applied to the entire surface under conditions where the etching selection ratio is sufficiently large. For example, if the etching rate of silicon oxide film 13 is 1, conditions are selected such that the etching rate of polysilicon film 12 is about 10 to 20. As an etching gas for obtaining such a selectivity, for example, CFa, CCl2F2, CCl4, etc. can be used.
このエツチングは、ポリシリコン膜１２が全て除去され
て、シリコン基板１１の裏面１１ａが完全に露出するま
で行う。This etching is performed until all of the polysilicon film 12 is removed and the back surface 11a of the silicon substrate 11 is completely exposed.
上記のエツチングでは、シリコン酸化膜１３の膜厚の薄
い部分では厚い部分よりも短時間で除去されるので、そ
の時間差に応じて、シリコン酸化膜１３直下のポリシリ
コン膜１２におけるエソチ−ングの進行度合に大きな差
が生じ、このエッチングの差がそのままシリコン基板１
１の裏面１１ａに影響を及ぼす。すなわち、このエツチ
ングにより、シリコン酸化膜１３の膜厚むらが上記エツ
チング選択比に等しい１０〜２０倍に増幅されて、第１
図（Ｃ）に示すようにシリコン基板１１の裏面ｌｌａの
荒れとなって生じる。エツチング後の裏面１１ａからは
、その表面粗さにして、例えば厚さ方向に１０００〜２
０００人程度、かつ面内方向に３００〜５００人程度の
非常に微細な荒れを得ることができる。In the above etching, the thinner parts of the silicon oxide film 13 are removed in a shorter time than the thicker parts, so the progress of etho-etching in the polysilicon film 12 directly under the silicon oxide film 13 depends on the time difference. A large difference occurs in the degree of etching, and this difference in etching is directly reflected in the silicon substrate 1.
This affects the back surface 11a of 1. That is, by this etching, the film thickness unevenness of the silicon oxide film 13 is amplified by a factor of 10 to 20, which is equal to the etching selectivity, and the first
As shown in Figure (C), the back surface lla of the silicon substrate 11 becomes rough. The surface roughness of the back surface 11a after etching is, for example, 1000 to 2 in the thickness direction.
It is possible to obtain very fine roughness of about 300 to 500 in the in-plane direction.
その後、シリコン基板１１の荒れた裏面１１ａ上に、真
空蒸着法やスパッタ法で電極材料を堆積させることによ
り、第１図（ｄ）に示すように裏面電極１４を形成する
。この裏面電極１４としては、裏面１１ａ側から順に、
例えばクロム、ニッケル、金からなる３層構造とするこ
とができる。Thereafter, an electrode material is deposited on the rough back surface 11a of the silicon substrate 11 by vacuum evaporation or sputtering to form a back electrode 14 as shown in FIG. 1(d). This back electrode 14 includes, in order from the back surface 11a side:
For example, it can have a three-layer structure consisting of chromium, nickel, and gold.
本実施例によれば、上述したようにシリコン基板ｌｌの
裏面１１ａにオングストロームオーダの非常に微細な荒
れを得ることができるので、裏面１１ａの表面積が大き
くなり、すなわち裏面電極１４との接着面が大きくなり
、よって裏面電極１４と裏面１１ａとの間で非常に大き
な接着力を得ることができる。これにより、前述したグ
イボンディング後においても、裏面電極１４が裏面ｌｌ
ａ上からたやすく剥がれるようなことはなくなる。According to this embodiment, as described above, it is possible to obtain extremely fine roughness on the order of angstroms on the back surface 11a of the silicon substrate 11, so that the surface area of the back surface 11a is increased, that is, the adhesive surface with the back electrode 14 is Therefore, a very large adhesive force can be obtained between the back electrode 14 and the back surface 11a. As a result, even after the above-mentioned Gui bonding, the back electrode 14 is
It will no longer be easily peeled off from above.
なお、上記実施例におけるポリシリコン膜１２及びシリ
コン酸化膜１３の厚さはほんの一例であり、これに限定
されることはない。Note that the thicknesses of the polysilicon film 12 and silicon oxide film 13 in the above embodiments are just examples, and are not limited thereto.
また、シリコン基板１１の裏面１１ａの表面粗さは、主
には、上述したエツチング選択比によって決定されるが
、この選択比も上述した値に限定されることはなく、裏
面１ａに荒れを生じさせることのできる程度に十分に大
きな値であればよい。Further, the surface roughness of the back surface 11a of the silicon substrate 11 is mainly determined by the etching selection ratio described above, but this selection ratio is not limited to the above-mentioned value, and may cause roughness on the back surface 1a. It is sufficient if the value is sufficiently large to the extent that it can be used.
更に、ポリシリコン膜１２の代わりに、他の多結晶膜を
使用してもよい。ただし、この場合、その多結晶膜表面
に形成される酸化膜に対して十分なエツチング選択比を
とりうるものを選ぶ必要がある。Furthermore, other polycrystalline films may be used instead of polysilicon film 12. However, in this case, it is necessary to select a material that can provide a sufficient etching selectivity with respect to the oxide film formed on the surface of the polycrystalline film.
また、裏面電極１４の構造は上述したような３層構造で
ある必要は全くなく、その他の構造であっても本発明の
効果に何ら変わりはない。Further, the structure of the back electrode 14 does not need to be the three-layer structure as described above, and the effects of the present invention will not change in any way even if other structures are used.
本発明によれば、半導体基板の裏面に多結晶膜表面の微
細な凹凸に対応して増幅された荒れを生じさせ、このよ
うに荒れて表面積（接着面）の大きくなった裏面に電極
を形成するようにしたので、裏面電極の接着力を著しく
増大させることができる。According to the present invention, amplified roughness corresponding to minute irregularities on the surface of a polycrystalline film is generated on the back surface of a semiconductor substrate, and electrodes are formed on the back surface where the surface area (adhesion surface) is increased due to the roughness. By doing so, the adhesive force of the back electrode can be significantly increased.
第１図（ａ）〜（ｄ）は本発明の裏面電極形成方法の一
実施例を示す製造工程図、
第２図（ａ）及び（ロ）は従来の裏面電極形°成力法の
一例を示す製造工程図である。
１１・・・シリコン基板、
１１ａ・・・裏面、
１２・・・ポリシリコン膜、
１３・・・シリコン酸化膜、
１４・・・裏面電極。
特許出願人 株式会社豊田自動織機製作所（Ｑ）
第１図Figures 1 (a) to (d) are manufacturing process diagrams showing one embodiment of the back electrode forming method of the present invention, and Figures 2 (a) and (b) are examples of the conventional back electrode forming method. FIG. DESCRIPTION OF SYMBOLS 11...Silicon substrate, 11a...Back surface, 12...Polysilicon film, 13...Silicon oxide film, 14...Back surface electrode. Patent applicant: Toyota Industries Corporation (Q) Figure 1
Claims (1)
）を形成する工程と、 該多結晶膜の表面を酸化して酸化膜（１３）を形成する
工程と、 該酸化膜に対する前記多結晶膜のエッチング選択比が十
分に大きい条件で、前記酸化膜及び多結晶膜にエッチン
グを施して除去する工程と、該エッチングによって露出
された前記半導体基板の裏面に電極材料を堆積させて裏
面電極（１４）を形成する工程とを備えたことを特徴と
する半導体装置の裏面電極形成方法。[Claims] A polycrystalline film (12) is formed on the back surface (11a) of the semiconductor substrate (11).
), a step of oxidizing the surface of the polycrystalline film to form an oxide film (13), and etching the oxide film under conditions where the etching selectivity of the polycrystalline film to the oxide film is sufficiently large. and a step of etching and removing the polycrystalline film, and a step of depositing an electrode material on the back surface of the semiconductor substrate exposed by the etching to form a back electrode (14). A method for forming a backside electrode of a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12118089A JPH02301133A (en) | 1989-05-15 | 1989-05-15 | Forming method for back side electrode of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12118089A JPH02301133A (en) | 1989-05-15 | 1989-05-15 | Forming method for back side electrode of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02301133A true JPH02301133A (en) | 1990-12-13 |
Family
ID=14804832
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12118089A Pending JPH02301133A (en) | 1989-05-15 | 1989-05-15 | Forming method for back side electrode of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02301133A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003063200A3 (en) * | 2002-01-16 | 2005-01-27 | Sputtered Films Inc | Method for improving the adhesion of a coating |
-
1989
- 1989-05-15 JP JP12118089A patent/JPH02301133A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003063200A3 (en) * | 2002-01-16 | 2005-01-27 | Sputtered Films Inc | Method for improving the adhesion of a coating |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US3886578A (en) | Low ohmic resistance platinum contacts for vanadium oxide thin film devices | |
| EP0856876A3 (en) | Method of manufacturing a bonding substrate | |
| JPH098124A (en) | Insulation separation substrate and its manufacture | |
| JPH02301133A (en) | Forming method for back side electrode of semiconductor device | |
| JPH03109731A (en) | Manufacture of semiconductor substrate | |
| JPS6377122A (en) | Manufacture of semiconductor device | |
| US6702637B2 (en) | Method of forming a small gap and its application to the fabrication of a lateral FED | |
| JP2857456B2 (en) | Method for manufacturing semiconductor film | |
| JPH01226166A (en) | Manufacture of semiconductor device substrate | |
| JPH06221945A (en) | Semiconductor pressure sensor and manufacture thereof | |
| JPS6258541B2 (en) | ||
| JPH02205339A (en) | Manufacture of semiconductor device | |
| JP2570729B2 (en) | Method for manufacturing semiconductor device | |
| KR100213759B1 (en) | Fabricating method of micro-beam for semiconductor sensor | |
| JPH05226307A (en) | Manufacture of semiconductor substrate | |
| JPH01224671A (en) | Manufacture of semiconductor acceleration sensor | |
| JPS62283679A (en) | Manufacture of semiconductor pressure sensor | |
| JPS6257114B2 (en) | ||
| JPS5823929B2 (en) | Manufacturing method of semiconductor device | |
| JPH06104680A (en) | Surface acoustic wave element | |
| JP2580612B2 (en) | Method for manufacturing semiconductor device | |
| JPH0233974A (en) | Manufacture of pressure converter | |
| JPH01259555A (en) | Semiconductor device and manufacture thereof | |
| JPS6337652A (en) | Adhesion method of substrate for semiconductor device | |
| JPH0290560A (en) | Manufacture of capacitor insulating film |