JPH03109731A - Manufacture of semiconductor substrate - Google Patents

Manufacture of semiconductor substrate

Info

Publication number
JPH03109731A
JPH03109731A JP24876589A JP24876589A JPH03109731A JP H03109731 A JPH03109731 A JP H03109731A JP 24876589 A JP24876589 A JP 24876589A JP 24876589 A JP24876589 A JP 24876589A JP H03109731 A JPH03109731 A JP H03109731A
Authority
JP
Japan
Prior art keywords
semiconductor substrate
layer
impurity concentration
substrate
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24876589A
Other languages
Japanese (ja)
Inventor
Yoshio Hattori
服部 芳雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP24876589A priority Critical patent/JPH03109731A/en
Publication of JPH03109731A publication Critical patent/JPH03109731A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain a thin semiconductor substrate layer uniformly on an insulating film by adhering a semiconductor substrate formed with the substrate layer having low impurity concentration on the surface of a semiconductor substrate having high impurity concentration to another substrate through an insulating film. CONSTITUTION:An epitaxial layer 2 having low impurity concentration is formed on a semiconductor substrate 1 having high impurity concentration, an oxide film 3 is formed on the layer 2, the substrate 1 is adhered to another substrate 4 to be adhered through the film 3, the substrate 1 is polished to be reduced in thickness, the adhered substrate 1 is immersed with etchant to remove the substrate 1 having high impurity concentration by etching, the layer 2 is oxidized to form an oxide film 5 in which the thickness of the epitaxial layer is reduced. The thickness of the layer 2 can be controlled to be thinner by the formation of the film 5. Here, if the thickness of the layer 2 is thicker than a desired thickness, the steps of forming and removing the film 5 may be repeated. Thus, the semiconductor substrate having a reduced thickness without irregularity in the thickness can be realized on the insulting film.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体基板を貼合わせて絶縁膜上に薄い半導体
基板層を形成した半導体基板の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor substrate in which semiconductor substrates are bonded together to form a thin semiconductor substrate layer on an insulating film.

〔発明の概要〕[Summary of the invention]

本発明は不純物濃度の高い半導体基板の表面に不純物濃
度の低い半導体基板層を形成した半導体基板を絶縁膜を
介して別の基板に貼合わせて、研摩と不純物濃度差によ
る選択エツチング、犠牲酸化とを組み合わせて、絶縁膜
上に11M以下の均一で薄い半導体基板層を存する半導
体基板の実用的な製造方法を捉供するものである。
In the present invention, a semiconductor substrate with a low impurity concentration semiconductor layer formed on the surface of a semiconductor substrate with a high impurity concentration is bonded to another substrate via an insulating film, and polishing, selective etching based on the difference in impurity concentration, and sacrificial oxidation are performed. The present invention provides a practical method for manufacturing a semiconductor substrate having a uniform and thin semiconductor substrate layer of 11M or less on an insulating film.

〔従来の技術〕[Conventional technology]

従来、絶縁股上に薄い半導体基板層を形成する方法とし
て、貼り合わせ基板が知られている。
2. Description of the Related Art Conventionally, a bonded substrate is known as a method for forming a thin semiconductor substrate layer on an insulating layer.

第2図は従来の貼合わせ半導体基板の製造工程順の断面
図である。
FIG. 2 is a cross-sectional view of a conventional bonded semiconductor substrate in the order of manufacturing steps.

半導体基板21に酸化膜23を形成する(第2図(a)
)前記半導体基板21を酸化膜23を介して別の貼合わ
せ基板24に貼合わせる(第2図山))。
An oxide film 23 is formed on the semiconductor substrate 21 (FIG. 2(a))
) The semiconductor substrate 21 is bonded to another bonded substrate 24 via the oxide film 23 (Fig. 2, crest)).

前記半導体基板21を研摩し半導体基板21を薄くして
、従来の貼合わせ半導体基板は完成する。
The semiconductor substrate 21 is polished to make the semiconductor substrate 21 thinner, and a conventional bonded semiconductor substrate is completed.

第2図(C))。Figure 2 (C)).

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

絶縁膜上の半導体基板21の厚みは1ffl以下が望ま
しいが、半導体基板全面を111m以下に均一に研摩す
ることは困難で、半導体基板21の厚みは2〜3−程度
にするのが限界であった。
The thickness of the semiconductor substrate 21 on the insulating film is preferably 1 ffl or less, but it is difficult to uniformly polish the entire surface of the semiconductor substrate to 111 m or less, and the maximum thickness of the semiconductor substrate 21 is about 2 to 3 mm. Ta.

〔課題を解決するための手段〕[Means to solve the problem]

本発明は前記課題を解決するために、不純物濃度の高い
半導体基板表面に、不純物濃度が低く、厚さも薄いエピ
タキシャル層を形成し、この基板を別の貼合わせ基板に
絶縁膜を介して貼合わせて、研摩と不純物濃度差による
選択エツチング、犠牲酸化とを組合わせて、不純物濃度
の高い半導体基板を除去して、絶縁膜上に不純物濃度の
低いエピタキシャル基板層のみを残して、絶I!膜上に
薄く、かつ、均一な半導体基板層を形成するものである
In order to solve the above problems, the present invention forms a thin epitaxial layer with a low impurity concentration on the surface of a semiconductor substrate with a high impurity concentration, and then bonds this substrate to another bonded substrate via an insulating film. Then, by combining polishing, selective etching based on the difference in impurity concentration, and sacrificial oxidation, the semiconductor substrate with high impurity concentration is removed, leaving only the epitaxial substrate layer with low impurity concentration on the insulating film. A thin and uniform semiconductor substrate layer is formed on the film.

〔実施例〕 以下本発明の詳細を図面を用いて説明する。〔Example〕 The details of the present invention will be explained below with reference to the drawings.

第1図は本発明の半導体基板の製造方法を示す工程順断
面図である。
FIG. 1 is a step-by-step sectional view showing a method for manufacturing a semiconductor substrate according to the present invention.

第1図1alは、不純物濃度が10 ’ ”cm−’以
上の濃度の高い半導体基板1に不純物濃度の低いエピタ
キシャルN(以下エビ層)2を形成した工程の断面図で
ある。
FIG. 1 1al is a cross-sectional view of a process in which epitaxial N (hereinafter referred to as a shrimp layer) 2 with a low impurity concentration is formed on a semiconductor substrate 1 with a high impurity concentration of 10'''cm-' or more.

第1回出)は前記エビ層2の表面に酸化膜3を形成した
工程の断面図である。
1st issue) is a cross-sectional view of the step of forming an oxide film 3 on the surface of the shrimp layer 2.

第1図(C)は酸化!l!3を介して別の貼合わせ基板
4に半導体基板1を貼合わせた工程の断面図である。
Figure 1 (C) shows oxidation! l! 3 is a cross-sectional view of a process in which the semiconductor substrate 1 is bonded to another bonded substrate 4 via the bonded substrate 3. FIG.

第1図1dlは貼合わせた半導体基板1を研摩し薄くし
た工程の断面図である0機械的な研摩は、半導体基板l
を薄くするスピードが速い。しかし、厚みむらは大きい
、そこで、不純物濃度の高い半導体基板1を薄く残して
いる。
Figure 1 1dl is a cross-sectional view of the process of polishing and thinning the bonded semiconductor substrate 1.
The speed of thinning is fast. However, the thickness unevenness is large, so the semiconductor substrate 1 with a high impurity concentration is left thin.

第1図1etは、10”cs+−”以上の不純物濃度の
高い半導体基板のみを選択的にエツチングする例えば、
フン酸と硝酸、酢酸を1:3:8に混合したエツチング
液に貼合わせた半導体基板lを浸し、不純物濃度の高い
半導体基板1をエツチング除去した工程の断面図である
。不純物濃度の高い半導体基板1はエツチング液によっ
てエツチング除去されるが、不純物濃度の低いエビ層2
はエツチングされずに残る。したがって、残った絶縁膜
上の半導体基板はエビ層2のみで、その厚みはエビ層2
を成長させた時のエビ層でほぼ決まる。エビ層の厚みの
制御は容易で厚みむらはほとんど生じない。
FIG. 1 1et shows, for example, selectively etching only a semiconductor substrate with a high impurity concentration of 10"cs+-" or more.
This is a cross-sectional view of a process in which the semiconductor substrate 1 with a high impurity concentration is etched away by immersing the bonded semiconductor substrate 1 in an etching solution containing a 1:3:8 mixture of hydronic acid, nitric acid, and acetic acid. The semiconductor substrate 1 with a high impurity concentration is etched away by an etching solution, but the shrimp layer 2 with a low impurity concentration
remains unetched. Therefore, the remaining semiconductor substrate on the insulating film is only the shrimp layer 2, and its thickness is the shrimp layer 2.
It is almost determined by the shrimp layer when grown. It is easy to control the thickness of the shrimp layer, and there is almost no unevenness in the thickness.

そこで、研摩によって生じた絶縁股上の半導体基板1の
厚みむらは無くすことができる。
Therefore, the thickness unevenness of the semiconductor substrate 1 on the insulating ridge caused by polishing can be eliminated.

第1図(flはエビ層2を酸化してエビ層の厚みを薄く
する酸化膜5を形成する工程の断面図である。
FIG. 1 (fl is a cross-sectional view of the step of forming an oxide film 5 that oxidizes the shrimp layer 2 to reduce the thickness of the shrimp layer.

この酸化膜5の形成により、エビN2の厚みをより薄く
制御するものである。また、選択エツチングにより生じ
たエビ層2の表面の欠陥を取除く効果もある。
By forming this oxide film 5, the thickness of the shrimp N2 is controlled to be thinner. It also has the effect of removing defects on the surface of the shrimp layer 2 caused by selective etching.

第1図(g)は酸化膜5をエツチング除去して、本発明
の半導体基板を完成させた工程の断面図である。また、
この工程でエビ層2の厚みが所望の厚みより厚い場合は
、酸化膜5を形成し除去する工程を繰り返せば良いこと
は明らかである。
FIG. 1(g) is a cross-sectional view of the step in which the oxide film 5 is removed by etching to complete the semiconductor substrate of the present invention. Also,
It is clear that if the thickness of the shrimp layer 2 is thicker than the desired thickness in this step, the steps of forming and removing the oxide film 5 may be repeated.

本発明の製造方法を用いれば、絶縁膜上の半導体基板層
の厚みを0.5n以下にすることも可能で理想的な絶縁
膜分離と接合容量を実現した高速MOS集積回路等に用
いる半導体基板を製造できる。
By using the manufacturing method of the present invention, it is possible to reduce the thickness of the semiconductor substrate layer on the insulating film to 0.5n or less, and the semiconductor substrate used for high-speed MOS integrated circuits etc. achieves ideal insulating film separation and junction capacitance. can be manufactured.

〔発明の効果〕〔Effect of the invention〕

以上の説明で明らかなように、本発明は不純物濃度の高
い半導体基板に不純物濃度の低いエビ層を形成し、酸化
膜を介して貼合わせた基板に貼合わせ、研摩と不純物濃
度による選択エツチング、犠牲酸化とを組合わせて、絶
縁膜上に薄く、かつ、厚みむらのない半導体基板を実現
できるものである。
As is clear from the above description, the present invention involves forming a layer with a low impurity concentration on a semiconductor substrate with a high impurity concentration, bonding the layer to a bonded substrate via an oxide film, polishing and selective etching according to the impurity concentration, By combining this method with sacrificial oxidation, it is possible to realize a semiconductor substrate that is thin and has no thickness unevenness on an insulating film.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の半導体基板の製造方法を示す工程順断
面図、第2図は従来の半導体基板の製造方法を示す工程
順の断面図である。 1121・・・半導体基板 2・ ・ ・ ・ ・エビ層 3.23・・・酸化膜 4゜ 24・ ・貼合わせ基板 ・酸化膜 以 上
FIG. 1 is a step-by-step cross-sectional view showing a method for manufacturing a semiconductor substrate according to the present invention, and FIG. 2 is a step-by-step cross-sectional view showing a conventional semiconductor substrate manufacturing method. 1121... Semiconductor substrate 2... - Shrimp layer 3.23... Oxide film 4゜24... Bonded substrate - Oxide film or more

Claims (1)

【特許請求の範囲】 不純物濃度の高い半導体基板表面に、不純物濃度の低い
層を形成する工程と、 前記不純物濃度の低い層の上に絶縁膜を介して基板を貼
合わせる工程と、 前記不純物濃度の高い半導体基板を研摩し薄くする工程
と、 前記不純物濃度の高い半導体基板をエッチング除去する
工程と、 前記不純物濃度の低い層を酸化し、酸化膜を形成し、前
記酸化膜を除去する工程とから成る半導体基板の製造方
法。
[Claims] A step of forming a layer with a low impurity concentration on the surface of a semiconductor substrate with a high impurity concentration; a step of laminating a substrate on the layer with a low impurity concentration via an insulating film; a step of polishing and thinning a semiconductor substrate with a high impurity concentration, a step of etching away the semiconductor substrate with a high impurity concentration, a step of oxidizing the layer with a low impurity concentration to form an oxide film, and a step of removing the oxide film. A method for manufacturing a semiconductor substrate comprising:
JP24876589A 1989-09-25 1989-09-25 Manufacture of semiconductor substrate Pending JPH03109731A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24876589A JPH03109731A (en) 1989-09-25 1989-09-25 Manufacture of semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24876589A JPH03109731A (en) 1989-09-25 1989-09-25 Manufacture of semiconductor substrate

Publications (1)

Publication Number Publication Date
JPH03109731A true JPH03109731A (en) 1991-05-09

Family

ID=17183044

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24876589A Pending JPH03109731A (en) 1989-09-25 1989-09-25 Manufacture of semiconductor substrate

Country Status (1)

Country Link
JP (1) JPH03109731A (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07183477A (en) * 1993-12-22 1995-07-21 Nec Corp Manufacture of semiconductor substrate
US5466631A (en) * 1991-10-11 1995-11-14 Canon Kabushiki Kaisha Method for producing semiconductor articles
US5705421A (en) * 1994-11-24 1998-01-06 Sony Corporation A SOI substrate fabricating method
US5840616A (en) * 1991-05-22 1998-11-24 Canon Kabushiki Kaisha Method for preparing semiconductor member
WO2000024059A1 (en) * 1998-10-16 2000-04-27 Shin-Etsu Handotai Co., Ltd. Method of producing soi wafer by hydrogen ion implanting separation method and soi wafer produced by the method
WO2000062343A1 (en) * 1999-04-09 2000-10-19 Shin-Etsu Handotai Co., Ltd. Soi wafer and method for producing soi wafer
US6544862B1 (en) 2000-01-14 2003-04-08 Silicon Genesis Corporation Particle distribution method and resulting structure for a layer transfer process
US6790747B2 (en) 1997-05-12 2004-09-14 Silicon Genesis Corporation Method and device for controlled cleaving process
US8993410B2 (en) 2006-09-08 2015-03-31 Silicon Genesis Corporation Substrate cleaving under controlled stress conditions
US9362439B2 (en) 2008-05-07 2016-06-07 Silicon Genesis Corporation Layer transfer of films utilizing controlled shear region

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5840616A (en) * 1991-05-22 1998-11-24 Canon Kabushiki Kaisha Method for preparing semiconductor member
US5466631A (en) * 1991-10-11 1995-11-14 Canon Kabushiki Kaisha Method for producing semiconductor articles
JPH07183477A (en) * 1993-12-22 1995-07-21 Nec Corp Manufacture of semiconductor substrate
US5705421A (en) * 1994-11-24 1998-01-06 Sony Corporation A SOI substrate fabricating method
US6790747B2 (en) 1997-05-12 2004-09-14 Silicon Genesis Corporation Method and device for controlled cleaving process
US6372609B1 (en) 1998-10-16 2002-04-16 Shin-Etsu Handotai Co., Ltd. Method of Fabricating SOI wafer by hydrogen ION delamination method and SOI wafer fabricated by the method
WO2000024059A1 (en) * 1998-10-16 2000-04-27 Shin-Etsu Handotai Co., Ltd. Method of producing soi wafer by hydrogen ion implanting separation method and soi wafer produced by the method
EP1100127A4 (en) * 1999-04-09 2002-04-24 Shinetsu Handotai Kk Soi wafer and method for producing soi wafer
EP1100127A1 (en) * 1999-04-09 2001-05-16 Shin-Etsu Handotai Co., Ltd Soi wafer and method for producing soi wafer
US6461939B1 (en) 1999-04-09 2002-10-08 Shin-Etsu Handotai Co., Ltd. SOI wafers and methods for producing SOI wafer
WO2000062343A1 (en) * 1999-04-09 2000-10-19 Shin-Etsu Handotai Co., Ltd. Soi wafer and method for producing soi wafer
US6544862B1 (en) 2000-01-14 2003-04-08 Silicon Genesis Corporation Particle distribution method and resulting structure for a layer transfer process
US8993410B2 (en) 2006-09-08 2015-03-31 Silicon Genesis Corporation Substrate cleaving under controlled stress conditions
US9356181B2 (en) 2006-09-08 2016-05-31 Silicon Genesis Corporation Substrate cleaving under controlled stress conditions
US9640711B2 (en) 2006-09-08 2017-05-02 Silicon Genesis Corporation Substrate cleaving under controlled stress conditions
US9362439B2 (en) 2008-05-07 2016-06-07 Silicon Genesis Corporation Layer transfer of films utilizing controlled shear region
US11444221B2 (en) 2008-05-07 2022-09-13 Silicon Genesis Corporation Layer transfer of films utilizing controlled shear region

Similar Documents

Publication Publication Date Title
US5344524A (en) SOI substrate fabrication
JP3395661B2 (en) Method for manufacturing SOI wafer
JPH0964321A (en) Manufacture of soi substrate
EP0867922A3 (en) Semiconductor substrate and method of manufacturing the same
JP2001210810A (en) Semiconductor wafer and manufacturing method therefor
JPH03109731A (en) Manufacture of semiconductor substrate
US5953620A (en) Method for fabricating a bonded SOI wafer
EP0955670A3 (en) Method of forming oxide film on an SOI layer and method of fabricating a bonded wafer
JPH0917984A (en) Bonded soi substrate manufacturing method
JPH07235651A (en) Semiconductor substrate and manufacture thereof
JPH0945882A (en) Semiconductor substrate and manufacture thereof
JPH05109678A (en) Manufacture of soi substrate
JPH07183477A (en) Manufacture of semiconductor substrate
JP2766417B2 (en) Manufacturing method of bonded dielectric separation wafer
JP2855639B2 (en) Method for manufacturing semiconductor device
JPH01226166A (en) Manufacture of semiconductor device substrate
JPH08274286A (en) Manufacture of soi substrate
JP2981673B2 (en) Semiconductor substrate manufacturing method
JPH0342814A (en) Manufacture of semiconductor substrate
JPH03270254A (en) Manufacture of semiconductor device
JPH05241139A (en) Liquid crystal display device
JPH05152427A (en) Manufacture of semiconductor device
JPH05109693A (en) Manufacture of soi substrate
JPH0563169A (en) Manufacture of semiconductor device
JPH07193203A (en) Manufacture of semiconductor substrate