JPH0563169A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0563169A JPH0563169A JP15792791A JP15792791A JPH0563169A JP H0563169 A JPH0563169 A JP H0563169A JP 15792791 A JP15792791 A JP 15792791A JP 15792791 A JP15792791 A JP 15792791A JP H0563169 A JPH0563169 A JP H0563169A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- substrate
- resist
- soi substrate
- manufacture
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
【0001】[0001]
【0002】[0002]
【産業上の利用分野】本発明は半導体装置、特にシリコ
ンウエハ双方を直接接合してなるSOI基板の製作方法
に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a method for manufacturing an SOI substrate which is formed by directly bonding both silicon wafers.
【0003】[0003]
【従来の技術】低リーク電流、低寄生容量の特徴を有す
るSOI(Silconon Lnsulator)基
板は図2(a)〜(e)に示す方法で製作されている。
すなわち、SOI基板のサブストレートとなるウエハ9
と表・裏の両面が鏡面となつているウエハ10とを、H
2 O2 +H2 SO4 の洗浄を行い親水化処理し、水酸基
(−OH)が水素結合することを利用し、貼り合わせ1
100℃、N2 中、2hr処理し接合を完了するもので
これを(b)に示す。2. Description of the Related Art An SOI (Silconon Lnsulator) substrate having a characteristic of low leakage current and low parasitic capacitance is manufactured by the method shown in FIGS.
That is, the wafer 9 serving as the substrate of the SOI substrate
And the wafer 10 whose front and back surfaces are mirror surfaces,
2 O 2 + H 2 SO 4 was washed and hydrophilized, and the fact that the hydroxyl group (—OH) was hydrogen bonded was used to bond 1
The bonding is completed by treating for 2 hours at 100 ° C. in N 2 , which is shown in (b).
【0004】次にこのようにして得たSOI基板の片側
のシリコン11の部分をラツピングと称する荒い研磨で
削り落とす。これを(c)に示す。更に荒い研磨の機械
的な歪みを取り除くためにシリコン12の部分をエツチ
ング液により除去する、これを(d)に示す。Next, a portion of the silicon 11 on one side of the SOI substrate thus obtained is scraped off by rough polishing called lapping. This is shown in (c). The portion of the silicon 12 is removed by an etching liquid in order to remove the mechanical strain of the rough polishing, which is shown in (d).
【0005】次にシリンコンの膜厚が均一かつ表面が平
坦になる様に仕上げ研磨となるポリツシングを行い、シ
リコン13の部分を削り落として(e)に示すようにS
OI基板を製作するものである。(文献「直接接合によ
るSOI基板上ヘMOSFETの試作」電子情報通信学
会技術、研究報告Vol.87 No344 P43〜
48)Next, polishing for final polishing is performed so that the film thickness of the silicon oxide is uniform and the surface is flat, and the portion of the silicon 13 is scraped off to obtain S as shown in (e).
The OI substrate is manufactured. (Document “Trial manufacture of MOSFET on SOI substrate by direct bonding” Institute of Electronics, Information and Communication Technology, Research Report Vol.87 No 344 P43-
48)
【0006】[0006]
【発明が解決しようとする課題】しかし前記SOI基板
の製作方法は研磨工程がかなり複雑であり、特に仕上げ
研磨は通常のバルクシリコンに対する鏡面研磨の方法と
は違つている。However, in the method of manufacturing the SOI substrate, the polishing process is quite complicated, and the final polishing is different from the normal mirror polishing method for bulk silicon.
【0007】これは研磨によつてシリコンの薄膜を残す
ために膜厚分布を測定し、加工量を調整したり、ウエハ
間の膜厚バラツキを少なくするために仕上げ研磨を行う
前に膜厚を測定しウエハを厚みによつて振り分けて研磨
を行う必要があり、従つて工程が複雑となり、大量処理
に適さないという問題点があつた。This is because the film thickness distribution is measured by polishing so as to leave a thin film of silicon, the processing amount is adjusted, and the film thickness is adjusted before finishing polishing in order to reduce film thickness variation between wafers. It is necessary to measure the wafers and sort the wafers according to the thickness to perform polishing, which complicates the process and is not suitable for large-scale processing.
【0008】本発明はSOI基板の製造に於て貼り合わ
せ後に於てもウエハの平坦度が確保されかつ加工工程が
簡単化されるSOI基板の製作方法を技術的課題とする
ものである。An object of the present invention is to provide a method of manufacturing an SOI substrate in which the flatness of the wafer is ensured even after the bonding in the manufacture of the SOI substrate and the processing steps are simplified.
【0009】[0009]
【0010】[0010]
【課題を解決するための手段】課題を解決するために講
じた技術的手段は次のようである。[Means for Solving the Problems] The technical measures taken to solve the problems are as follows.
【0011】半導体装置であるSOI基板の製作方法と
して、SOI基板のサブストレートとなるウエハに酸化
膜を形成し、レジストを塗布し、ウエハ表面以外の酸化
膜を除去し、レジストを除去してサブストレートのウエ
ハを製作する。As a method of manufacturing an SOI substrate which is a semiconductor device, an oxide film is formed on a wafer which is a substrate of the SOI substrate, a resist is applied, the oxide film other than the wafer surface is removed, and the resist is removed to remove the substrate. Fabricate a straight wafer.
【0012】次に前記サブストレートのウエハと表、裏
の両面が鏡面でウエハを洗浄後、親水化処理を行い、次
に水素結合を利用し、熱処理を行つてウエハどうしの接
合を行い、前記サブストレートのウエハにレジストを塗
布し、表面側をエツチングして一定の厚さとし、レジス
トを除去してSOI基板を製作する半導体装置の製作方
法である。Next, the wafer of the substrate and the front and back surfaces are mirror-finished, and after the wafer is cleaned, hydrophilic treatment is performed, and then hydrogen bonding is used to perform heat treatment to bond the wafers. This is a method of manufacturing a semiconductor device in which a resist is applied to a substrate wafer, the front surface side is etched to a constant thickness, and the resist is removed to manufacture an SOI substrate.
【0013】[0013]
【作用】SOI基板の製作に於て、ウエハとサブストレ
ートとなるウエハとを接合後、レジストを塗布しウエハ
の裏面に弗硝酸サクサンに少量の沃素を添加剤として加
えたエツチング液を使用して、エツチングすることによ
りシリコン部分を取り除くことができ、かつその表面は
充分に平坦度が確保出来るもので、従来の機械的な荒研
磨及びポリツシングの様な複雑な工程の必要性がないも
のである。In the manufacture of the SOI substrate, after the wafer and the wafer to be the substrate are bonded together, a resist is applied to the back surface of the wafer using an etching solution in which a small amount of iodine is added to succin fluoride nitrate as an additive. , The silicon part can be removed by etching, and the surface can have sufficient flatness, so that there is no need for complicated processes such as conventional mechanical rough polishing and polishing. .
【0014】〔実施例〕以下実施例について説明する。EXAMPLES Examples will be described below.
【0015】図1の(a)〜(h)にSOI基板の製造
工程を示す。FIGS. 1A to 1H show the manufacturing process of an SOI substrate.
【0016】SOI基板のサブストレートとなるウエハ
1を酸化し、酸化膜2を形成するこれを(b)に示す。A wafer 1 which is a substrate of an SOI substrate is oxidized to form an oxide film 2 as shown in FIG.
【0017】次にウエハ表面にレジスト3を塗布し
(c)、ウエハ表面以外の酸化膜を除去し、つづいてレ
ジストを除去するこれを(d)に示す、ここまでの工程
でSOI基板のサブストレートとなるウエハ4が完成す
る。Next, the resist 3 is applied to the wafer surface (c), the oxide film other than the wafer surface is removed, and then the resist is removed. This is shown in (d). The straight wafer 4 is completed.
【0018】次にSOI基板のサブストレートとなるウ
エハ4と表・裏の両面が鏡面となつてウエハ5とをH2
O2 −H2 SO4 洗浄を行い、親水化処理を行い、水酸
基(−OH)が水素結合することを利用し、1100
℃、2hrN2 中で熱処理し、ウエハどうしの接続を完
了する、これを(e)に示す。Next, the wafer 4 serving as the substrate of the SOI substrate and the wafer 5 having both front and back surfaces mirror-finished are H 2
O 2 —H 2 SO 4 was washed, and a hydrophilic treatment was performed to make use of the fact that a hydroxyl group (—OH) is hydrogen-bonded.
Heat treatment is performed at 2 ° C. for 2 hrN 2 to complete the connection between the wafers, which is shown in (e).
【0019】次にSOI基板のサブストレートとなるウ
エハ4にレジスト6を塗布し(f)、表面側をHNO3
−HF−CH3 COOHに少量のI2 を添加剤として加
えたエツチング液を用いて、一部7をエツチングし、所
定の厚さとする、これを(g)に示す。Next, a resist 6 is applied to the wafer 4 which will be the substrate of the SOI substrate (f), and HNO 3 is applied to the front surface side.
Part of 7 is etched to a predetermined thickness using an etching liquid prepared by adding a small amount of I 2 as an additive to —HF—CH 3 COOH. This is shown in (g).
【0020】次にレジスト6を除去し、SOI基板8が
完成する、これを(h)に示す。Next, the resist 6 is removed, and the SOI substrate 8 is completed. This is shown in (h).
【0021】以上の方法でSOI基板を製作することに
より貼り合わせ後のウエハの研磨をエツチング液による
化学的研磨によつてのみ行い、機械的研磨を行う工程が
省略出来るものである。By manufacturing the SOI substrate by the above method, the wafer after bonding can be polished only by chemical polishing with an etching solution, and the step of mechanical polishing can be omitted.
【0022】[0022]
【効果】本発明のSOI基板の製造は、機械研磨工程が
省略されて、工程管理が容易となり、更にエツチング液
による研磨であるので、ウエハ間のエツチング厚さのバ
ラツキが少なく、大量処理が可能となり、使用する装置
も機械的研磨と比較すると簡単な装置でよく、大幅のコ
ストの低減を計ることができる。[Effect] In the manufacture of the SOI substrate of the present invention, the mechanical polishing step is omitted, the process control is easy, and the etching liquid is used for polishing, so that there is little variation in the etching thickness between wafers and a large amount of processing is possible. Therefore, a simpler device can be used as compared with the mechanical polishing, and the cost can be greatly reduced.
【図面の簡単な説明】[Brief description of drawings]
【図1】本実施例の説明図で(a)〜(h)は各工程順
の説明図である。FIG. 1 is an explanatory diagram of the present embodiment, in which (a) to (h) are explanatory diagrams in the order of each step.
【図2】従来例の説明図で、(a)〜(e)は各工程順
の説明図である。FIG. 2 is an explanatory diagram of a conventional example, in which (a) to (e) are explanatory diagrams in the order of steps.
1 シリコンウエハ 2 酸化膜 3 レジスト 7 エツチング部 8 SOIウエハ 9 SOIサブストレートウエハ 10 両面鏡面ウエハ 11 研削部 12 エツチング部 13 研削部 1 Silicon Wafer 2 Oxide Film 3 Resist 7 Etching Part 8 SOI Wafer 9 SOI Substrate Wafer 10 Double Sided Mirror Wafer 11 Grinding Part 12 Etching Part 13 Grinding Part
Claims (1)
として、SOI基板のサブストレートとなるウエハに酸
化膜を形成し、レジスト塗布、酸化膜除去、レジスト除
去を行いサブストレートのウエハを製作し、次に前記サ
ブストレートのウエハと表・裏の両面が鏡面であるウエ
ハを洗浄後親水化処理を行い、水素結合を利用し、熱処
理を行つて、前記ウエハどうしの接合を行い、前記サブ
ストレートのウエハにレジストを塗布し、表面側をエッ
チングして一定の厚さとし、レジストを除去してSOI
基板を製作する半導体装置の製作方法。1. As a method of manufacturing an SOI substrate which is a semiconductor device, an oxide film is formed on a wafer to be a substrate of an SOI substrate, and resist coating, oxide film removal and resist removal are performed to manufacture a substrate wafer. Next, the wafer of the substrate and the wafer whose front and back surfaces are both mirror-finished are subjected to a hydrophilization treatment, and then hydrogen bonding is used to perform a heat treatment to bond the wafers to each other. The wafer is coated with resist, the surface side is etched to a certain thickness, and the resist is removed to remove the SOI.
A method of manufacturing a semiconductor device for manufacturing a substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15792791A JPH0563169A (en) | 1991-06-28 | 1991-06-28 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15792791A JPH0563169A (en) | 1991-06-28 | 1991-06-28 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0563169A true JPH0563169A (en) | 1993-03-12 |
Family
ID=15660516
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15792791A Pending JPH0563169A (en) | 1991-06-28 | 1991-06-28 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0563169A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7020890B1 (en) | 1999-04-05 | 2006-03-28 | Sharp Kabushiki Kaisha | Millimeter wave transmitter, millimeter wave receiver and millimeter wave communication system enabling simplification of wiring and improvement in degree of freedom for setting receiver in receiving system for terrestrial broadcasting and satellite broadcasting |
-
1991
- 1991-06-28 JP JP15792791A patent/JPH0563169A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7020890B1 (en) | 1999-04-05 | 2006-03-28 | Sharp Kabushiki Kaisha | Millimeter wave transmitter, millimeter wave receiver and millimeter wave communication system enabling simplification of wiring and improvement in degree of freedom for setting receiver in receiving system for terrestrial broadcasting and satellite broadcasting |
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