JPH02291596A - Driving method for plasma display panel - Google Patents

Abstract

PURPOSE:To prevent surface discharge in address switching and mislighting due to priming effect from occurring by fixing a scanning voltage for nonselection at a voltage value between the voltage value of applied voltage pulses in an address period and a 0 voltage. CONSTITUTION:A figure shows a pulse voltage waveform (a) applied to N row electrodes, i.e. scanning electrodes, pulse voltage waveforms (b) and (c) applied to (m) column electrodes and (n) column electrodes as data-side electrodes, a pulse voltage waveform (d) applied to cells in (m) columns and N rows, and a pulse voltage waveform (e) applied to cells in N rows and (n) columns. This driving method fixes the voltage of scanning electric power in the nonapplication period of the pulse voltage at the voltage value between the crest value of the pulse voltage in the address period and 0 potential. Consequently, a voltage difference at the time of the transition from the nonselection period to the address period is reducible, so the surface discharge and misillumination due to the priming effect are prevented from being caused.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for driving a plasma display panel (hereinafter referred to as PDP), and particularly relates to a method for driving a plasma display panel (hereinafter referred to as PDP), and in particular, a method for driving a plasma display panel (hereinafter referred to as PDP).
This relates to a method of driving P.

[Prior Art] In general, an AC refresh type FDP is comprised of a scanning electrode group and a data electrode group that are arranged orthogonally facing each other with a dielectric film and a discharge space interposed therebetween. This FDP
In this case, a time-divided pulsed voltage is applied to the scanning electrode group, and a pulsed voltage with the opposite phase to the voltage waveform applied to the scanning electrode group is applied to the data electrode group when lighting is on, and when it is not lighting. It is driven by applying pulse voltages of the same phase (Japanese Patent Publication No. 55-48318).

By the way, the brightness of an AC refresh type FDP is proportional to the number of pulses included in a unit time, so as the number of scanning electrodes increases, the driving frequency required to obtain sufficient brightness increases, which reduces power consumption. The disadvantage was that it increased.

Therefore, in order to solve this drawback, for example, the patent application Sho Gl-
No. 173102 divides the pulse application period to the scanning electrodes (one scanning period) into an address period and a hold period,
A DPD driving method has been proposed in which the frequency of the applied voltage pulse during the address period is lower than the frequency of the applied voltage pulse during the hold period. In this method, when the frequency of the voltage pulse applied to the scanning electrode during the hold period is increased and the pulse applied to the data side electrode is eliminated, the addressed discharge cell maintains its discharge state, and the unaddressed discharge The cell remains in a non-discharged state.

According to this driving method, the number of pulses applied to the data-side electrode is reduced, so power consumption can be reduced, and by increasing the frequency of the hold period, high brightness can also be achieved. are doing.

However, even in the above-described driving method, there is a problem that the driving voltage range becomes narrow when a time lag occurs between the high-frequency pulses applied to the scanning electrode and the data-side electrode during the address period.

This problem will be explained using FIG.

FIG. 3 is a timing chart for explaining the above-mentioned driving method proposed in Japanese Patent Application No. Sho Gl-173102. FIG. 3(a) shows the pulsed voltage applied to the Nth row electrode (scanning electrode), and FIG. 3(b) and (C) show the mth row electrode (scanning electrode).
It shows the pulsed voltages applied to the column electrodes (data side electrodes) and the n-th column electrodes (data side electrodes). Furthermore, a period a during which a low-frequency pulsed voltage is applied to the N-th row electrode is defined as an address period, and a period b during which a high-frequency pulsed voltage is applied is defined as a hold period.

Now, the voltage at which one discharge cell in the PDP discharges is the minimum discharge starting voltage (Vomtn), and the voltage at which all discharge cells in the PDP discharge is the maximum discharge starting voltage (Vo,,.+
−). To drive the cell, a pulsed voltage (Vo) is applied to the row electrode (scanning electrode), and a pulsed voltage (Vo) that is in phase or opposite to the pulsed voltage applied to the row electrode (data side electrode) is applied to the column electrode (data side electrode). This is done by applying V, ). The FDP stops discharging when the condition 1D1n>Vo-VI is satisfied, and starts discharging when the condition VDmlx≦Vo+Vt is satisfied. The pulsed voltage applied to the cell is expressed by the potential difference between the pulsed voltage applied between the row electrode and the column electrode. The waveform is shown in d). Therefore, apply to the cell (N row, m column)? The real voltage VO +V is V. When the condition +VI≧VDffllX is satisfied, (N
(row, column m) the cell is lit, (row N, column n) the voltage V applied to the cell. -v1 is V. If the condition -V+>VD■ is satisfied, the cell (N row, n column) is in a non-lighted state.

Furthermore, as mentioned above, in the address period a of FIG.
(Nth row, m column) Once a cell discharges, due to residual effects such as charged particles and metastable atoms generated by the discharge, the discharge can be maintained at a voltage lower than the cell's discharge starting voltage, and the cells in the panel V Eim the highest sustaining voltage among
*If x, then the voltage Vo applied to the cells (N rows, m columns) during the hold period b is V. If ≧V Smax is satisfied, the cell (N row, m column) connects the discharge.

On the other hand, the cell (N row, n column) has, in the address period a,
Since it is in a non-discharge state, (V
o +V+ ) +V+ = Vo pulse state voltage (
e) is applied, for example V. ≧V Offline
However, since the frequency of the pulsed voltage applied during the hold period b is very high, for example, 2.5 MH2, the cells (N rows, n columns) can be maintained in a non-discharge state due to the discharge delay phenomenon. .

By the way, the pulse waveforms (b) and (C) applied to the m-th column electrode and the n-th column electrode are not the output waveforms of the drive circuit, but show the pulse voltage waveforms applied to the column electrodes of the actual cell. . That is, a transparent electrode with a sheet resistance of about 8 Ω/gate is normally used as the data side electrode (column electrode), and the pulse voltage waveform on the transparent electrode is distorted due to the resistance of this transparent electrode and the interelectrode capacitance. For example, in a PDP with 640x400 cells and a cell pitch of 0.36mm, the resistance of the transparent electrode is about 8KΩ, the interelectrode capacitance is about 30PF, and when the driving frequency exceeds 700KHz, as shown in Figure 3(b). As shown in (c), waveform distortion becomes a problem.

For example, in address period a in FIG. 3, (N rows, m
Column) cells are V as shown in (d). A pulse voltage of +V is applied to enter the selected state.

On the other hand (N row, n column), the ideal voltage is V. A pulse voltage of 1V1 is applied, and the cell is in a non-lighting state, but in reality, due to distortion of the pulse voltage applied to the n-column electrode, a voltage with a peak-like pulse as shown in (e) is generated. applied. Due to the presence of this peak-like pulse, (
(N row, n column) cell will cause false lighting, so the actual V.

The value has to be set to a value considerably lower than the theoretical value, which has the disadvantage that the driving voltage range becomes narrow.

Therefore, in order to solve the above-mentioned problems, the present applicant set the pulse voltage value in the address period lower than the pulse voltage value in the hold period in the driving method described above, thereby increasing the driving voltage range of the FDP. proposed that it could be expanded. This driving method is shown in FIG.

As shown in FIG. 4, according to this driving method, the pulse voltage applied to the cell when not selected [see FIG. Figure 3 (
e)], the range of driving voltages can be expanded compared to the conventional method.

[Problems to be Solved by the Invention] However, the above-described conventional PDP also has the following problems. That is, the scanning electrode pitch is 0.3
As high-resolution PDPs began to be developed, surface discharge occurred between these scan electrodes when scanning was transferred from the Nth scan electrode to the (N+1)th scan electrode, resulting in non-lighting. There was a problem that the cell would be erroneously lit. In addition, due to the briming effect of charged particles, etc., the pulse voltage applied to the non-selected cell [Fig. Discharge may be generated due to voltage changes, which may cause false lighting.

The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide a method for driving a plasma display panel that has a wide driving voltage range and less occurrence of erroneous lighting.

[Means for Solving the Problems] A method for driving a plasma display panel according to the present invention divides the application period of a pulse voltage to each scanning electrode into an address period and a hold period, and the address period is longer than the hold period. In a plasma display panel driving method in which a pulse voltage of low frequency and low amplitude is applied, the voltage of the scanning power during the non-application period of the pulse voltage is set to a value between the waveform value of the pulse voltage during the address period and the O potential. It is characterized by being fixed at a voltage value.

[Function] According to the present invention, the pulse application period to each scan electrode is divided into an address period and a hold period, and a pulse voltage having a lower frequency and lower amplitude is applied in the address period than in the hold period. It is possible to prevent false lighting by reducing power consumption and suppressing peak noise. In addition, the voltage during the non-selection period of the scanning electrode is determined from the peak value of the pulse voltage during the address period of the pulse voltage during the address period.
7I! By fixing the voltage to a value between 1 and 2, it is possible to reduce the voltage difference when moving from the non-selection period to the address period, thereby preventing the occurrence of discharge and erroneous lighting due to the lining effect.

[Embodiments] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a waveform diagram for explaining the FDP driving method according to the first embodiment of the present invention, and FIG. 1(a) shows the pulse voltage waveform applied to the N row electrode (scanning electrode); Figure (b)
and (C) are pulse voltage waveforms applied to the m column electrode (data side electrode) and n column electrode (data side electrode), respectively, and (d) of the same figure is the pulse applied to the (N row, m column) cell. Voltage waveform (e) in the figure is a pulse voltage waveform applied to the cells (N rows, n columns).

In this driving method, the pulse voltage (a) applied to the scanning side electrode is divided into an address period a and a hold period b, and the amplitude VO2 of the address period a is equal to the amplitude ■ of the hold period b. Is the frequency of the pulse voltage in address period a smaller than i and in the hold period? is set lower than the frequency of the pulse voltage. The pulse frequency of the hold period b is selected to a frequency that does not cause cell discharge. Also,
The scanning side electrode has a voltage of V during a period in which no pulse voltage is applied. It is fixed at 2.

On the other hand, when the data side electrode is turned on,
), a pulse in phase with the pulse voltage (a) is applied only during the address period a, and when the light is not lit, an O voltage is applied as shown in (C) of the figure.

Now, the voltage at which one discharge cell in the PDP discharges is the minimum discharge starting voltage (VD,...l1), and the voltage at which all discharge cells in the PDP discharge is the maximum discharge starting voltage (V o■
X), the voltage applied to the cell (N row, m column) is as shown in Figure 1 (d), and if the following conditions are satisfied, the cell (N row, m column) is Discharge.

V o2+ V s≧ VD■8 ・・・・・・
(1) Also, if the following conditions are satisfied, does discharge once start in address period a (N row, m column)? The battery maintains discharge even during the hold period b.

Vo+≧V S. ．． ．． ...-
(2>Here, ■9■8 is the highest sustaining voltage among all cells of the panel.

On the other hand, the voltage applied to the cell (N row, n column) is shown in Figure 1 (
As shown in e), if the following conditions are satisfied,
(N row, n column) The cell does not generate a discharge in the address period a.

V o2≧V D -t-..."
・(3) In the method of this embodiment, the address period a
The potential change at the beginning of is ■. 2, and the conventional change V. I
smaller than Therefore, even with such potential changes, the cells (N rows, n columns) will not be erroneously illuminated. Also N
When scanning moves from the (N+1)th scanning electrode to the (N+1)th scanning electrode, the potential change between the scanning electrodes is (V 02+
V 02), and in the conventional case (V ot +
(2 VO2) < (2
Since the relationship (Vot) is established, it is also possible to prevent erroneous lighting due to surface discharge between the scanning electrodes.

Further, during the hold period b, the pulse voltage value V. 1
■. Even if it is set to a value higher than the n+In value, the frequency of the hold voltage pulse during the hold period b is high, so
Due to the discharge leakage phenomenon, the cell (CN row, n column) can maintain a non-discharged state, just as in the conventional case.

Incidentally, the present inventor applied the driving method of this embodiment,
When a plasma display panel having 640×400 cells was driven, the following characteristics were obtained.

Note that here, the frequency in address period a is set to 70
0KH. , the frequency in hold period b is 2.5MH
z, v. = eov.

As a result, we were able to obtain stable operation within the following boxes.

160v≦VOI≦180v and 140v≦VO2<160V FIG. 2 is a waveform diagram for explaining the FDP driving method according to the second embodiment of the present invention, and FIG. Pulse voltage waveform applied to the electrode), same figure (b)
and (c) are the pulse voltage waveforms applied to the m-column electrode (data side electrode) and n-column electrode (data side electrode), respectively, (d) is the pulse voltage waveform applied to the cell, and (e) is the pulse voltage waveform applied to the cell. )
(N rows, n columns) indicate pulse voltage waveforms applied to the cells, respectively.

That is, in this embodiment, as shown in FIG. 2(a), the potential of the scanning side electrode is fixed at 0 potential during a period when no pulse voltage is applied.

Other driving methods are the same as those in the embodiment shown in FIG.

In this embodiment method, as in the case of the first embodiment described above, if the following conditions are satisfied in the voltage waveform (d) applied to the cell (N rows, m columns), (N
row, column m) the cell discharges.

VO2 + V1 ≧Vnmax ++
*e* (4) Furthermore, if the following conditions are satisfied, the cells (N rows, m columns) that once started discharging in the address period a continue discharging in the hold period b.

Vos≧Vs. ,,． X. ．． ．． ．． ．． ．． (5) On the other hand, if the voltage waveform (e) applied to the (N row, n column) cell satisfies the following conditions, the (N row, n column) cell will not generate a discharge in the address period a. .

V02<VDmIn...
...(6) Also, in the hold period b, Vol.
Even if V DmIn is set to a value higher than V DmIn, the frequency of the hold voltage pulse in hold period b is as high as, for example, 2.5 MHz, so the cell (N row, n column) maintains a non-discharge state due to the discharge delay phenomenon. be able to.

Furthermore, in this second embodiment as well, the potential change at the beginning of the address period a is V. 2, and even with this potential change, the cells (N rows, n columns) will not be erroneously illuminated. Also,
Even when scanning moves from the Nth scanning electrode to the (N+1)th scanning electrode, the potential change between the scanning electrodes is (V oI+
V 02), and in the conventional case (V o+ +
V o+), (V oI + V 02) < (2
Since the relationship VQ1) is established, it is also possible to prevent erroneous lighting due to surface discharge between the scanning electrodes.

Note that the present invention is not limited to the embodiments described above. For example, the applied voltage when the scanning side electrode is not selected is V. 2～
It may be fixed to any value within the range of 0.

[Effects of the Invention] As explained above, the present invention divides the pulse period applied to the scan electrode into an address period and a hold period, and sets the voltage value and frequency in the address period lower than those in the hold period. In this driving method, the scanning voltage during non-selection is changed from the voltage value of the applied voltage pulse during the address period to 0.
Since the voltage value is fixed between the voltages, it is possible to prevent the occurrence of erroneous lighting due to surface discharge and priming effect during address switching, and it has the effect that the drive voltage range can be expanded.

[Brief explanation of the drawing]

FIG. 1 is a voltage waveform diagram for explaining the FDP driving method according to the first embodiment of the present invention, and FIG. 2 is a voltage waveform diagram for explaining the FDP driving method according to the second embodiment of the present invention. 3 and 4 are voltage waveform diagrams for explaining conventional FDP driving methods, respectively.

Claims (1)

[Claims] (1) Driving a plasma display panel in which the period during which a pulse voltage is applied to each scanning electrode is divided into an address period and a hold period, and a pulse voltage with a lower frequency and lower amplitude is applied in the address period than in the hold period. A method for driving a plasma display panel, characterized in that the voltage of the scanning power during the non-application period of the pulse voltage is fixed to a voltage value between the peak value of the pulse voltage during the address period and 0 potential.