JPH02291142A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To accurately control a size and to universally use a plurality of processes for a plurality of products by using check patterns in which lengths of sides of unit patterns along a direction in which the unit patterns have been arranged are changed one after another in an arrangement direction. CONSTITUTION:A rectangular pattern row 1 is constituted of six rectangular unit patterns A1 to A6 which have been arranged in a row in a prescribed direction. Lengths of sides, in a prescribed direction, of the individual unit patterns A1 to A6 are set to 0.5, 0.6, 0.7, 0.8, 0.9 and 1.0mum, respectively; an interval between the individual unit patterns is made definite at 20mum. A length of sides of the unit patterns A1 to A6 in a direction perpendicular to the prescribed direction is made definite at 1mum or lower. The check patterns are formed as resist patterns on a wafer; the rectangular patterns A1 to A6 are formed as circles A1' to A6' whose area is nearly equal.

Description

Detailed Description of the Invention [Field of Application in Industry-12] The present invention relates to a method for manufacturing a semiconductor integrated circuit device, which includes a lithography process in which the state of a resist film pattern for element formation is monitored using a resist film pattern for checking. .

[Prior Art] For example, in the step-by-step lithography process for forming polycrystalline silicon gate electrodes, polycrystalline silicon is deposited on the entire surface of the gate insulation film and the field insulation film provided on one side of the semiconductor substrate. A silicon film is deposited, a positive type resist film is applied thereon, the resist film is subjected to reduction projection exposure, etc., and then developed to obtain a predetermined resist 1 pattern.

Then, by selectively etching and removing the polycrystalline silicon film using this resist pattern as a mask, a predetermined pattern of gate 1 electrodes and a polycrystalline silicon wiring layer is obtained. In this case, by checking the shape of these electrodes and wiring layers after ethoching is completed, even if a shape defect caused by the resist pattern used as a mask is discovered, rework is no longer possible. . Therefore,
Before performing the etching process, it is necessary to check whether a predetermined resist pattern has been obtained after developing the resist. If exposure is performed using the correct mask and under the correct conditions, a predetermined resist pattern should be obtained.

However, due to factors such as fluctuations in resist coating conditions, reduction projection exposure conditions, development conditions, etc., or setting errors,
Patterns may become connected, or the patterns may collapse, making it impossible to obtain the desired shape and desired dimensions. In order to check this phenomenon, it is necessary to form a check pattern with the same width and spacing as the pattern in the element formation area, and to confirm that the predetermined dimensions are maintained in the check pattern. Bye. This can be done visually. If any inconvenience is found in this check pattern, the entire resist film is removed and the resist coating, exposure, and development steps are performed again, thereby making it possible to redo the work.

As a pattern for conventional technology, for example (Japanese Patent Application Laid-Open No. 5Ei
162834), there is a resist in which the width of the unit patterns and the interval between the unit patterns are equal. Furthermore, the technique described in JP-A No. 63-GG934 uses a pattern with a constant interval, but by increasing the width of the resist band on both sides of the interval, it is possible to monitor more precisely. That is.

[Problem to be Solved by the Invention] However, when the above-mentioned conventional check pattern is used, there is a drawback that it is necessary to prepare a vast area on the semiconductor wafer or semiconductor pellet in order to form the check pattern. There is.

In this case, if the process that requires particularly precise control of the dimensions of a resist pattern for forming elements on a semiconductor wafer or semiconductor chip is a limited number of processes such as a gate electrode forming process, No major problems arise even if the above-mentioned chip patterns having relatively large areas are used.

However, in the lithography process of semiconductor integrated circuit devices where the minimum design dimension is less than 0.8 μm, precise control of the dimensions of resist patterns for element formation is required throughout almost the entire process. come. Therefore, it is necessary to provide a large area on the wafer or pellet for forming the check pattern.

In addition, although the degree of integration is improving, the size of semiconductor pellets cannot be increased due to package limitations, so the area for check patterns on semiconductor pellets, which was previously available, has to be reduced. There is no situation. This makes it extremely difficult to control package dimensions throughout the entire process using conventional check patterns.

On the other hand, each lithography condition includes a considerable amount of fluctuation, and even if it appears from the outside that the same conditions are always maintained, these same conditions are not necessarily reproduced. For example, fluctuations in mask dimensions (even masks of the same type and process are slightly different in size), resist film thickness fluctuations, reduction magnification fluctuations, focus fluctuations, exposure amount fluctuations, or development temperature fluctuations. When attempting precise dimensional control, various instabilities become a problem. In order to maintain stable dimensions under such circumstances, it is preferable to constantly monitor all processes of pattern formation and maintain and manage the entire production line at a certain level.

However, as described above, since the conventional check pattern has a relatively large area, it is extremely difficult to form the check pattern on the semiconductor wafer in each step.

The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide a method for manufacturing a semiconductor integrated circuit device, in which even if a check pattern is applied to each step, the formation area can be kept small, and dimensions can be precisely controlled.

[Means for Solving the Problems] A method for manufacturing a semiconductor integrated circuit device according to the present invention includes simultaneously patterning an element formation pattern and a check pattern for monitoring the element formation pattern on a resist film, or performing a lithography process. In the method of manufacturing a raw conductor integrated circuit device, the check pattern includes three or more rectangular unit patterns arranged in a predetermined direction with a predetermined interval between them, and the unit pattern is arranged in the predetermined direction. The length of the side along the direction changes sequentially toward the predetermined direction, and the length of the side in the direction perpendicular to the predetermined direction is a constant value of 1 μm or less.

[Function] In the present invention, since the length of the side of the unit pattern along the direction in which the unit pattern is arranged changes sequentially in the arrangement direction, by using this check pattern, precise dimensional control is possible. It can be used universally in multiple processes for multiple products.

[Embodiments] Next, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1(a) is a plan view showing a check pattern (at the time of design) used in the embodiment method of the present invention, and FIG. FIG. 3 is a plan view showing a resist pattern.

The dimensions shown in FIG. 1(a) are the dimensions at the time of design.

The rectangular pattern row 1 is composed of six rectangular unit patterns A1 to 80 arranged in a line in a predetermined direction. Each unit pattern A1 to A6 has a side length in the predetermined direction of 0.5/lm, 0.6 μm, 0.7 μm, respectively.
0.8 μm, 0.9 μm, 1.0 μm,
The interval between each unit pattern is constant at 2.0 μm. Further, the length of the sides of the unit patterns A1 to A6 in the direction perpendicular to the predetermined direction is constant at 0.6 μm.

When this check pattern is formed as a renos 1 pattern on a wafer, as shown in FIG. become.

In FIG. 1(b), under certain lithography conditions, pattern 2 (A,', A2') is not resolved and pattern 3 (A3
' to 80') obscures the resolution.

FIG. 2(a) shows a cross-sectional view when the pattern is formed by leaving the resist (so-called left pattern). As shown in FIG. 2, an insulating film 5 is formed on a silicon substrate 4, a conductive film 6 is formed on the insulating film 5, and resist films 7 and 8 are formed on the conductive film 6 in a pattern. It is formed.

The resist film 8 of the resolved pattern 3 has a rectangular cross section, but the resist film 7 of the unresolved pattern 2 has a lower height than the resist film 8 and has rounded edges. .

FIG. 2(b) shows a cross-sectional view when the pattern is formed by removing the resist (so-called punched pattern). The resist film 10 of the resolved pattern 3 is completely separated, but the resist 1. remains between the resist films 9 of the unresolved pattern 2.

In either case, it is possible to identify the unresolved pattern 2 by observing the resist patterns 2 and 3.
It can be seen that patterns up to the length of pattern A3) can be resolved.

FIG. 3 is a plan view showing a second embodiment of the invention.

Rectangular pattern B I1 to Bee in an array of 6 rows x 6 columns
are arranged. For the first to sixth rows, the length of each side in the column direction (direction of arrow 12) is 0.5μ.
m, o. eμ111, 0.7μm10.8μm10.
9 μm and 1.0 μm, and this length is constant for each row.

In addition, for the first to sixth columns, the length of the side along the husband's Z row direction (arrow 11 direction) is 0.5 μm and 10.6 μm.
m, 0.7 μm, 0.8 μm, o. aμm and 1.0
μm, and this length is constant for each row.

At this time, under the lithography conditions as shown in FIG. 1, the pattern B Il+ B 12+ B 13+
6 in the upper left, like B 21 + B22 + B31
One pattern is not resolved, and the other patterns are resolved.

Since these are arranged flat, they are easy to recognize and visual check is extremely easy.

? FIG. 4 is a plan view showing a third embodiment of the present invention. In this embodiment, the pattern is a so-called cutout pattern formed by removing rectangular unit patterns C I1 to CCE or Lens}. The rectangular patterns C I1 to CGG are arranged in an array of 6 rows and 6 columns.

The sizes of each of the 1a-place patterns CI1 to cee are the same as the unit patterns B11 to Bee in FIG.

For example, in the lithography process for forming the polycrystalline silicon gate electrode 1, the rectangular unit pattern used as the check pattern is usually a pattern formed by leaving the resist 1 (remaining pattern). It is. In this case, as shown in FIG. 2(a), the unresolved rectangle can be identified because it is as low as the height of the ratio 1.

However, in the subsequent etching process, the polycrystalline silicon film is inevitably etched using a fine circular resist pattern as a mask, as shown in Figure 5.
Resist 7 of unresolved pattern 2! II M1
1 3 and peeling of conductive film 6 such as polycrystalline Noricon film i1i
11I14 etc. are likely to occur and become a factor that reduces the manufacturing yield of semiconductor integrated circuit devices.

On the other hand, as shown in FIG. 3, even in the lithography process of polycrystalline silicon, a check pattern formed by a pattern (blank pattern) formed by removing the trace 1 is removed. This can prevent pattern peeling and improve manufacturing yield.

Furthermore, it is possible to use the same pattern in a plurality of steps, such as in the lithography process for the contact 1 and the hole opening.

At this time, it is important to be able to use the same judgment criteria when visually inspecting check patterns even if the processes are different, which greatly contributes to improving work efficiency.

In addition, advances in lithography technology have reduced the current resolution limit to 0. When it becomes possible to form holes in patterns even smaller than G tlm x 0.7 μm, we will reach the next level of 0.7 μm. Gu m X O. It is sufficient to pour into a G u m N or 0.5 μm×0.6 μm, and the same pattern can be used beyond the limits of technology.

As explained in "Effects of the Invention" 2, the present invention allows the same existing check pattern to be used universally in multiple processes for multiple products, so that it can be used constantly within the manufacturing line. This makes it possible to check lithography conditions using the same pattern, and has the effect of stabilizing lithography conditions and, by extension, stabilizing the quality of manufactured products.

[Brief explanation of drawings]

FIG. 1 (aL (b) is a plan view showing the first embodiment of the present invention, FIGS. 2 (a) and (b) are longitudinal sectional views thereof,
FIG. 3 is a plan view showing the second embodiment of the present invention, FIG. 4 is a plan view showing the third embodiment of the invention, FIG. 5 is a vertical sectional view showing a defective example, and FIG. It is a longitudinal cross-sectional view showing an improved example.

Claims (1)

[Claims] (1) In a method for manufacturing a semiconductor integrated circuit device including a lithography process in which a resist film is simultaneously patterned with an element formation pattern and a check pattern for monitoring the element formation pattern, the check pattern has three or more rectangular patterns. unit patterns are arranged in a predetermined direction with predetermined intervals between them, and the unit patterns have a side length along the predetermined direction that sequentially changes toward the predetermined direction, A method for manufacturing a semiconductor integrated circuit device, characterized in that the length of a side in a direction perpendicular to the predetermined direction is a constant value of 1 μm or less.