JPH02291129A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH02291129A JPH02291129A JP11152789A JP11152789A JPH02291129A JP H02291129 A JPH02291129 A JP H02291129A JP 11152789 A JP11152789 A JP 11152789A JP 11152789 A JP11152789 A JP 11152789A JP H02291129 A JPH02291129 A JP H02291129A
- Authority
- JP
- Japan
- Prior art keywords
- film
- siloxane polymer
- organic siloxane
- wiring part
- inorganic insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- KPUWHANPEXNPJT-UHFFFAOYSA-N disiloxane Chemical class [SiH3]O[SiH3] KPUWHANPEXNPJT-UHFFFAOYSA-N 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 239000002184 metal Substances 0.000 claims abstract description 4
- 238000002161 passivation Methods 0.000 claims description 13
- 229920006254 polymer film Polymers 0.000 claims 2
- 229920000642 polymer Polymers 0.000 abstract description 13
- 239000010410 layer Substances 0.000 abstract description 11
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 4
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 3
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 abstract description 2
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 239000002344 surface layer Substances 0.000 abstract description 2
- 230000000694 effects Effects 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 238000002474 experimental method Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 125000005375 organosiloxane group Chemical group 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Landscapes
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に、配線のエレクトロマ
イグレーション耐性、および、耐湿性に強い半導体装置
に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a semiconductor device, and more particularly to a semiconductor device that has strong wiring electromigration resistance and moisture resistance.
従来半導体装置のパッシベーション膜はプラズマCVD
法により成長したシリコン窒化膜(以下P−SiNと表
す)単層、あるいは第3図に示すように、PSG膜34
上にP−SiN35を形成した2層構造などであった。Conventional passivation films for semiconductor devices are made using plasma CVD.
A single layer of silicon nitride film (hereinafter referred to as P-SiN) grown by the method, or a PSG film 34 as shown in
It had a two-layer structure with P-SiN35 formed thereon.
上述した従来のパッシベーション膜ではCVD膜の性質
として配線段差側部の膜厚が薄くなったり膜質が脆くな
ったりずる。これは配線間隔が微細になるにつれさらに
顕著となる現象である。すなわちCVD法とは化学気相
反応のことであり、配線間隔が微細になると新鮮な反応
ガスが供給されにくくなるためである。In the conventional passivation film described above, due to the characteristics of the CVD film, the thickness of the film on the side of the wiring step becomes thinner and the film quality becomes brittle. This phenomenon becomes more noticeable as the wiring spacing becomes finer. That is, the CVD method is a chemical vapor phase reaction, and as the wiring spacing becomes fine, it becomes difficult to supply fresh reaction gas.
このためにどのようなことが起こるかというとまず、パ
ッシベーション膜の本来の目的である耐湿性が低下する
。また、パッシベーション膜の下を走る配線のエレクト
ロマイグレーション耐性が低下する。これを詳しく説明
すると、電流が流れると配線内に圧縮応力が発生する。What happens because of this is that the moisture resistance, which is the original purpose of the passivation film, deteriorates. Furthermore, the electromigration resistance of the wiring running under the passivation film is reduced. To explain this in detail, when a current flows, compressive stress is generated within the wiring.
この応力にパッシベーション膜が耐えられなくなるとク
ラックが発生し、配線のふくれやウィスカーが発生し、
エレクト四マイグレーションが加速される。この時の応
力の最大値はほぼ1 0 10dyne/ ct程度と
概算される。この程度の応力は本来CVD膜が耐えられ
る値であるが、配線側部で膜質が劣化しているため、こ
れに耐えきれなくなっている。When the passivation film can no longer withstand this stress, cracks occur, causing bulges and whiskers in the wiring.
Elect4 migration will be accelerated. The maximum value of stress at this time is estimated to be approximately 1010 dyne/ct. This level of stress is originally a value that the CVD film can withstand, but because the film quality has deteriorated on the wiring side, it is no longer able to withstand this stress.
本発明によれば、半導体基板上に形成した最上層の金属
配線を覆って形成されたパッシベーション膜が下から順
に、無機絶縁膜,有機シロキサンボリマー、無機絶縁膜
である半導体装置を得る。According to the present invention, a semiconductor device is obtained in which the passivation film formed covering the uppermost layer of metal wiring formed on the semiconductor substrate is an inorganic insulating film, an organic siloxane polymer, and an inorganic insulating film in order from the bottom.
次に木発明について図面を参照して説明する。 Next, the wooden invention will be explained with reference to the drawings.
第1図は本発明の一実施例の縦断面図である。FIG. 1 is a longitudinal sectional view of an embodiment of the present invention.
ここで、素子部、および、最上層配線よりも下層の配線
,層間膜等は省略してある。高さ1.0μmのAA配線
13」二にPSG膜14を常圧CVDにより0.2μm
〜0.5μm成長し特開昭63−266519に示され
た方法により有機シロキサンポリマー層15を形成する
。すなわち、有機シロキサンポリマーのアルコール溶液
を回転塗布し02プラズマにより表面層の酸化を行い、
その後400’C 3 0分の熱処理を行う。膜厚は平
坦部で0. 2μm〜0.5μmとした。次にプラズマ
CVDによりシリコン窒化膜16を0.3μm成長する
。こうして得られたパッシベーション膜のエレクトロマ
イグレーション抑制効果を調べるために、以下の実験を
行った。Here, the element portion, wiring in layers lower than the top layer wiring, interlayer films, etc. are omitted. AA wiring 13" with a height of 1.0 μm and a PSG film 14 of 0.2 μm by atmospheric pressure CVD.
The organic siloxane polymer layer 15 is grown to a thickness of 0.5 .mu.m by the method disclosed in JP-A No. 63-266519. That is, an alcohol solution of an organic siloxane polymer is spin-coated and the surface layer is oxidized by 02 plasma.
Thereafter, heat treatment is performed at 400'C for 30 minutes. The film thickness is 0. The thickness was 2 μm to 0.5 μm. Next, a silicon nitride film 16 is grown to a thickness of 0.3 μm by plasma CVD. In order to investigate the electromigration suppressing effect of the passivation film thus obtained, the following experiment was conducted.
シリコン酸化膜上に高さ1. 0μm,幅8.0μm,
長さ500μmのAj2配線を形成し、その上に上記の
パッシベーション構造を形成した。これを(A)とする
。比較のために(A)の構造で有機シロキサンポリマー
の代わりに無機SOG(商品名OCD−Type2)0
.1μmを用いた水準(B),中間層の無い水準すなわ
ちP−SiN/PSG(C)も作成した。セラミックパ
ッケージに組立て、200℃,電流密度2.OX106
A/ cntの条件でエレク}・ロマイダレーション試
験を行った。平均故障時間は(A)約1000時間、(
B)約180時間、(C)約150時間であり木発明の
効果がわかる。A height of 1. 0μm, width 8.0μm,
An Aj2 wiring having a length of 500 μm was formed, and the above passivation structure was formed thereon. This is called (A). For comparison, inorganic SOG (trade name OCD-Type 2) was used instead of the organic siloxane polymer in the structure of (A).
.. A level using 1 μm (B) and a level without an intermediate layer, that is, P-SiN/PSG (C) were also created. Assembled in ceramic package, 200℃, current density 2. OX106
An electromagnetization test was conducted under the conditions of A/cnt. The average failure time is (A) approximately 1000 hours, (
B) about 180 hours, (C) about 150 hours, which shows the effect of the wooden invention.
パッシベーション膜の耐湿性を調べるために以下の実験
を行ったリン濃度10mol%のPSG膜上に幅/間隔
−1. 0 / 1. 0μmのAfl配線が数10本
平行に走るパターンの上に上述したパッシベーション膜
構造を形成し、モールドパッケージに組立てた。125
℃23気圧, H20 1 0 0%の条件でPCT試
験を行った。30時間後の断線不良発生チップ数は(A
)0ケ/20ケ (B)2ケ/20ケ (C)20ケ/
20ケ だった。In order to investigate the moisture resistance of the passivation film, the following experiment was conducted on a PSG film with a phosphorus concentration of 10 mol%. 0/1. The above-mentioned passivation film structure was formed on a pattern in which several tens of 0 μm Afl wirings ran in parallel, and a molded package was assembled. 125
The PCT test was carried out under the conditions of 23 atm of °C and 100% of H20. The number of chips with disconnection defects after 30 hours is (A
)0 pcs/20 pcs (B) 2 pcs/20 pcs (C) 20 pcs/
It was 20.
この結果により、本発明におけるパッシベション膜が耐
湿性においても効果が大きいことがわかる。This result shows that the passivation film of the present invention is highly effective in terms of moisture resistance.
第2図は本発明の他の実施例の縦断面図である。FIG. 2 is a longitudinal sectional view of another embodiment of the invention.
ここではプラズマCVD法により0.2μm〜10μm
形成したSiON膜(24)j二に有機シロキサンポリ
マー層(25)を塗布一焼成法により平坦部膜厚0.2
μ〜05μに形成した。この実施例では、SiON膜2
4の耐湿性が優れているため、有機シロキサンボリマー
層25上に無機絶縁膜を形成する必要がなく、工程数を
短縮することができる。Here, 0.2 μm to 10 μm is obtained by plasma CVD method.
An organic siloxane polymer layer (25) is applied to the formed SiON film (24) and then baked to a flat part thickness of 0.2
It was formed to a thickness of μ to 05μ. In this example, the SiON film 2
Since No. 4 has excellent moisture resistance, there is no need to form an inorganic insulating film on the organic siloxane polymer layer 25, and the number of steps can be reduced.
以上説明したように本発明は、有機シロキサンポリマー
によりCVD膜が本来持つ段差側面部の脆弱さが補強さ
れるので耐湿性および配線のエレクトロマイダレーショ
ン耐性の非常に優れた半導体装置が実現できる。特にエ
レクトロマイグレーション耐性の向上は、無機SOGに
よる「平滑化」では不充分で、有機シロキサンポリマー
による「平坦化」により初めて実現できる。As explained above, in the present invention, the weakness inherent in the stepped side surfaces of the CVD film is reinforced by the organic siloxane polymer, so that it is possible to realize a semiconductor device with extremely excellent moisture resistance and wiring electromida- tion resistance. In particular, improvement in electromigration resistance can only be achieved by "flattening" using an organic siloxane polymer, since "smoothing" using inorganic SOG is insufficient.
第1図は本発明の一実施例の半導体装置の縦断面図、第
2図は本発明の他の実施例を表す縦断面図、第3図は従
来の半導体装置の問題点を説明するための縦断面図であ
る。
11,21.31・・・・・・半導体基板、12,22
,32・・・・・絶縁膜、13,23.33・・・・・
A.C配線、よ
14,34・・・・・・PSG膜、15.25・・・・
・有機シロキサンポリマー層、16.35・・・・・シ
リコン窒化膜、36・・・・・・腐食、37・・・・・
・クラック、24・・・・SiON膜。
代理人 弁理士 内 原 晋FIG. 1 is a vertical sectional view of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a vertical sectional view showing another embodiment of the present invention, and FIG. 3 is for explaining problems of a conventional semiconductor device. FIG. 11,21.31...Semiconductor substrate, 12,22
, 32... Insulating film, 13, 23. 33...
A. C wiring, 14,34...PSG film, 15.25...
・Organosiloxane polymer layer, 16.35...Silicon nitride film, 36...Corrosion, 37...
・Crack, 24...SiON film. Agent Patent Attorney Susumu Uchihara
Claims (1)
て形成されたパッシベーション膜が、下から順に無機絶
縁膜、有機シロキサンポリマー膜、無機絶縁膜であるこ
とを特徴とする半導体装置(2)半導体基板上に形成し
た最上層の金属配線を覆って形成されたパッシベーショ
ン膜が下から順に無機絶縁膜、有機シロキサンポリマー
膜であることを特徴とする半導体装置(1) A semiconductor device characterized in that the passivation film formed covering the uppermost layer of metal wiring formed on the semiconductor substrate is an inorganic insulating film, an organic siloxane polymer film, and an inorganic insulating film in order from the bottom (2). ) A semiconductor device characterized in that the passivation film formed covering the uppermost layer of metal wiring formed on the semiconductor substrate is an inorganic insulating film and an organic siloxane polymer film in order from the bottom.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11152789A JPH02291129A (en) | 1989-04-28 | 1989-04-28 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11152789A JPH02291129A (en) | 1989-04-28 | 1989-04-28 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02291129A true JPH02291129A (en) | 1990-11-30 |
Family
ID=14563595
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11152789A Pending JPH02291129A (en) | 1989-04-28 | 1989-04-28 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02291129A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5942802A (en) * | 1995-10-09 | 1999-08-24 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method of producing the same |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57111030A (en) * | 1980-12-27 | 1982-07-10 | Fujitsu Ltd | Passivation film |
JPS5948929A (en) * | 1982-08-13 | 1984-03-21 | ウエスタ−ン・エレクトリツク・カムパニ−・インコ−ポレ−テツド | Semiconductor device |
JPS6239025A (en) * | 1985-08-14 | 1987-02-20 | Fujitsu Ltd | Manufacture of semiconductor device |
JPS6325929A (en) * | 1986-07-17 | 1988-02-03 | Nec Corp | Semiconductor integrated circuit |
JPS63137433A (en) * | 1986-11-28 | 1988-06-09 | Fujitsu Ltd | Manufacture of semiconductor device |
JPS6450533A (en) * | 1987-08-21 | 1989-02-27 | Showa Denko Kk | Wiring board |
-
1989
- 1989-04-28 JP JP11152789A patent/JPH02291129A/en active Pending
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57111030A (en) * | 1980-12-27 | 1982-07-10 | Fujitsu Ltd | Passivation film |
JPS5948929A (en) * | 1982-08-13 | 1984-03-21 | ウエスタ−ン・エレクトリツク・カムパニ−・インコ−ポレ−テツド | Semiconductor device |
JPS6239025A (en) * | 1985-08-14 | 1987-02-20 | Fujitsu Ltd | Manufacture of semiconductor device |
JPS6325929A (en) * | 1986-07-17 | 1988-02-03 | Nec Corp | Semiconductor integrated circuit |
JPS63137433A (en) * | 1986-11-28 | 1988-06-09 | Fujitsu Ltd | Manufacture of semiconductor device |
JPS6450533A (en) * | 1987-08-21 | 1989-02-27 | Showa Denko Kk | Wiring board |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5942802A (en) * | 1995-10-09 | 1999-08-24 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method of producing the same |
US6200912B1 (en) | 1995-10-09 | 2001-03-13 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method of producing the same |
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