JPH02290328A - Output buffer circuit - Google Patents

Abstract

PURPOSE:To evade a rapid change in an output buffer, to reduce noise and to prevent malfunction by connecting plural unit buffers in parallel, and controlling the active state of part of them with an external control signal. CONSTITUTION:When input signals S1-S3 change to an L level, a couple of inverters comprising FETs Q1, Q2 and Q4, Q5 change to logical H, a main buffer 10 is driven at a high speed and the output state of buffers Q1-Q3 changes simultaneously. When the signals S1-S4 change to logical L entirely simultaneously, a signal CS of a NOR gate G5 changes to logical H, a FET Q3 is turned off and the inverter comprising the TRs Q4, Q5 is inactivated and finally the main buffer 10 is driven only with the TRs Q1, Q2. Thus, the level of the gate of the FETs Q6, Q7 changes slowly from L to H to prevent production of noise, thereby evading malfunction.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an output puff 1 circuit in a semiconductor integrated circuit.

[Conventional Technology] Conventionally, as shown in FIG.
3 and a main buffer circuit 24 which has a large driving ability to drive the load connected to the output terminal 22. The pre-buffer circuit 23 has a driving ability capable of rapidly charging and discharging the input capacitance of the main buffer circuit 24, and has a P-channel MOS transistor Q18.
and an N-channel MOS transistor Q17 are connected in a complementary pair. In addition, the main buffer circuit 24 is a P-channel MOS transistor Q18 with large driving capacity.
and an N-channel MOS transistor Q19 are connected in a complementary pair.

[Problem to be Solved by the Invention] A large number of the above-mentioned output buffer circuits are often provided in a conductor integrated circuit. However, when a large number of output buffer circuits with large driving capabilities operate simultaneously, a large current momentarily flows through the power supply line, generating noise and causing malfunctions of the peripheral circuitry and the integrated circuit itself.

The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide an output buffer circuit that can reduce noise when a large number of circuits operate simultaneously.

[Means for Solving the Problems] Output according to the present invention {The sofa circuit is an output buffer circuit including a main buffer circuit for driving a load and a pre-buffer circuit for driving this main buffer circuit, in which the output buffer circuit according to the present invention The hybrid buffer circuit is configured by connecting a plurality of unit buffers in parallel, and the active state of some of the unit buffers is controlled by an external control signal.

[Function] In the present invention, some of the unit buffers of the pre-buffer circuit can be made active or inactive by external control, so that the charging/discharging time of the main buffer circuit by the pre-buffer circuit is reduced. can be controlled.

Therefore, according to the present invention, by detecting the timing at which a large number of output buffer circuits turn on or off simultaneously and applying this as a control signal, it is possible to shift the switching timing of some of the output buffer circuits. Therefore, sudden changes in the output buffer circuit are alleviated, and noise can be suppressed.

[Embodiments] Next, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a part of a semiconductor integrated circuit according to a first embodiment of the present invention.

Input signals 81, 82, S3, from internal circuits (not shown),
S4 are delay adjustment circuits Gl. G2. The signals are input to the output buffer circuit Of, 02.03.04 of this embodiment via G3, G4 and input terminals 1.2, 3.4, respectively. Output buffer circuits 01 to 04 receive input signals 81 to S4, respectively.
are amplified to drive loads connected to output terminals 5, 6, and 7.8, respectively.

On the other hand, the input signals 81 to S4 are all input to the NOR circuit G5. NOR circuit G5 receives input signals S1 to S
4 are all L (low level potential), the control signal CS is set to H.
(high level potential).

This control signal CS is input to each output buffer circuit 01-04.

The output buffer circuits 01 to o4 all have the same configuration. Therefore, among these, output buffer circuit 0
Only the configuration of No. 1 is shown in FIG.

That is, the output buffer circuit 01 is configured by cascade-connecting a buffer circuit 9 and a main buffer circuit 1o. The prebuffer 1 circuit 9 is constructed by connecting two CMOS inverters as the unit buffer 1 in parallel.

One CMOS inverter is composed of a P-channel MOS transistor Q1 and an N-channel MOS transistor Q2, and the other CMOS inverter is composed of a P-channel MOS transistor Q3, Q4 and an N-channel MOS transistor.
It is composed of a transistor Q5.

Here, the transistor Q3 has the aforementioned control signal CS input to its gate, and selectively connects the CMOS inverter consisting of the transistors Q4 and Q5 to the power supply in accordance with the control signal Cs.

Next, the operation of the output buffer circuit configured as described above will be explained.

If all of the output buffer circuits 01 to 04 do not transition from H to L at the same time, for example, the input signals 81 to S3
simultaneously transitioned from H to L, but when the input signal S4 is fixed at H, the control signal CS maintains L, so
Transistor Q3 remains on. Therefore, when the input signals S1 to S3 change from H to L, a pair of CMOS inverters formed by transistors Ql and Q2 and transistors Q4 and Q5 change their output states from L to H, and the main buffer The circuit 10 is driven at high speed. Therefore, each output buffer circuit 01 to 03
simultaneously changes the output state.

On the other hand, when the input signals 81 to S4 all change from H to L at the same time, the control signal C S # (changes from L to H, changing the transistor Q3 from the on state to the off state) output from the NOR circuit G5. As a result, the inverter made up of transistors Q4 and Q5 becomes inactive, and as a result, the main buffer circuit 10 is made up of transistors Q1 and Q2.
It will be driven only by For this reason, the gate 1 of transistors Q6 and Q7 constituting the main buffer circuit 10
・The potential changes slowly from the edge to H, making it possible to prevent the generation of noise.

FIG. 2 is a diagram showing the configuration of an output buffer circuit according to a second embodiment of the present invention.

In this circuit, the buffer circuit 13 that drives the main buffer circuit 14 is different from the circuit in the previous embodiment. That is, in this embodiment, the buffer circuit 13 includes a P-channel MOS transistor Q8 and an N-channel MOS transistor Q8.
It is constructed by connecting in parallel a first CMOS inverter made up of an OS transistor Q9 and a second CMOS inverter made up of P-channel MOS transistors QIO, Qll and N-channel MOS transistors Q12 and Q13. Of these, in the second CMOS inverter, the gates of transistors QIO and Q13 are controlled by a control signal CS.

This circuit has the effect of preventing the generation of noise not only when the input signal changes from H to L, but also when it changes from L to H.

Note that the present invention is not limited to the above-mentioned embodiments. In the above embodiment, two unit buffer circuits are connected in parallel as a pre-buffer circuit, but a large number of unit buffer circuits are connected in parallel to create a unit buffer circuit that can operate sequentially according to the number of transitioning output buffer circuits. More detailed control such as reducing the number may be performed.

[Effects of the Invention] As explained above, the present invention makes it possible to control the driving ability of the pre-buffer circuit that drives the main buffer circuit when a large number of output buffer circuits operate simultaneously. It is possible to avoid sudden changes in the bath sofa portion, reduce noise generated, and reduce the occurrence of malfunctions caused by the noise.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an output buffer circuit according to a first embodiment of the present invention, FIG. 2 is a block diagram of an output buffer circuit according to a second embodiment of the present invention, and FIG. 3 is a block diagram of a conventional output buffer circuit. It is a block diagram of a circuit. 1-4. ti, 21; input terminal, S~8.12, 22;
Output terminal. fL 11, 2i; pre-buffer circuit,
1L top, Lij2Li; Main buffer circuit, 61~G
4; Delay adjustment circuit, G5; NOR circuit, Q1, Q3, Q
4, QB, Q8, QIO. Qll, Q16, Q18;P
channel MOS} transistor, Q2. Q5, Q7, Q9
, Q12, Q13, Q15. Q17, Q19; N-channel MOS} Transistors 1 to 4: Input terminals 5 to 8: Output terminals i = Pre-buffer circuit iQ = Main buffer circuit 01 to 04: Output vanofer circuit G1 to G4: Delay adjustment circuit G5: NOR circuit Application People NEC IC Microcomputer System Co., Ltd.

Claims (1)

[Claims] (1) In an output buffer circuit including a main buffer circuit that drives a load and a pre-buffer circuit that drives the main buffer circuit, the pre-buffer circuit includes:
1. An output buffer circuit comprising a plurality of unit buffers connected in parallel, and wherein the active state of some of the unit buffers is controlled by an external control signal.